/*
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* Copyright © 2014 Broadcom
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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/** @file vc4_tiling.c
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*
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* Handles information about the VC4 tiling formats, and loading and storing
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* from them.
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*
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* Texture mipmap levels on VC4 are (with the exception of 32-bit RGBA raster
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* textures for scanout) stored as groups of microtiles. If the texture is at
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* least 4x4 microtiles (utiles), then those microtiles are arranged in a sort
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* of Hilbert-fractal-ish layout (T), otherwise the microtiles are in raster
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* order (LT).
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*
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* Specifically, the T format has:
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*
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* - 64b utiles of pixels in a raster-order grid according to cpp. It's 4x4
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* pixels at 32 bit depth.
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*
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* - 1k subtiles made of a 4x4 raster-order grid of 64b utiles (so usually
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* 16x16 pixels).
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*
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* - 4k tiles made of a 2x2 grid of 1k subtiles (so usually 32x32 pixels). On
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* even 4k tile rows, they're arranged as (BL, TL, TR, BR), and on odd rows
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* they're (TR, BR, BL, TL), where bottom left is start of memory.
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*
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* - an image made of 4k tiles in rows either left-to-right (even rows of 4k
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* tiles) or right-to-left (odd rows of 4k tiles).
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*/
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#include "vc4_screen.h"
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#include "vc4_context.h"
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#include "vc4_tiling.h"
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/**
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* The texture unit decides what tiling format a particular miplevel is using
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* this function, so we lay out our miptrees accordingly.
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*/
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bool
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vc4_size_is_lt(uint32_t width, uint32_t height, int cpp)
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{
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return (width <= 4 * vc4_utile_width(cpp) ||
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height <= 4 * vc4_utile_height(cpp));
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}
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static void
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check_box_utile_alignment(const struct pipe_box *box, int cpp)
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{
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assert(!(box->x & (vc4_utile_width(cpp) - 1)));
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assert(!(box->y & (vc4_utile_height(cpp) - 1)));
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assert(!(box->width & (vc4_utile_width(cpp) - 1)));
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assert(!(box->height & (vc4_utile_height(cpp) - 1)));
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}
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/**
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* Takes a utile x and y (and the number of utiles of width of the image) and
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* returns the offset to the utile within a VC4_TILING_FORMAT_TF image.
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*/
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static uint32_t
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t_utile_address(uint32_t utile_x, uint32_t utile_y,
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uint32_t utile_stride)
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{
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/* T images have to be aligned to 8 utiles (4x4 subtiles, which are
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* 2x2 in a 4k tile).
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*/
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assert(!(utile_stride & 7));
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uint32_t tile_stride = utile_stride >> 3;
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/* 4k tile offsets. */
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uint32_t tile_x = utile_x >> 3;
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uint32_t tile_y = utile_y >> 3;
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bool odd_tile_y = tile_y & 1;
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/* Odd lines of 4k tiles go right-to-left. */
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if (odd_tile_y)
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tile_x = tile_stride - tile_x - 1;
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uint32_t tile_offset = 4096 * (tile_y * tile_stride + tile_x);
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uint32_t stile_x = (utile_x >> 2) & 1;
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uint32_t stile_y = (utile_y >> 2) & 1;
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uint32_t stile_index = (stile_y << 1) + stile_x;
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static const uint32_t odd_stile_map[4] = {2, 1, 3, 0};
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static const uint32_t even_stile_map[4] = {0, 3, 1, 2};
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uint32_t stile_offset = 1024 * (odd_tile_y ?
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odd_stile_map[stile_index] :
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even_stile_map[stile_index]);
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/* This function no longer handles the utile offset within a subtile.
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* Walking subtiles is the job of the LT image handler.
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*/
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assert(!(utile_x & 3) && !(utile_y & 3));
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#if 0
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fprintf(stderr, "utile %d,%d -> %d + %d + %d (stride %d,%d) = %d\n",
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utile_x, utile_y,
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tile_offset, stile_offset, utile_offset,
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utile_stride, tile_stride,
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tile_offset + stile_offset + utile_offset);
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#endif
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return tile_offset + stile_offset;
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}
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/**
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* Loads or stores a T texture image by breaking it down into subtiles
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* (1024-byte, 4x4-utile) sub-images that we can use the LT tiling functions
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* on.
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*/
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static inline void
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vc4_t_image_helper(void *gpu, uint32_t gpu_stride,
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void *cpu, uint32_t cpu_stride,
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int cpp, const struct pipe_box *box,
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bool to_cpu)
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{
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uint32_t utile_w = vc4_utile_width(cpp);
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uint32_t utile_h = vc4_utile_height(cpp);
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uint32_t utile_w_shift = ffs(utile_w) - 1;
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uint32_t utile_h_shift = ffs(utile_h) - 1;
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uint32_t stile_w = 4 * utile_w;
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uint32_t stile_h = 4 * utile_h;
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assert(stile_w * stile_h * cpp == 1024);
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uint32_t utile_stride = gpu_stride / cpp / utile_w;
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uint32_t x1 = box->x;
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uint32_t y1 = box->y;
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uint32_t x2 = box->x + box->width;
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uint32_t y2 = box->y + box->height;
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struct pipe_box partial_box;
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uint32_t gpu_lt_stride = stile_w * cpp;
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for (uint32_t y = y1; y < y2; y = align(y + 1, stile_h)) {
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partial_box.y = y & (stile_h - 1);
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partial_box.height = MIN2(y2 - y, stile_h - partial_box.y);
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uint32_t cpu_offset = 0;
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for (uint32_t x = x1; x < x2; x = align(x + 1, stile_w)) {
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partial_box.x = x & (stile_w - 1);
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partial_box.width = MIN2(x2 - x,
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stile_w - partial_box.x);
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/* The dst offset we want is the start of this
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* subtile
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*/
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uint32_t gpu_offset =
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t_utile_address((x >> utile_w_shift) & ~0x3,
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(y >> utile_h_shift) & ~0x3,
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utile_stride);
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if (to_cpu) {
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vc4_load_lt_image(cpu + cpu_offset,
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cpu_stride,
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gpu + gpu_offset,
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gpu_lt_stride,
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cpp, &partial_box);
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} else {
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vc4_store_lt_image(gpu + gpu_offset,
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gpu_lt_stride,
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cpu + cpu_offset,
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cpu_stride,
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cpp, &partial_box);
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}
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cpu_offset += partial_box.width * cpp;
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}
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cpu += cpu_stride * partial_box.height;
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}
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}
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static void
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vc4_store_t_image(void *dst, uint32_t dst_stride,
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void *src, uint32_t src_stride,
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int cpp, const struct pipe_box *box)
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{
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vc4_t_image_helper(dst, dst_stride,
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src, src_stride,
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cpp, box, false);
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}
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static void
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vc4_load_t_image(void *dst, uint32_t dst_stride,
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void *src, uint32_t src_stride,
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int cpp, const struct pipe_box *box)
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{
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vc4_t_image_helper(src, src_stride,
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dst, dst_stride,
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cpp, box, true);
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}
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/**
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* Loads pixel data from the start (microtile-aligned) box in \p src to the
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* start of \p dst according to the given tiling format.
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*/
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void
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vc4_load_tiled_image(void *dst, uint32_t dst_stride,
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void *src, uint32_t src_stride,
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uint8_t tiling_format, int cpp,
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const struct pipe_box *box)
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{
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check_box_utile_alignment(box, cpp);
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if (tiling_format == VC4_TILING_FORMAT_LT) {
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vc4_load_lt_image(dst, dst_stride,
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src, src_stride,
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cpp, box);
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} else {
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assert(tiling_format == VC4_TILING_FORMAT_T);
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vc4_load_t_image(dst, dst_stride,
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src, src_stride,
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cpp, box);
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}
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}
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/**
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* Stores pixel data from the start of \p src into a (microtile-aligned) box in
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* \p dst according to the given tiling format.
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*/
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void
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vc4_store_tiled_image(void *dst, uint32_t dst_stride,
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void *src, uint32_t src_stride,
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uint8_t tiling_format, int cpp,
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const struct pipe_box *box)
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{
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check_box_utile_alignment(box, cpp);
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if (tiling_format == VC4_TILING_FORMAT_LT) {
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vc4_store_lt_image(dst, dst_stride,
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src, src_stride,
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cpp, box);
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} else {
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assert(tiling_format == VC4_TILING_FORMAT_T);
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vc4_store_t_image(dst, dst_stride,
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src, src_stride,
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cpp, box);
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}
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}
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