/*
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* Copyright © 2014 Broadcom
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include "util/ralloc.h"
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#include "util/register_allocate.h"
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#include "vc4_context.h"
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#include "vc4_qir.h"
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#include "vc4_qpu.h"
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#define QPU_R(file, index) { QPU_MUX_##file, index }
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static const struct qpu_reg vc4_regs[] = {
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{ QPU_MUX_R0, 0},
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{ QPU_MUX_R1, 0},
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{ QPU_MUX_R2, 0},
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{ QPU_MUX_R3, 0},
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{ QPU_MUX_R4, 0},
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QPU_R(A, 0),
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QPU_R(B, 0),
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QPU_R(A, 1),
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QPU_R(B, 1),
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QPU_R(A, 2),
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QPU_R(B, 2),
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QPU_R(A, 3),
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QPU_R(B, 3),
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QPU_R(A, 4),
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QPU_R(B, 4),
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QPU_R(A, 5),
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QPU_R(B, 5),
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QPU_R(A, 6),
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QPU_R(B, 6),
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QPU_R(A, 7),
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QPU_R(B, 7),
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QPU_R(A, 8),
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QPU_R(B, 8),
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QPU_R(A, 9),
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QPU_R(B, 9),
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QPU_R(A, 10),
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QPU_R(B, 10),
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QPU_R(A, 11),
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QPU_R(B, 11),
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QPU_R(A, 12),
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QPU_R(B, 12),
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QPU_R(A, 13),
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QPU_R(B, 13),
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QPU_R(A, 14),
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QPU_R(B, 14),
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QPU_R(A, 15),
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QPU_R(B, 15),
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QPU_R(A, 16),
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QPU_R(B, 16),
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QPU_R(A, 17),
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QPU_R(B, 17),
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QPU_R(A, 18),
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QPU_R(B, 18),
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QPU_R(A, 19),
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QPU_R(B, 19),
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QPU_R(A, 20),
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QPU_R(B, 20),
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QPU_R(A, 21),
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QPU_R(B, 21),
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QPU_R(A, 22),
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QPU_R(B, 22),
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QPU_R(A, 23),
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QPU_R(B, 23),
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QPU_R(A, 24),
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QPU_R(B, 24),
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QPU_R(A, 25),
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QPU_R(B, 25),
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QPU_R(A, 26),
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QPU_R(B, 26),
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QPU_R(A, 27),
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QPU_R(B, 27),
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QPU_R(A, 28),
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QPU_R(B, 28),
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QPU_R(A, 29),
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QPU_R(B, 29),
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QPU_R(A, 30),
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QPU_R(B, 30),
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QPU_R(A, 31),
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QPU_R(B, 31),
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};
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#define ACC_INDEX 0
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#define ACC_COUNT 5
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#define AB_INDEX (ACC_INDEX + ACC_COUNT)
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#define AB_COUNT 64
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static void
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vc4_alloc_reg_set(struct vc4_context *vc4)
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{
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assert(vc4_regs[AB_INDEX].addr == 0);
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assert(vc4_regs[AB_INDEX + 1].addr == 0);
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STATIC_ASSERT(ARRAY_SIZE(vc4_regs) == AB_INDEX + 64);
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if (vc4->regs)
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return;
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vc4->regs = ra_alloc_reg_set(vc4, ARRAY_SIZE(vc4_regs), true);
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/* The physical regfiles split us into two classes, with [0] being the
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* whole space and [1] being the bottom half (for threaded fragment
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* shaders).
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*/
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for (int i = 0; i < 2; i++) {
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vc4->reg_class_any[i] = ra_alloc_reg_class(vc4->regs);
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vc4->reg_class_a_or_b[i] = ra_alloc_reg_class(vc4->regs);
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vc4->reg_class_a_or_b_or_acc[i] = ra_alloc_reg_class(vc4->regs);
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vc4->reg_class_r4_or_a[i] = ra_alloc_reg_class(vc4->regs);
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vc4->reg_class_a[i] = ra_alloc_reg_class(vc4->regs);
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}
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vc4->reg_class_r0_r3 = ra_alloc_reg_class(vc4->regs);
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/* r0-r3 */
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for (uint32_t i = ACC_INDEX; i < ACC_INDEX + 4; i++) {
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ra_class_add_reg(vc4->regs, vc4->reg_class_r0_r3, i);
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ra_class_add_reg(vc4->regs, vc4->reg_class_a_or_b_or_acc[0], i);
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ra_class_add_reg(vc4->regs, vc4->reg_class_a_or_b_or_acc[1], i);
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}
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/* R4 gets a special class because it can't be written as a general
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* purpose register. (it's TMU_NOSWAP as a write address).
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*/
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for (int i = 0; i < 2; i++) {
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ra_class_add_reg(vc4->regs, vc4->reg_class_r4_or_a[i],
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ACC_INDEX + 4);
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ra_class_add_reg(vc4->regs, vc4->reg_class_any[i],
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ACC_INDEX + 4);
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}
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/* A/B */
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for (uint32_t i = AB_INDEX; i < AB_INDEX + 64; i ++) {
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/* Reserve ra14/rb14 for spilling fixup_raddr_conflict() in
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* vc4_qpu_emit.c
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*/
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if (vc4_regs[i].addr == 14)
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continue;
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ra_class_add_reg(vc4->regs, vc4->reg_class_any[0], i);
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ra_class_add_reg(vc4->regs, vc4->reg_class_a_or_b[0], i);
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ra_class_add_reg(vc4->regs, vc4->reg_class_a_or_b_or_acc[0], i);
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if (vc4_regs[i].addr < 16) {
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ra_class_add_reg(vc4->regs, vc4->reg_class_any[1], i);
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ra_class_add_reg(vc4->regs, vc4->reg_class_a_or_b[1], i);
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ra_class_add_reg(vc4->regs, vc4->reg_class_a_or_b_or_acc[1], i);
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}
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/* A only */
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if (((i - AB_INDEX) & 1) == 0) {
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ra_class_add_reg(vc4->regs, vc4->reg_class_a[0], i);
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ra_class_add_reg(vc4->regs, vc4->reg_class_r4_or_a[0], i);
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if (vc4_regs[i].addr < 16) {
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ra_class_add_reg(vc4->regs,
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vc4->reg_class_a[1], i);
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ra_class_add_reg(vc4->regs,
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vc4->reg_class_r4_or_a[1], i);
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}
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}
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}
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ra_set_finalize(vc4->regs, NULL);
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}
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struct node_to_temp_map {
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uint32_t temp;
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uint32_t priority;
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};
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static int
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node_to_temp_priority(const void *in_a, const void *in_b)
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{
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const struct node_to_temp_map *a = in_a;
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const struct node_to_temp_map *b = in_b;
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return a->priority - b->priority;
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}
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#define CLASS_BIT_A (1 << 0)
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#define CLASS_BIT_B (1 << 1)
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#define CLASS_BIT_R4 (1 << 2)
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#define CLASS_BIT_R0_R3 (1 << 4)
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struct vc4_ra_select_callback_data {
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uint32_t next_acc;
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uint32_t next_ab;
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};
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static unsigned int
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vc4_ra_select_callback(struct ra_graph *g, BITSET_WORD *regs, void *data)
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{
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struct vc4_ra_select_callback_data *vc4_ra = data;
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/* If r4 is available, always choose it -- few other things can go
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* there, and choosing anything else means inserting a mov.
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*/
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if (BITSET_TEST(regs, ACC_INDEX + 4))
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return ACC_INDEX + 4;
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/* Choose an accumulator if possible (no delay between write and
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* read), but round-robin through them to give post-RA instruction
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* selection more options.
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*/
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for (int i = 0; i < ACC_COUNT; i++) {
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int acc_off = (vc4_ra->next_acc + i) % ACC_COUNT;
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int acc = ACC_INDEX + acc_off;
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if (BITSET_TEST(regs, acc)) {
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vc4_ra->next_acc = acc_off + 1;
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return acc;
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}
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}
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for (int i = 0; i < AB_COUNT; i++) {
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int ab_off = (vc4_ra->next_ab + i) % AB_COUNT;
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int ab = AB_INDEX + ab_off;
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if (BITSET_TEST(regs, ab)) {
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vc4_ra->next_ab = ab_off + 1;
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return ab;
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}
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}
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unreachable("RA must pass us at least one possible reg.");
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}
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/**
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* Returns a mapping from QFILE_TEMP indices to struct qpu_regs.
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*
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* The return value should be freed by the caller.
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*/
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struct qpu_reg *
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vc4_register_allocate(struct vc4_context *vc4, struct vc4_compile *c)
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{
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struct node_to_temp_map map[c->num_temps];
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uint32_t temp_to_node[c->num_temps];
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uint8_t class_bits[c->num_temps];
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struct qpu_reg *temp_registers = calloc(c->num_temps,
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sizeof(*temp_registers));
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struct vc4_ra_select_callback_data callback_data = {
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.next_acc = 0,
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.next_ab = 0,
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};
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/* If things aren't ever written (undefined values), just read from
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* r0.
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*/
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for (uint32_t i = 0; i < c->num_temps; i++)
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temp_registers[i] = qpu_rn(0);
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vc4_alloc_reg_set(vc4);
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struct ra_graph *g = ra_alloc_interference_graph(vc4->regs,
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c->num_temps);
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/* Compute the live ranges so we can figure out interference. */
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qir_calculate_live_intervals(c);
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ra_set_select_reg_callback(g, vc4_ra_select_callback, &callback_data);
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for (uint32_t i = 0; i < c->num_temps; i++) {
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map[i].temp = i;
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map[i].priority = c->temp_end[i] - c->temp_start[i];
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}
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qsort(map, c->num_temps, sizeof(map[0]), node_to_temp_priority);
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for (uint32_t i = 0; i < c->num_temps; i++) {
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temp_to_node[map[i].temp] = i;
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}
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/* Figure out our register classes and preallocated registers. We
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* start with any temp being able to be in any file, then instructions
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* incrementally remove bits that the temp definitely can't be in.
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*/
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memset(class_bits,
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CLASS_BIT_A | CLASS_BIT_B | CLASS_BIT_R4 | CLASS_BIT_R0_R3,
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sizeof(class_bits));
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int ip = 0;
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qir_for_each_inst_inorder(inst, c) {
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if (qir_writes_r4(inst)) {
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/* This instruction writes r4 (and optionally moves
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* its result to a temp), so nothing else can be
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* stored in r4 across it.
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*/
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for (int i = 0; i < c->num_temps; i++) {
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if (c->temp_start[i] < ip && c->temp_end[i] > ip)
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class_bits[i] &= ~CLASS_BIT_R4;
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}
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/* If we're doing a conditional write of something
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* writing R4 (math, tex results), then make sure that
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* we store in a temp so that we actually
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* conditionally move the result.
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*/
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if (inst->cond != QPU_COND_ALWAYS)
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class_bits[inst->dst.index] &= ~CLASS_BIT_R4;
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} else {
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/* R4 can't be written as a general purpose
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* register. (it's TMU_NOSWAP as a write address).
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*/
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if (inst->dst.file == QFILE_TEMP)
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class_bits[inst->dst.index] &= ~CLASS_BIT_R4;
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}
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switch (inst->op) {
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case QOP_FRAG_Z:
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ra_set_node_reg(g, temp_to_node[inst->dst.index],
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AB_INDEX + QPU_R_FRAG_PAYLOAD_ZW * 2 + 1);
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break;
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case QOP_FRAG_W:
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ra_set_node_reg(g, temp_to_node[inst->dst.index],
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AB_INDEX + QPU_R_FRAG_PAYLOAD_ZW * 2);
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break;
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case QOP_ROT_MUL:
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assert(inst->src[0].file == QFILE_TEMP);
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class_bits[inst->src[0].index] &= CLASS_BIT_R0_R3;
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break;
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case QOP_THRSW:
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/* All accumulators are invalidated across a thread
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* switch.
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*/
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for (int i = 0; i < c->num_temps; i++) {
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if (c->temp_start[i] < ip && c->temp_end[i] > ip)
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class_bits[i] &= ~(CLASS_BIT_R0_R3 |
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CLASS_BIT_R4);
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}
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break;
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default:
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break;
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}
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if (inst->dst.pack && !qir_is_mul(inst)) {
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/* The non-MUL pack flags require an A-file dst
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* register.
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*/
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class_bits[inst->dst.index] &= CLASS_BIT_A;
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}
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/* Apply restrictions for src unpacks. The integer unpacks
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* can only be done from regfile A, while float unpacks can be
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* either A or R4.
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*/
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for (int i = 0; i < qir_get_nsrc(inst); i++) {
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if (inst->src[i].file == QFILE_TEMP &&
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inst->src[i].pack) {
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if (qir_is_float_input(inst)) {
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class_bits[inst->src[i].index] &=
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CLASS_BIT_A | CLASS_BIT_R4;
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} else {
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class_bits[inst->src[i].index] &=
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CLASS_BIT_A;
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}
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}
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}
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ip++;
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}
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for (uint32_t i = 0; i < c->num_temps; i++) {
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int node = temp_to_node[i];
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switch (class_bits[i]) {
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case CLASS_BIT_A | CLASS_BIT_B | CLASS_BIT_R4 | CLASS_BIT_R0_R3:
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ra_set_node_class(g, node,
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vc4->reg_class_any[c->fs_threaded]);
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break;
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case CLASS_BIT_A | CLASS_BIT_B:
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ra_set_node_class(g, node,
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vc4->reg_class_a_or_b[c->fs_threaded]);
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break;
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case CLASS_BIT_A | CLASS_BIT_B | CLASS_BIT_R0_R3:
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ra_set_node_class(g, node,
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vc4->reg_class_a_or_b_or_acc[c->fs_threaded]);
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break;
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case CLASS_BIT_A | CLASS_BIT_R4:
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ra_set_node_class(g, node,
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vc4->reg_class_r4_or_a[c->fs_threaded]);
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break;
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case CLASS_BIT_A:
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ra_set_node_class(g, node,
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vc4->reg_class_a[c->fs_threaded]);
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break;
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case CLASS_BIT_R0_R3:
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ra_set_node_class(g, node, vc4->reg_class_r0_r3);
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break;
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default:
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/* DDX/DDY used across thread switched might get us
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* here.
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*/
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if (c->fs_threaded) {
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c->failed = true;
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free(temp_registers);
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return NULL;
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}
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fprintf(stderr, "temp %d: bad class bits: 0x%x\n",
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i, class_bits[i]);
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abort();
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break;
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}
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}
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for (uint32_t i = 0; i < c->num_temps; i++) {
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for (uint32_t j = i + 1; j < c->num_temps; j++) {
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if (!(c->temp_start[i] >= c->temp_end[j] ||
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c->temp_start[j] >= c->temp_end[i])) {
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ra_add_node_interference(g,
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temp_to_node[i],
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temp_to_node[j]);
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}
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}
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}
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bool ok = ra_allocate(g);
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if (!ok) {
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if (!c->fs_threaded) {
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fprintf(stderr, "Failed to register allocate:\n");
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qir_dump(c);
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}
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c->failed = true;
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free(temp_registers);
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return NULL;
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}
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for (uint32_t i = 0; i < c->num_temps; i++) {
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temp_registers[i] = vc4_regs[ra_get_node_reg(g, temp_to_node[i])];
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/* If the value's never used, just write to the NOP register
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* for clarity in debug output.
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*/
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if (c->temp_start[i] == c->temp_end[i])
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temp_registers[i] = qpu_ra(QPU_W_NOP);
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}
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ralloc_free(g);
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return temp_registers;
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}
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