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/*
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* Copyright © 2014 Broadcom
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include "vc4_qpu.h"
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static void
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fail_instr(uint64_t inst, const char *msg)
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{
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fprintf(stderr, "vc4_qpu_validate: %s: ", msg);
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vc4_qpu_disasm(&inst, 1);
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fprintf(stderr, "\n");
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abort();
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}
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static bool
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writes_reg(uint64_t inst, uint32_t w)
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{
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return (QPU_GET_FIELD(inst, QPU_WADDR_ADD) == w ||
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QPU_GET_FIELD(inst, QPU_WADDR_MUL) == w);
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}
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static bool
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_reads_reg(uint64_t inst, uint32_t r, bool ignore_a, bool ignore_b)
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{
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struct {
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uint32_t mux, addr;
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} src_regs[] = {
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{ QPU_GET_FIELD(inst, QPU_ADD_A) },
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{ QPU_GET_FIELD(inst, QPU_ADD_B) },
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{ QPU_GET_FIELD(inst, QPU_MUL_A) },
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{ QPU_GET_FIELD(inst, QPU_MUL_B) },
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};
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/* Branches only reference raddr_a (no mux), and we don't use that
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* feature of branching.
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*/
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if (QPU_GET_FIELD(inst, QPU_SIG) == QPU_SIG_BRANCH)
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return false;
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/* Load immediates don't read any registers. */
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if (QPU_GET_FIELD(inst, QPU_SIG) == QPU_SIG_LOAD_IMM)
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return false;
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for (int i = 0; i < ARRAY_SIZE(src_regs); i++) {
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if (!ignore_a &&
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src_regs[i].mux == QPU_MUX_A &&
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(QPU_GET_FIELD(inst, QPU_RADDR_A) == r))
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return true;
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if (!ignore_b &&
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QPU_GET_FIELD(inst, QPU_SIG) != QPU_SIG_SMALL_IMM &&
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src_regs[i].mux == QPU_MUX_B &&
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(QPU_GET_FIELD(inst, QPU_RADDR_B) == r))
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return true;
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}
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return false;
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}
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static bool
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reads_reg(uint64_t inst, uint32_t r)
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{
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return _reads_reg(inst, r, false, false);
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}
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static bool
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reads_a_reg(uint64_t inst, uint32_t r)
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{
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return _reads_reg(inst, r, false, true);
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}
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static bool
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reads_b_reg(uint64_t inst, uint32_t r)
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{
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return _reads_reg(inst, r, true, false);
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}
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static bool
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writes_sfu(uint64_t inst)
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{
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return (writes_reg(inst, QPU_W_SFU_RECIP) ||
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writes_reg(inst, QPU_W_SFU_RECIPSQRT) ||
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writes_reg(inst, QPU_W_SFU_EXP) ||
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writes_reg(inst, QPU_W_SFU_LOG));
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}
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/**
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* Checks for the instruction restrictions from page 37 ("Summary of
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* Instruction Restrictions").
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*/
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void
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vc4_qpu_validate(uint64_t *insts, uint32_t num_inst)
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{
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bool scoreboard_locked = false;
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bool threaded = false;
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/* We don't want to do validation in release builds, but we want to
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* keep compiling the validation code to make sure it doesn't get
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* broken.
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*/
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#ifndef DEBUG
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return;
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#endif
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for (int i = 0; i < num_inst; i++) {
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uint64_t inst = insts[i];
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uint32_t sig = QPU_GET_FIELD(inst, QPU_SIG);
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if (sig != QPU_SIG_PROG_END) {
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if (qpu_inst_is_tlb(inst))
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scoreboard_locked = true;
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if (sig == QPU_SIG_THREAD_SWITCH ||
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sig == QPU_SIG_LAST_THREAD_SWITCH) {
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threaded = true;
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}
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continue;
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}
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/* "The Thread End instruction must not write to either physical
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* regfile A or B."
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*/
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if (QPU_GET_FIELD(inst, QPU_WADDR_ADD) < 32 ||
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QPU_GET_FIELD(inst, QPU_WADDR_MUL) < 32) {
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fail_instr(inst, "write to phys reg in thread end");
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}
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/* Can't trigger an implicit wait on scoreboard in the program
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* end instruction.
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*/
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if (qpu_inst_is_tlb(inst) && !scoreboard_locked)
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fail_instr(inst, "implicit sb wait in program end");
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/* Two delay slots will be executed. */
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assert(i + 2 <= num_inst);
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for (int j = i; j < i + 2; j++) {
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/* "The last three instructions of any program
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* (Thread End plus the following two delay-slot
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* instructions) must not do varyings read, uniforms
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* read or any kind of VPM, VDR, or VDW read or
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* write."
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*/
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if (writes_reg(insts[j], QPU_W_VPM) ||
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reads_reg(insts[j], QPU_R_VARY) ||
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reads_reg(insts[j], QPU_R_UNIF) ||
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reads_reg(insts[j], QPU_R_VPM)) {
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fail_instr(insts[j], "last 3 instructions "
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"using fixed functions");
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}
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/* "The Thread End instruction and the following two
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* delay slot instructions must not write or read
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* address 14 in either regfile A or B."
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*/
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if (writes_reg(insts[j], 14) ||
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reads_reg(insts[j], 14)) {
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fail_instr(insts[j], "last 3 instructions "
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"must not use r14");
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}
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}
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/* "The final program instruction (the second delay slot
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* instruction) must not do a TLB Z write."
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*/
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if (writes_reg(insts[i + 2], QPU_W_TLB_Z)) {
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fail_instr(insts[i + 2], "final instruction doing "
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"Z write");
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}
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}
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/* "A scoreboard wait must not occur in the first two instructions of
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* a fragment shader. This is either the explicit Wait for Scoreboard
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* signal or an implicit wait with the first tile-buffer read or
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* write instruction."
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*/
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for (int i = 0; i < 2; i++) {
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uint64_t inst = insts[i];
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if (qpu_inst_is_tlb(inst))
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fail_instr(inst, "sb wait in first two insts");
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}
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/* "If TMU_NOSWAP is written, the write must be three instructions
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* before the first TMU write instruction. For example, if
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* TMU_NOSWAP is written in the first shader instruction, the first
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* TMU write cannot occur before the 4th shader instruction."
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*/
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int last_tmu_noswap = -10;
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for (int i = 0; i < num_inst; i++) {
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uint64_t inst = insts[i];
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if ((i - last_tmu_noswap) <= 3 &&
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(writes_reg(inst, QPU_W_TMU0_S) ||
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writes_reg(inst, QPU_W_TMU1_S))) {
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fail_instr(inst, "TMU write too soon after TMU_NOSWAP");
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}
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if (writes_reg(inst, QPU_W_TMU_NOSWAP))
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last_tmu_noswap = i;
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}
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/* "An instruction must not read from a location in physical regfile A
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* or B that was written to by the previous instruction."
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*/
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for (int i = 0; i < num_inst - 1; i++) {
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uint64_t inst = insts[i];
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uint32_t add_waddr = QPU_GET_FIELD(inst, QPU_WADDR_ADD);
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uint32_t mul_waddr = QPU_GET_FIELD(inst, QPU_WADDR_MUL);
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uint32_t waddr_a, waddr_b;
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if (inst & QPU_WS) {
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waddr_b = add_waddr;
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waddr_a = mul_waddr;
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} else {
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waddr_a = add_waddr;
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waddr_b = mul_waddr;
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}
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if ((waddr_a < 32 && reads_a_reg(insts[i + 1], waddr_a)) ||
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(waddr_b < 32 && reads_b_reg(insts[i + 1], waddr_b))) {
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fail_instr(insts[i + 1],
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"Reads physical reg too soon after write");
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}
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}
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/* "After an SFU lookup instruction, accumulator r4 must not be read
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* in the following two instructions. Any other instruction that
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* results in r4 being written (that is, TMU read, TLB read, SFU
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* lookup) cannot occur in the two instructions following an SFU
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* lookup."
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*/
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int last_sfu_inst = -10;
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for (int i = 0; i < num_inst - 1; i++) {
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uint64_t inst = insts[i];
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uint32_t sig = QPU_GET_FIELD(inst, QPU_SIG);
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if (i - last_sfu_inst <= 2 &&
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(writes_sfu(inst) ||
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sig == QPU_SIG_LOAD_TMU0 ||
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sig == QPU_SIG_LOAD_TMU1 ||
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sig == QPU_SIG_COLOR_LOAD)) {
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fail_instr(inst, "R4 write too soon after SFU write");
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}
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if (writes_sfu(inst))
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last_sfu_inst = i;
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}
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for (int i = 0; i < num_inst - 1; i++) {
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uint64_t inst = insts[i];
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if (QPU_GET_FIELD(inst, QPU_SIG) == QPU_SIG_SMALL_IMM &&
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QPU_GET_FIELD(inst, QPU_SMALL_IMM) >=
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QPU_SMALL_IMM_MUL_ROT) {
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uint32_t mux_a = QPU_GET_FIELD(inst, QPU_MUL_A);
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uint32_t mux_b = QPU_GET_FIELD(inst, QPU_MUL_B);
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/* "The full horizontal vector rotate is only
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* available when both of the mul ALU input arguments
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* are taken from accumulators r0-r3."
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*/
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if (mux_a > QPU_MUX_R3 || mux_b > QPU_MUX_R3) {
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fail_instr(inst,
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"MUL rotate using non-accumulator "
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"input");
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}
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if (QPU_GET_FIELD(inst, QPU_SMALL_IMM) ==
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QPU_SMALL_IMM_MUL_ROT) {
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/* "An instruction that does a vector rotate
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* by r5 must not immediately follow an
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* instruction that writes to r5."
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*/
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if (writes_reg(insts[i - 1], QPU_W_ACC5)) {
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fail_instr(inst,
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"vector rotate by r5 "
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"immediately after r5 write");
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}
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}
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/* "An instruction that does a vector rotate must not
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* immediately follow an instruction that writes to the
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* accumulator that is being rotated."
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*/
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if (writes_reg(insts[i - 1], QPU_W_ACC0 + mux_a) ||
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writes_reg(insts[i - 1], QPU_W_ACC0 + mux_b)) {
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fail_instr(inst,
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"vector rotate of value "
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"written in previous instruction");
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}
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}
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}
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/* "An instruction that does a vector rotate must not immediately
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* follow an instruction that writes to the accumulator that is being
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* rotated.
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*
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* XXX: TODO.
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*/
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/* "After an instruction that does a TLB Z write, the multisample mask
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* must not be read as an instruction input argument in the following
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* two instruction. The TLB Z write instruction can, however, be
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* followed immediately by a TLB color write."
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*/
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for (int i = 0; i < num_inst - 1; i++) {
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uint64_t inst = insts[i];
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if (writes_reg(inst, QPU_W_TLB_Z) &&
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(reads_a_reg(insts[i + 1], QPU_R_MS_REV_FLAGS) ||
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reads_a_reg(insts[i + 2], QPU_R_MS_REV_FLAGS))) {
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fail_instr(inst, "TLB Z write followed by MS mask read");
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}
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}
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/*
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* "A single instruction can only perform a maximum of one of the
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* following closely coupled peripheral accesses in a single
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* instruction: TMU write, TMU read, TLB write, TLB read, TLB
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* combined color read and write, SFU write, Mutex read or Semaphore
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* access."
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*/
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for (int i = 0; i < num_inst - 1; i++) {
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uint64_t inst = insts[i];
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if (qpu_num_sf_accesses(inst) > 1)
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fail_instr(inst, "Single instruction writes SFU twice");
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}
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/* "The uniform base pointer can be written (from SIMD element 0) by
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* the processor to reset the stream, there must be at least two
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* nonuniform-accessing instructions following a pointer change
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* before uniforms can be accessed once more."
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*/
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int last_unif_pointer_update = -3;
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for (int i = 0; i < num_inst; i++) {
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uint64_t inst = insts[i];
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uint32_t waddr_add = QPU_GET_FIELD(inst, QPU_WADDR_ADD);
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uint32_t waddr_mul = QPU_GET_FIELD(inst, QPU_WADDR_MUL);
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if (reads_reg(inst, QPU_R_UNIF) &&
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i - last_unif_pointer_update <= 2) {
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fail_instr(inst,
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"uniform read too soon after pointer update");
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}
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if (waddr_add == QPU_W_UNIFORMS_ADDRESS ||
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waddr_mul == QPU_W_UNIFORMS_ADDRESS)
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last_unif_pointer_update = i;
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}
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if (threaded) {
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bool last_thrsw_found = false;
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bool scoreboard_locked = false;
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int tex_samples_outstanding = 0;
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int last_tex_samples_outstanding = 0;
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int thrsw_ip = -1;
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for (int i = 0; i < num_inst; i++) {
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uint64_t inst = insts[i];
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uint32_t sig = QPU_GET_FIELD(inst, QPU_SIG);
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if (i == thrsw_ip) {
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/* In order to get texture results back in the
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* correct order, before a new thrsw we have
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* to read all the texture results from before
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* the previous thrsw.
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*
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* FIXME: Is collecting the remaining results
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* during the delay slots OK, or should we do
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* this at THRSW signal time?
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*/
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if (last_tex_samples_outstanding != 0) {
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fail_instr(inst, "THRSW with texture "
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"results from the previous "
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"THRSW still in the FIFO.");
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}
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last_tex_samples_outstanding =
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tex_samples_outstanding;
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tex_samples_outstanding = 0;
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}
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if (qpu_inst_is_tlb(inst))
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scoreboard_locked = true;
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switch (sig) {
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case QPU_SIG_THREAD_SWITCH:
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case QPU_SIG_LAST_THREAD_SWITCH:
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/* No thread switching with the scoreboard
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* locked. Doing so means we may deadlock
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* when the other thread tries to lock
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* scoreboard.
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*/
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if (scoreboard_locked) {
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fail_instr(inst, "THRSW with the "
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"scoreboard locked.");
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}
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/* No thread switching after lthrsw, since
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* lthrsw means that we get delayed until the
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* other shader is ready for us to terminate.
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*/
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if (last_thrsw_found) {
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fail_instr(inst, "THRSW after a "
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"previous LTHRSW");
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}
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if (sig == QPU_SIG_LAST_THREAD_SWITCH)
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last_thrsw_found = true;
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/* No THRSW while we already have a THRSW
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* queued.
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*/
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if (i < thrsw_ip) {
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fail_instr(inst,
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"THRSW with a THRSW queued.");
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}
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thrsw_ip = i + 3;
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break;
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case QPU_SIG_LOAD_TMU0:
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case QPU_SIG_LOAD_TMU1:
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if (last_tex_samples_outstanding == 0) {
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fail_instr(inst, "TMU load with nothing "
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"in the results fifo from "
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"the previous THRSW.");
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}
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last_tex_samples_outstanding--;
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break;
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}
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uint32_t waddr_add = QPU_GET_FIELD(inst, QPU_WADDR_ADD);
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uint32_t waddr_mul = QPU_GET_FIELD(inst, QPU_WADDR_MUL);
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if (waddr_add == QPU_W_TMU0_S ||
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waddr_add == QPU_W_TMU1_S ||
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waddr_mul == QPU_W_TMU0_S ||
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waddr_mul == QPU_W_TMU1_S) {
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tex_samples_outstanding++;
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}
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}
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}
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}
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