/*
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* Copyright © 2014 Broadcom
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include <inttypes.h>
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#include "vc4_context.h"
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#include "vc4_qir.h"
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#include "vc4_qpu.h"
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#include "util/ralloc.h"
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static void
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vc4_dump_program(struct vc4_compile *c)
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{
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fprintf(stderr, "%s prog %d/%d QPU:\n",
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qir_get_stage_name(c->stage),
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c->program_id, c->variant_id);
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for (int i = 0; i < c->qpu_inst_count; i++) {
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fprintf(stderr, "0x%016"PRIx64" ", c->qpu_insts[i]);
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vc4_qpu_disasm(&c->qpu_insts[i], 1);
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fprintf(stderr, "\n");
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}
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fprintf(stderr, "\n");
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}
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static void
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queue(struct qblock *block, uint64_t inst)
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{
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struct queued_qpu_inst *q = rzalloc(block, struct queued_qpu_inst);
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q->inst = inst;
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list_addtail(&q->link, &block->qpu_inst_list);
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}
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static uint64_t *
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last_inst(struct qblock *block)
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{
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struct queued_qpu_inst *q =
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(struct queued_qpu_inst *)block->qpu_inst_list.prev;
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return &q->inst;
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}
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static void
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set_last_cond_add(struct qblock *block, uint32_t cond)
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{
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*last_inst(block) = qpu_set_cond_add(*last_inst(block), cond);
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}
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static void
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set_last_cond_mul(struct qblock *block, uint32_t cond)
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{
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*last_inst(block) = qpu_set_cond_mul(*last_inst(block), cond);
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}
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/**
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* Some special registers can be read from either file, which lets us resolve
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* raddr conflicts without extra MOVs.
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*/
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static bool
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swap_file(struct qpu_reg *src)
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{
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switch (src->addr) {
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case QPU_R_UNIF:
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case QPU_R_VARY:
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if (src->mux == QPU_MUX_SMALL_IMM) {
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return false;
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} else {
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if (src->mux == QPU_MUX_A)
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src->mux = QPU_MUX_B;
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else
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src->mux = QPU_MUX_A;
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return true;
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}
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default:
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return false;
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}
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}
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/**
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* Sets up the VPM read FIFO before we do any VPM read.
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*
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* VPM reads (vertex attribute input) and VPM writes (varyings output) from
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* the QPU reuse the VRI (varying interpolation) block's FIFOs to talk to the
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* VPM block. In the VS/CS (unlike in the FS), the block starts out
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* uninitialized, and you need to emit setup to the block before any VPM
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* reads/writes.
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*
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* VRI has a FIFO in each direction, with each FIFO able to hold four
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* 32-bit-per-vertex values. VPM reads come through the read FIFO and VPM
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* writes go through the write FIFO. The read/write setup values from QPU go
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* through the write FIFO as well, with a sideband signal indicating that
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* they're setup values. Once a read setup reaches the other side of the
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* FIFO, the VPM block will start asynchronously reading vertex attributes and
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* filling the read FIFO -- that way hopefully the QPU doesn't have to block
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* on reads later.
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*
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* VPM read setup can configure 16 32-bit-per-vertex values to be read at a
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* time, which is 4 vec4s. If more than that is being read (since we support
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* 8 vec4 vertex attributes), then multiple read setup writes need to be done.
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*
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* The existence of the FIFO makes it seem like you should be able to emit
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* both setups for the 5-8 attribute cases and then do all the attribute
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* reads. However, once the setup value makes it to the other end of the
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* write FIFO, it will immediately update the VPM block's setup register.
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* That updated setup register would be used for read FIFO fills from then on,
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* breaking whatever remaining VPM values were supposed to be read into the
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* read FIFO from the previous attribute set.
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*
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* As a result, we need to emit the read setup, pull every VPM read value from
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* that setup, and only then emit the second setup if applicable.
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*/
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static void
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setup_for_vpm_read(struct vc4_compile *c, struct qblock *block)
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{
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if (c->num_inputs_in_fifo) {
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c->num_inputs_in_fifo--;
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return;
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}
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c->num_inputs_in_fifo = MIN2(c->num_inputs_remaining, 16);
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queue(block,
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qpu_load_imm_ui(qpu_vrsetup(),
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c->vpm_read_offset |
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0x00001a00 |
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((c->num_inputs_in_fifo & 0xf) << 20)));
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c->num_inputs_remaining -= c->num_inputs_in_fifo;
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c->vpm_read_offset += c->num_inputs_in_fifo;
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c->num_inputs_in_fifo--;
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}
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/**
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* This is used to resolve the fact that we might register-allocate two
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* different operands of an instruction to the same physical register file
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* even though instructions have only one field for the register file source
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* address.
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*
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* In that case, we need to move one to a temporary that can be used in the
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* instruction, instead. We reserve ra14/rb14 for this purpose.
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*/
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static void
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fixup_raddr_conflict(struct qblock *block,
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struct qpu_reg dst,
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struct qpu_reg *src0, struct qpu_reg *src1,
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struct qinst *inst, uint64_t *unpack)
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{
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uint32_t mux0 = src0->mux == QPU_MUX_SMALL_IMM ? QPU_MUX_B : src0->mux;
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uint32_t mux1 = src1->mux == QPU_MUX_SMALL_IMM ? QPU_MUX_B : src1->mux;
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if (mux0 <= QPU_MUX_R5 ||
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mux0 != mux1 ||
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(src0->addr == src1->addr &&
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src0->mux == src1->mux)) {
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return;
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}
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if (swap_file(src0) || swap_file(src1))
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return;
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if (mux0 == QPU_MUX_A) {
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/* Make sure we use the same type of MOV as the instruction,
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* in case of unpacks.
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*/
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if (qir_is_float_input(inst))
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queue(block, qpu_a_FMAX(qpu_rb(14), *src0, *src0));
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else
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queue(block, qpu_a_MOV(qpu_rb(14), *src0));
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/* If we had an unpack on this A-file source, we need to put
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* it into this MOV, not into the later move from regfile B.
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*/
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if (inst->src[0].pack) {
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*last_inst(block) |= *unpack;
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*unpack = 0;
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}
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*src0 = qpu_rb(14);
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} else {
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queue(block, qpu_a_MOV(qpu_ra(14), *src0));
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*src0 = qpu_ra(14);
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}
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}
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static void
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set_last_dst_pack(struct qblock *block, struct qinst *inst)
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{
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MAYBE_UNUSED bool had_pm = *last_inst(block) & QPU_PM;
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MAYBE_UNUSED bool had_ws = *last_inst(block) & QPU_WS;
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MAYBE_UNUSED uint32_t unpack = QPU_GET_FIELD(*last_inst(block), QPU_UNPACK);
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if (!inst->dst.pack)
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return;
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*last_inst(block) |= QPU_SET_FIELD(inst->dst.pack, QPU_PACK);
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if (qir_is_mul(inst)) {
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assert(!unpack || had_pm);
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*last_inst(block) |= QPU_PM;
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} else {
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assert(!unpack || !had_pm);
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assert(!had_ws); /* dst must be a-file to pack. */
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}
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}
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static void
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handle_r4_qpu_write(struct qblock *block, struct qinst *qinst,
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struct qpu_reg dst)
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{
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if (dst.mux != QPU_MUX_R4) {
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queue(block, qpu_a_MOV(dst, qpu_r4()));
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set_last_cond_add(block, qinst->cond);
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} else {
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assert(qinst->cond == QPU_COND_ALWAYS);
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if (qinst->sf)
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queue(block, qpu_a_MOV(qpu_ra(QPU_W_NOP), qpu_r4()));
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}
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}
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static void
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vc4_generate_code_block(struct vc4_compile *c,
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struct qblock *block,
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struct qpu_reg *temp_registers)
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{
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int last_vpm_read_index = -1;
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qir_for_each_inst(qinst, block) {
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#if 0
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fprintf(stderr, "translating qinst to qpu: ");
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qir_dump_inst(qinst);
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fprintf(stderr, "\n");
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#endif
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static const struct {
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uint32_t op;
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} translate[] = {
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#define A(name) [QOP_##name] = {QPU_A_##name}
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#define M(name) [QOP_##name] = {QPU_M_##name}
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A(FADD),
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A(FSUB),
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A(FMIN),
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A(FMAX),
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A(FMINABS),
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A(FMAXABS),
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A(FTOI),
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A(ITOF),
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A(ADD),
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A(SUB),
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A(SHL),
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A(SHR),
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A(ASR),
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A(MIN),
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A(MAX),
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A(AND),
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A(OR),
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A(XOR),
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A(NOT),
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M(FMUL),
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M(V8MULD),
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M(V8MIN),
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M(V8MAX),
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M(V8ADDS),
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M(V8SUBS),
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M(MUL24),
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/* If we replicate src[0] out to src[1], this works
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* out the same as a MOV.
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*/
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[QOP_MOV] = { QPU_A_OR },
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[QOP_FMOV] = { QPU_A_FMAX },
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[QOP_MMOV] = { QPU_M_V8MIN },
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[QOP_MIN_NOIMM] = { QPU_A_MIN },
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};
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uint64_t unpack = 0;
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struct qpu_reg src[ARRAY_SIZE(qinst->src)];
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for (int i = 0; i < qir_get_nsrc(qinst); i++) {
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int index = qinst->src[i].index;
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switch (qinst->src[i].file) {
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case QFILE_NULL:
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case QFILE_LOAD_IMM:
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src[i] = qpu_rn(0);
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break;
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case QFILE_TEMP:
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src[i] = temp_registers[index];
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if (qinst->src[i].pack) {
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assert(!unpack ||
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unpack == qinst->src[i].pack);
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unpack = QPU_SET_FIELD(qinst->src[i].pack,
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QPU_UNPACK);
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if (src[i].mux == QPU_MUX_R4)
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unpack |= QPU_PM;
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}
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break;
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case QFILE_UNIF:
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src[i] = qpu_unif();
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break;
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case QFILE_VARY:
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src[i] = qpu_vary();
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break;
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case QFILE_SMALL_IMM:
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src[i].mux = QPU_MUX_SMALL_IMM;
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src[i].addr = qpu_encode_small_immediate(qinst->src[i].index);
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/* This should only have returned a valid
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* small immediate field, not ~0 for failure.
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*/
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assert(src[i].addr <= 47);
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break;
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case QFILE_VPM:
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setup_for_vpm_read(c, block);
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assert((int)qinst->src[i].index >=
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last_vpm_read_index);
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(void)last_vpm_read_index;
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last_vpm_read_index = qinst->src[i].index;
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src[i] = qpu_ra(QPU_R_VPM);
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break;
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case QFILE_FRAG_X:
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src[i] = qpu_ra(QPU_R_XY_PIXEL_COORD);
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break;
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case QFILE_FRAG_Y:
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src[i] = qpu_rb(QPU_R_XY_PIXEL_COORD);
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break;
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case QFILE_FRAG_REV_FLAG:
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src[i] = qpu_rb(QPU_R_MS_REV_FLAGS);
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break;
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case QFILE_QPU_ELEMENT:
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src[i] = qpu_ra(QPU_R_ELEM_QPU);
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break;
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case QFILE_TLB_COLOR_WRITE:
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case QFILE_TLB_COLOR_WRITE_MS:
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case QFILE_TLB_Z_WRITE:
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case QFILE_TLB_STENCIL_SETUP:
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case QFILE_TEX_S:
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case QFILE_TEX_S_DIRECT:
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case QFILE_TEX_T:
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case QFILE_TEX_R:
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case QFILE_TEX_B:
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unreachable("bad qir src file");
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}
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}
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struct qpu_reg dst;
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switch (qinst->dst.file) {
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case QFILE_NULL:
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dst = qpu_ra(QPU_W_NOP);
|
break;
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case QFILE_TEMP:
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dst = temp_registers[qinst->dst.index];
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break;
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case QFILE_VPM:
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dst = qpu_ra(QPU_W_VPM);
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break;
|
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case QFILE_TLB_COLOR_WRITE:
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dst = qpu_tlbc();
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break;
|
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case QFILE_TLB_COLOR_WRITE_MS:
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dst = qpu_tlbc_ms();
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break;
|
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case QFILE_TLB_Z_WRITE:
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dst = qpu_ra(QPU_W_TLB_Z);
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break;
|
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case QFILE_TLB_STENCIL_SETUP:
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dst = qpu_ra(QPU_W_TLB_STENCIL_SETUP);
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break;
|
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case QFILE_TEX_S:
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case QFILE_TEX_S_DIRECT:
|
dst = qpu_rb(QPU_W_TMU0_S);
|
break;
|
|
case QFILE_TEX_T:
|
dst = qpu_rb(QPU_W_TMU0_T);
|
break;
|
|
case QFILE_TEX_R:
|
dst = qpu_rb(QPU_W_TMU0_R);
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break;
|
|
case QFILE_TEX_B:
|
dst = qpu_rb(QPU_W_TMU0_B);
|
break;
|
|
case QFILE_VARY:
|
case QFILE_UNIF:
|
case QFILE_SMALL_IMM:
|
case QFILE_LOAD_IMM:
|
case QFILE_FRAG_X:
|
case QFILE_FRAG_Y:
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case QFILE_FRAG_REV_FLAG:
|
case QFILE_QPU_ELEMENT:
|
assert(!"not reached");
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break;
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}
|
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MAYBE_UNUSED bool handled_qinst_cond = false;
|
|
switch (qinst->op) {
|
case QOP_RCP:
|
case QOP_RSQ:
|
case QOP_EXP2:
|
case QOP_LOG2:
|
switch (qinst->op) {
|
case QOP_RCP:
|
queue(block, qpu_a_MOV(qpu_rb(QPU_W_SFU_RECIP),
|
src[0]) | unpack);
|
break;
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case QOP_RSQ:
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queue(block, qpu_a_MOV(qpu_rb(QPU_W_SFU_RECIPSQRT),
|
src[0]) | unpack);
|
break;
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case QOP_EXP2:
|
queue(block, qpu_a_MOV(qpu_rb(QPU_W_SFU_EXP),
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src[0]) | unpack);
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break;
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case QOP_LOG2:
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queue(block, qpu_a_MOV(qpu_rb(QPU_W_SFU_LOG),
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src[0]) | unpack);
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break;
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default:
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abort();
|
}
|
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handle_r4_qpu_write(block, qinst, dst);
|
handled_qinst_cond = true;
|
|
break;
|
|
case QOP_LOAD_IMM:
|
assert(qinst->src[0].file == QFILE_LOAD_IMM);
|
queue(block, qpu_load_imm_ui(dst, qinst->src[0].index));
|
break;
|
|
case QOP_LOAD_IMM_U2:
|
queue(block, qpu_load_imm_u2(dst, qinst->src[0].index));
|
break;
|
|
case QOP_LOAD_IMM_I2:
|
queue(block, qpu_load_imm_i2(dst, qinst->src[0].index));
|
break;
|
|
case QOP_ROT_MUL:
|
/* Rotation at the hardware level occurs on the inputs
|
* to the MUL unit, and they must be accumulators in
|
* order to have the time necessary to move things.
|
*/
|
assert(src[0].mux <= QPU_MUX_R3);
|
|
queue(block,
|
qpu_m_rot(dst, src[0], qinst->src[1].index -
|
QPU_SMALL_IMM_MUL_ROT) | unpack);
|
set_last_cond_mul(block, qinst->cond);
|
handled_qinst_cond = true;
|
set_last_dst_pack(block, qinst);
|
break;
|
|
case QOP_MS_MASK:
|
src[1] = qpu_ra(QPU_R_MS_REV_FLAGS);
|
fixup_raddr_conflict(block, dst, &src[0], &src[1],
|
qinst, &unpack);
|
queue(block, qpu_a_AND(qpu_ra(QPU_W_MS_FLAGS),
|
src[0], src[1]) | unpack);
|
break;
|
|
case QOP_FRAG_Z:
|
case QOP_FRAG_W:
|
/* QOP_FRAG_Z/W don't emit instructions, just allocate
|
* the register to the Z/W payload.
|
*/
|
break;
|
|
case QOP_TLB_COLOR_READ:
|
queue(block, qpu_NOP());
|
*last_inst(block) = qpu_set_sig(*last_inst(block),
|
QPU_SIG_COLOR_LOAD);
|
handle_r4_qpu_write(block, qinst, dst);
|
handled_qinst_cond = true;
|
break;
|
|
case QOP_VARY_ADD_C:
|
queue(block, qpu_a_FADD(dst, src[0], qpu_r5()) | unpack);
|
break;
|
|
|
case QOP_TEX_RESULT:
|
queue(block, qpu_NOP());
|
*last_inst(block) = qpu_set_sig(*last_inst(block),
|
QPU_SIG_LOAD_TMU0);
|
handle_r4_qpu_write(block, qinst, dst);
|
handled_qinst_cond = true;
|
break;
|
|
case QOP_THRSW:
|
queue(block, qpu_NOP());
|
*last_inst(block) = qpu_set_sig(*last_inst(block),
|
QPU_SIG_THREAD_SWITCH);
|
c->last_thrsw = last_inst(block);
|
break;
|
|
case QOP_BRANCH:
|
/* The branch target will be updated at QPU scheduling
|
* time.
|
*/
|
queue(block, (qpu_branch(qinst->cond, 0) |
|
QPU_BRANCH_REL));
|
handled_qinst_cond = true;
|
break;
|
|
case QOP_UNIFORMS_RESET:
|
fixup_raddr_conflict(block, dst, &src[0], &src[1],
|
qinst, &unpack);
|
|
queue(block, qpu_a_ADD(qpu_ra(QPU_W_UNIFORMS_ADDRESS),
|
src[0], src[1]));
|
break;
|
|
default:
|
assert(qinst->op < ARRAY_SIZE(translate));
|
assert(translate[qinst->op].op != 0); /* NOPs */
|
|
/* Skip emitting the MOV if it's a no-op. */
|
if (qir_is_raw_mov(qinst) &&
|
dst.mux == src[0].mux && dst.addr == src[0].addr) {
|
break;
|
}
|
|
/* If we have only one source, put it in the second
|
* argument slot as well so that we don't take up
|
* another raddr just to get unused data.
|
*/
|
if (qir_get_non_sideband_nsrc(qinst) == 1)
|
src[1] = src[0];
|
|
fixup_raddr_conflict(block, dst, &src[0], &src[1],
|
qinst, &unpack);
|
|
if (qir_is_mul(qinst)) {
|
queue(block, qpu_m_alu2(translate[qinst->op].op,
|
dst,
|
src[0], src[1]) | unpack);
|
set_last_cond_mul(block, qinst->cond);
|
} else {
|
queue(block, qpu_a_alu2(translate[qinst->op].op,
|
dst,
|
src[0], src[1]) | unpack);
|
set_last_cond_add(block, qinst->cond);
|
}
|
handled_qinst_cond = true;
|
set_last_dst_pack(block, qinst);
|
|
break;
|
}
|
|
assert(qinst->cond == QPU_COND_ALWAYS ||
|
handled_qinst_cond);
|
|
if (qinst->sf)
|
*last_inst(block) |= QPU_SF;
|
}
|
}
|
|
void
|
vc4_generate_code(struct vc4_context *vc4, struct vc4_compile *c)
|
{
|
struct qblock *start_block = list_first_entry(&c->blocks,
|
struct qblock, link);
|
|
struct qpu_reg *temp_registers = vc4_register_allocate(vc4, c);
|
if (!temp_registers)
|
return;
|
|
switch (c->stage) {
|
case QSTAGE_VERT:
|
case QSTAGE_COORD:
|
c->num_inputs_remaining = c->num_inputs;
|
queue(start_block, qpu_load_imm_ui(qpu_vwsetup(), 0x00001a00));
|
break;
|
case QSTAGE_FRAG:
|
break;
|
}
|
|
qir_for_each_block(block, c)
|
vc4_generate_code_block(c, block, temp_registers);
|
|
/* Switch the last SIG_THRSW instruction to SIG_LAST_THRSW.
|
*
|
* LAST_THRSW is a new signal in BCM2708B0 (including Raspberry Pi)
|
* that ensures that a later thread doesn't try to lock the scoreboard
|
* and terminate before an earlier-spawned thread on the same QPU, by
|
* delaying switching back to the later shader until earlier has
|
* finished. Otherwise, if the earlier thread was hitting the same
|
* quad, the scoreboard would deadlock.
|
*/
|
if (c->last_thrsw) {
|
assert(QPU_GET_FIELD(*c->last_thrsw, QPU_SIG) ==
|
QPU_SIG_THREAD_SWITCH);
|
*c->last_thrsw = ((*c->last_thrsw & ~QPU_SIG_MASK) |
|
QPU_SET_FIELD(QPU_SIG_LAST_THREAD_SWITCH,
|
QPU_SIG));
|
}
|
|
uint32_t cycles = qpu_schedule_instructions(c);
|
uint32_t inst_count_at_schedule_time = c->qpu_inst_count;
|
|
/* thread end can't have VPM write or read */
|
if (QPU_GET_FIELD(c->qpu_insts[c->qpu_inst_count - 1],
|
QPU_WADDR_ADD) == QPU_W_VPM ||
|
QPU_GET_FIELD(c->qpu_insts[c->qpu_inst_count - 1],
|
QPU_WADDR_MUL) == QPU_W_VPM ||
|
QPU_GET_FIELD(c->qpu_insts[c->qpu_inst_count - 1],
|
QPU_RADDR_A) == QPU_R_VPM ||
|
QPU_GET_FIELD(c->qpu_insts[c->qpu_inst_count - 1],
|
QPU_RADDR_B) == QPU_R_VPM) {
|
qpu_serialize_one_inst(c, qpu_NOP());
|
}
|
|
/* thread end can't have uniform read */
|
if (QPU_GET_FIELD(c->qpu_insts[c->qpu_inst_count - 1],
|
QPU_RADDR_A) == QPU_R_UNIF ||
|
QPU_GET_FIELD(c->qpu_insts[c->qpu_inst_count - 1],
|
QPU_RADDR_B) == QPU_R_UNIF) {
|
qpu_serialize_one_inst(c, qpu_NOP());
|
}
|
|
/* thread end can't have TLB operations */
|
if (qpu_inst_is_tlb(c->qpu_insts[c->qpu_inst_count - 1]))
|
qpu_serialize_one_inst(c, qpu_NOP());
|
|
/* Make sure there's no existing signal set (like for a small
|
* immediate)
|
*/
|
if (QPU_GET_FIELD(c->qpu_insts[c->qpu_inst_count - 1],
|
QPU_SIG) != QPU_SIG_NONE) {
|
qpu_serialize_one_inst(c, qpu_NOP());
|
}
|
|
c->qpu_insts[c->qpu_inst_count - 1] =
|
qpu_set_sig(c->qpu_insts[c->qpu_inst_count - 1],
|
QPU_SIG_PROG_END);
|
qpu_serialize_one_inst(c, qpu_NOP());
|
qpu_serialize_one_inst(c, qpu_NOP());
|
|
switch (c->stage) {
|
case QSTAGE_VERT:
|
case QSTAGE_COORD:
|
break;
|
case QSTAGE_FRAG:
|
c->qpu_insts[c->qpu_inst_count - 1] =
|
qpu_set_sig(c->qpu_insts[c->qpu_inst_count - 1],
|
QPU_SIG_SCOREBOARD_UNLOCK);
|
break;
|
}
|
|
cycles += c->qpu_inst_count - inst_count_at_schedule_time;
|
|
if (vc4_debug & VC4_DEBUG_SHADERDB) {
|
fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d estimated cycles\n",
|
qir_get_stage_name(c->stage),
|
c->program_id, c->variant_id,
|
cycles);
|
}
|
|
if (vc4_debug & VC4_DEBUG_QPU)
|
vc4_dump_program(c);
|
|
vc4_qpu_validate(c->qpu_insts, c->qpu_inst_count);
|
|
free(temp_registers);
|
}
|
