/*
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* Copyright © 2014 Broadcom
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#ifndef VC4_QPU_H
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#define VC4_QPU_H
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#include <stdio.h>
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#include <stdint.h>
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#include "util/u_math.h"
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#include "vc4_qpu_defines.h"
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struct vc4_compile;
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struct qpu_reg {
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enum qpu_mux mux;
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uint8_t addr;
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};
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static inline struct qpu_reg
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qpu_rn(int n)
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{
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struct qpu_reg r = {
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QPU_MUX_R0 + n,
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0,
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};
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return r;
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}
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static inline struct qpu_reg
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qpu_ra(int addr)
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{
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struct qpu_reg r = {
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QPU_MUX_A,
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addr,
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};
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return r;
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}
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static inline struct qpu_reg
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qpu_rb(int addr)
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{
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struct qpu_reg r = {
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QPU_MUX_B,
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addr,
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};
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return r;
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}
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static inline struct qpu_reg
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qpu_vary()
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{
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struct qpu_reg r = {
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QPU_MUX_A,
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QPU_R_VARY,
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};
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return r;
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}
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static inline struct qpu_reg
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qpu_unif()
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{
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struct qpu_reg r = {
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QPU_MUX_A,
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QPU_R_UNIF,
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};
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return r;
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}
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static inline struct qpu_reg
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qpu_vrsetup()
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{
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return qpu_ra(QPU_W_VPMVCD_SETUP);
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}
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static inline struct qpu_reg
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qpu_vwsetup()
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{
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return qpu_rb(QPU_W_VPMVCD_SETUP);
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}
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static inline struct qpu_reg
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qpu_tlbc()
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{
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struct qpu_reg r = {
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QPU_MUX_A,
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QPU_W_TLB_COLOR_ALL,
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};
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return r;
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}
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static inline struct qpu_reg
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qpu_tlbc_ms()
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{
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struct qpu_reg r = {
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QPU_MUX_A,
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QPU_W_TLB_COLOR_MS,
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};
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return r;
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}
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static inline struct qpu_reg qpu_r0(void) { return qpu_rn(0); }
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static inline struct qpu_reg qpu_r1(void) { return qpu_rn(1); }
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static inline struct qpu_reg qpu_r2(void) { return qpu_rn(2); }
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static inline struct qpu_reg qpu_r3(void) { return qpu_rn(3); }
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static inline struct qpu_reg qpu_r4(void) { return qpu_rn(4); }
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static inline struct qpu_reg qpu_r5(void) { return qpu_rn(5); }
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uint64_t qpu_NOP(void) ATTRIBUTE_CONST;
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uint64_t qpu_a_MOV(struct qpu_reg dst, struct qpu_reg src) ATTRIBUTE_CONST;
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uint64_t qpu_m_MOV(struct qpu_reg dst, struct qpu_reg src) ATTRIBUTE_CONST;
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uint64_t qpu_a_alu2(enum qpu_op_add op, struct qpu_reg dst,
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struct qpu_reg src0, struct qpu_reg src1) ATTRIBUTE_CONST;
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uint64_t qpu_m_alu2(enum qpu_op_mul op, struct qpu_reg dst,
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struct qpu_reg src0, struct qpu_reg src1) ATTRIBUTE_CONST;
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uint64_t qpu_merge_inst(uint64_t a, uint64_t b) ATTRIBUTE_CONST;
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uint64_t qpu_load_imm_ui(struct qpu_reg dst, uint32_t val) ATTRIBUTE_CONST;
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uint64_t qpu_load_imm_u2(struct qpu_reg dst, uint32_t val) ATTRIBUTE_CONST;
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uint64_t qpu_load_imm_i2(struct qpu_reg dst, uint32_t val) ATTRIBUTE_CONST;
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uint64_t qpu_branch(uint32_t cond, uint32_t target) ATTRIBUTE_CONST;
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uint64_t qpu_set_sig(uint64_t inst, uint32_t sig) ATTRIBUTE_CONST;
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uint64_t qpu_set_cond_add(uint64_t inst, uint32_t cond) ATTRIBUTE_CONST;
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uint64_t qpu_set_cond_mul(uint64_t inst, uint32_t cond) ATTRIBUTE_CONST;
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uint32_t qpu_encode_small_immediate(uint32_t i) ATTRIBUTE_CONST;
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uint64_t qpu_m_rot(struct qpu_reg dst, struct qpu_reg src, int rot) ATTRIBUTE_CONST;
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bool qpu_waddr_is_tlb(uint32_t waddr) ATTRIBUTE_CONST;
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bool qpu_inst_is_tlb(uint64_t inst) ATTRIBUTE_CONST;
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int qpu_num_sf_accesses(uint64_t inst) ATTRIBUTE_CONST;
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void qpu_serialize_one_inst(struct vc4_compile *c, uint64_t inst);
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static inline enum qpu_cond
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qpu_cond_complement(enum qpu_cond cond)
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{
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return cond ^ 1;
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}
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static inline uint64_t
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qpu_load_imm_f(struct qpu_reg dst, float val)
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{
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return qpu_load_imm_ui(dst, fui(val));
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}
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#define A_ALU2(op) \
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static inline uint64_t \
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qpu_a_##op(struct qpu_reg dst, struct qpu_reg src0, struct qpu_reg src1) \
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{ \
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return qpu_a_alu2(QPU_A_##op, dst, src0, src1); \
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}
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#define M_ALU2(op) \
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static inline uint64_t \
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qpu_m_##op(struct qpu_reg dst, struct qpu_reg src0, struct qpu_reg src1) \
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{ \
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return qpu_m_alu2(QPU_M_##op, dst, src0, src1); \
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}
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#define A_ALU1(op) \
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static inline uint64_t \
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qpu_a_##op(struct qpu_reg dst, struct qpu_reg src0) \
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{ \
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return qpu_a_alu2(QPU_A_##op, dst, src0, src0); \
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}
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/*A_ALU2(NOP) */
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A_ALU2(FADD)
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A_ALU2(FSUB)
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A_ALU2(FMIN)
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A_ALU2(FMAX)
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A_ALU2(FMINABS)
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A_ALU2(FMAXABS)
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A_ALU1(FTOI)
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A_ALU1(ITOF)
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A_ALU2(ADD)
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A_ALU2(SUB)
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A_ALU2(SHR)
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A_ALU2(ASR)
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A_ALU2(ROR)
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A_ALU2(SHL)
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A_ALU2(MIN)
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A_ALU2(MAX)
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A_ALU2(AND)
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A_ALU2(OR)
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A_ALU2(XOR)
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A_ALU1(NOT)
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A_ALU1(CLZ)
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A_ALU2(V8ADDS)
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A_ALU2(V8SUBS)
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/* M_ALU2(NOP) */
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M_ALU2(FMUL)
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M_ALU2(MUL24)
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M_ALU2(V8MULD)
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M_ALU2(V8MIN)
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M_ALU2(V8MAX)
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M_ALU2(V8ADDS)
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M_ALU2(V8SUBS)
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void
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vc4_qpu_disasm(const uint64_t *instructions, int num_instructions);
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void
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vc4_qpu_disasm_pack_mul(FILE *out, uint32_t pack);
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void
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vc4_qpu_disasm_pack_a(FILE *out, uint32_t pack);
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void
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vc4_qpu_disasm_unpack(FILE *out, uint32_t pack);
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void
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vc4_qpu_validate(uint64_t *insts, uint32_t num_inst);
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void
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vc4_qpu_disasm_cond(FILE *out, uint32_t cond);
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void
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vc4_qpu_disasm_cond_branch(FILE *out, uint32_t cond);
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#endif /* VC4_QPU_H */
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