/*
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* Copyright © 2014 Broadcom
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include <stdbool.h>
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#include "util/ralloc.h"
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#include "vc4_qir.h"
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#include "vc4_qpu.h"
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#define QPU_MUX(mux, muxfield) \
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QPU_SET_FIELD(mux != QPU_MUX_SMALL_IMM ? mux : QPU_MUX_B, muxfield)
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static uint64_t
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set_src_raddr(uint64_t inst, struct qpu_reg src)
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{
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if (src.mux == QPU_MUX_A) {
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assert(QPU_GET_FIELD(inst, QPU_RADDR_A) == QPU_R_NOP ||
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QPU_GET_FIELD(inst, QPU_RADDR_A) == src.addr);
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return QPU_UPDATE_FIELD(inst, src.addr, QPU_RADDR_A);
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}
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if (src.mux == QPU_MUX_B) {
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assert((QPU_GET_FIELD(inst, QPU_RADDR_B) == QPU_R_NOP ||
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QPU_GET_FIELD(inst, QPU_RADDR_B) == src.addr) &&
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QPU_GET_FIELD(inst, QPU_SIG) != QPU_SIG_SMALL_IMM);
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return QPU_UPDATE_FIELD(inst, src.addr, QPU_RADDR_B);
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}
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if (src.mux == QPU_MUX_SMALL_IMM) {
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if (QPU_GET_FIELD(inst, QPU_SIG) == QPU_SIG_SMALL_IMM) {
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assert(QPU_GET_FIELD(inst, QPU_RADDR_B) == src.addr);
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} else {
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inst = qpu_set_sig(inst, QPU_SIG_SMALL_IMM);
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assert(QPU_GET_FIELD(inst, QPU_RADDR_B) == QPU_R_NOP);
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}
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return ((inst & ~QPU_RADDR_B_MASK) |
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QPU_SET_FIELD(src.addr, QPU_RADDR_B));
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}
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return inst;
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}
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uint64_t
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qpu_NOP()
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{
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uint64_t inst = 0;
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inst |= QPU_SET_FIELD(QPU_A_NOP, QPU_OP_ADD);
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inst |= QPU_SET_FIELD(QPU_M_NOP, QPU_OP_MUL);
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/* Note: These field values are actually non-zero */
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inst |= QPU_SET_FIELD(QPU_W_NOP, QPU_WADDR_ADD);
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inst |= QPU_SET_FIELD(QPU_W_NOP, QPU_WADDR_MUL);
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inst |= QPU_SET_FIELD(QPU_R_NOP, QPU_RADDR_A);
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inst |= QPU_SET_FIELD(QPU_R_NOP, QPU_RADDR_B);
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inst |= QPU_SET_FIELD(QPU_SIG_NONE, QPU_SIG);
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return inst;
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}
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static uint64_t
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qpu_a_dst(struct qpu_reg dst)
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{
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uint64_t inst = 0;
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if (dst.mux <= QPU_MUX_R5) {
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/* Translate the mux to the ACCn values. */
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inst |= QPU_SET_FIELD(32 + dst.mux, QPU_WADDR_ADD);
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} else {
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inst |= QPU_SET_FIELD(dst.addr, QPU_WADDR_ADD);
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if (dst.mux == QPU_MUX_B)
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inst |= QPU_WS;
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}
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return inst;
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}
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static uint64_t
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qpu_m_dst(struct qpu_reg dst)
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{
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uint64_t inst = 0;
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if (dst.mux <= QPU_MUX_R5) {
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/* Translate the mux to the ACCn values. */
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inst |= QPU_SET_FIELD(32 + dst.mux, QPU_WADDR_MUL);
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} else {
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inst |= QPU_SET_FIELD(dst.addr, QPU_WADDR_MUL);
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if (dst.mux == QPU_MUX_A)
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inst |= QPU_WS;
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}
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return inst;
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}
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uint64_t
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qpu_a_MOV(struct qpu_reg dst, struct qpu_reg src)
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{
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uint64_t inst = 0;
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inst |= QPU_SET_FIELD(QPU_SIG_NONE, QPU_SIG);
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inst |= QPU_SET_FIELD(QPU_A_OR, QPU_OP_ADD);
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inst |= QPU_SET_FIELD(QPU_R_NOP, QPU_RADDR_A);
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inst |= QPU_SET_FIELD(QPU_R_NOP, QPU_RADDR_B);
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inst |= qpu_a_dst(dst);
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inst |= QPU_SET_FIELD(QPU_COND_ALWAYS, QPU_COND_ADD);
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inst |= QPU_MUX(src.mux, QPU_ADD_A);
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inst |= QPU_MUX(src.mux, QPU_ADD_B);
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inst = set_src_raddr(inst, src);
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inst |= QPU_SET_FIELD(QPU_W_NOP, QPU_WADDR_MUL);
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return inst;
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}
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uint64_t
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qpu_m_MOV(struct qpu_reg dst, struct qpu_reg src)
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{
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uint64_t inst = 0;
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inst |= QPU_SET_FIELD(QPU_SIG_NONE, QPU_SIG);
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inst |= QPU_SET_FIELD(QPU_M_V8MIN, QPU_OP_MUL);
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inst |= QPU_SET_FIELD(QPU_R_NOP, QPU_RADDR_A);
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inst |= QPU_SET_FIELD(QPU_R_NOP, QPU_RADDR_B);
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inst |= qpu_m_dst(dst);
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inst |= QPU_SET_FIELD(QPU_COND_ALWAYS, QPU_COND_MUL);
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inst |= QPU_MUX(src.mux, QPU_MUL_A);
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inst |= QPU_MUX(src.mux, QPU_MUL_B);
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inst = set_src_raddr(inst, src);
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inst |= QPU_SET_FIELD(QPU_W_NOP, QPU_WADDR_ADD);
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return inst;
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}
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uint64_t
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qpu_load_imm_ui(struct qpu_reg dst, uint32_t val)
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{
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uint64_t inst = 0;
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inst |= qpu_a_dst(dst);
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inst |= QPU_SET_FIELD(QPU_W_NOP, QPU_WADDR_MUL);
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inst |= QPU_SET_FIELD(QPU_COND_ALWAYS, QPU_COND_ADD);
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inst |= QPU_SET_FIELD(QPU_COND_ALWAYS, QPU_COND_MUL);
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inst |= QPU_SET_FIELD(QPU_SIG_LOAD_IMM, QPU_SIG);
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inst |= val;
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return inst;
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}
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uint64_t
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qpu_load_imm_u2(struct qpu_reg dst, uint32_t val)
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{
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return qpu_load_imm_ui(dst, val) | QPU_SET_FIELD(QPU_LOAD_IMM_MODE_U2,
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QPU_LOAD_IMM_MODE);
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}
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uint64_t
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qpu_load_imm_i2(struct qpu_reg dst, uint32_t val)
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{
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return qpu_load_imm_ui(dst, val) | QPU_SET_FIELD(QPU_LOAD_IMM_MODE_I2,
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QPU_LOAD_IMM_MODE);
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}
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uint64_t
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qpu_branch(uint32_t cond, uint32_t target)
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{
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uint64_t inst = 0;
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inst |= qpu_a_dst(qpu_ra(QPU_W_NOP));
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inst |= qpu_m_dst(qpu_rb(QPU_W_NOP));
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inst |= QPU_SET_FIELD(cond, QPU_BRANCH_COND);
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inst |= QPU_SET_FIELD(QPU_SIG_BRANCH, QPU_SIG);
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inst |= QPU_SET_FIELD(target, QPU_BRANCH_TARGET);
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return inst;
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}
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uint64_t
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qpu_a_alu2(enum qpu_op_add op,
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struct qpu_reg dst, struct qpu_reg src0, struct qpu_reg src1)
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{
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uint64_t inst = 0;
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inst |= QPU_SET_FIELD(QPU_SIG_NONE, QPU_SIG);
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inst |= QPU_SET_FIELD(op, QPU_OP_ADD);
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inst |= QPU_SET_FIELD(QPU_R_NOP, QPU_RADDR_A);
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inst |= QPU_SET_FIELD(QPU_R_NOP, QPU_RADDR_B);
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inst |= qpu_a_dst(dst);
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inst |= QPU_SET_FIELD(QPU_COND_ALWAYS, QPU_COND_ADD);
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inst |= QPU_MUX(src0.mux, QPU_ADD_A);
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inst = set_src_raddr(inst, src0);
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inst |= QPU_MUX(src1.mux, QPU_ADD_B);
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inst = set_src_raddr(inst, src1);
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inst |= QPU_SET_FIELD(QPU_W_NOP, QPU_WADDR_MUL);
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return inst;
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}
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uint64_t
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qpu_m_alu2(enum qpu_op_mul op,
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struct qpu_reg dst, struct qpu_reg src0, struct qpu_reg src1)
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{
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uint64_t inst = 0;
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inst |= QPU_SET_FIELD(QPU_SIG_NONE, QPU_SIG);
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inst |= QPU_SET_FIELD(op, QPU_OP_MUL);
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inst |= QPU_SET_FIELD(QPU_R_NOP, QPU_RADDR_A);
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inst |= QPU_SET_FIELD(QPU_R_NOP, QPU_RADDR_B);
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inst |= qpu_m_dst(dst);
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inst |= QPU_SET_FIELD(QPU_COND_ALWAYS, QPU_COND_MUL);
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inst |= QPU_MUX(src0.mux, QPU_MUL_A);
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inst = set_src_raddr(inst, src0);
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inst |= QPU_MUX(src1.mux, QPU_MUL_B);
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inst = set_src_raddr(inst, src1);
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inst |= QPU_SET_FIELD(QPU_W_NOP, QPU_WADDR_ADD);
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return inst;
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}
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uint64_t
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qpu_m_rot(struct qpu_reg dst, struct qpu_reg src0, int rot)
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{
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uint64_t inst = 0;
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inst = qpu_m_alu2(QPU_M_V8MIN, dst, src0, src0);
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inst = QPU_UPDATE_FIELD(inst, QPU_SIG_SMALL_IMM, QPU_SIG);
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inst = QPU_UPDATE_FIELD(inst, QPU_SMALL_IMM_MUL_ROT + rot,
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QPU_SMALL_IMM);
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return inst;
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}
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static bool
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merge_fields(uint64_t *merge,
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uint64_t a, uint64_t b,
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uint64_t mask, uint64_t ignore)
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{
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if ((a & mask) == ignore) {
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*merge = (*merge & ~mask) | (b & mask);
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} else if ((b & mask) == ignore) {
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*merge = (*merge & ~mask) | (a & mask);
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} else {
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if ((a & mask) != (b & mask))
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return false;
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}
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return true;
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}
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int
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qpu_num_sf_accesses(uint64_t inst)
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{
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int accesses = 0;
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static const uint32_t specials[] = {
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QPU_W_TLB_COLOR_MS,
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QPU_W_TLB_COLOR_ALL,
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QPU_W_TLB_Z,
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QPU_W_TMU0_S,
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QPU_W_TMU0_T,
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QPU_W_TMU0_R,
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QPU_W_TMU0_B,
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QPU_W_TMU1_S,
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QPU_W_TMU1_T,
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QPU_W_TMU1_R,
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QPU_W_TMU1_B,
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QPU_W_SFU_RECIP,
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QPU_W_SFU_RECIPSQRT,
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QPU_W_SFU_EXP,
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QPU_W_SFU_LOG,
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};
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uint32_t waddr_add = QPU_GET_FIELD(inst, QPU_WADDR_ADD);
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uint32_t waddr_mul = QPU_GET_FIELD(inst, QPU_WADDR_MUL);
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uint32_t raddr_a = QPU_GET_FIELD(inst, QPU_RADDR_A);
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uint32_t raddr_b = QPU_GET_FIELD(inst, QPU_RADDR_B);
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for (int j = 0; j < ARRAY_SIZE(specials); j++) {
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if (waddr_add == specials[j])
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accesses++;
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if (waddr_mul == specials[j])
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accesses++;
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}
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if (raddr_a == QPU_R_MUTEX_ACQUIRE)
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accesses++;
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if (raddr_b == QPU_R_MUTEX_ACQUIRE &&
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QPU_GET_FIELD(inst, QPU_SIG) != QPU_SIG_SMALL_IMM)
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accesses++;
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/* XXX: semaphore, combined color read/write? */
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switch (QPU_GET_FIELD(inst, QPU_SIG)) {
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case QPU_SIG_COLOR_LOAD:
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case QPU_SIG_COLOR_LOAD_END:
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case QPU_SIG_LOAD_TMU0:
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case QPU_SIG_LOAD_TMU1:
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accesses++;
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}
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return accesses;
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}
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static bool
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qpu_waddr_ignores_ws(uint32_t waddr)
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{
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switch(waddr) {
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case QPU_W_ACC0:
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case QPU_W_ACC1:
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case QPU_W_ACC2:
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case QPU_W_ACC3:
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case QPU_W_NOP:
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case QPU_W_TLB_Z:
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case QPU_W_TLB_COLOR_MS:
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case QPU_W_TLB_COLOR_ALL:
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case QPU_W_TLB_ALPHA_MASK:
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case QPU_W_VPM:
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case QPU_W_SFU_RECIP:
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case QPU_W_SFU_RECIPSQRT:
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case QPU_W_SFU_EXP:
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case QPU_W_SFU_LOG:
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case QPU_W_TMU0_S:
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case QPU_W_TMU0_T:
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case QPU_W_TMU0_R:
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case QPU_W_TMU0_B:
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case QPU_W_TMU1_S:
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case QPU_W_TMU1_T:
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case QPU_W_TMU1_R:
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case QPU_W_TMU1_B:
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return true;
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}
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return false;
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}
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static void
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swap_ra_file_mux_helper(uint64_t *merge, uint64_t *a, uint32_t mux_shift)
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{
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uint64_t mux_mask = (uint64_t)0x7 << mux_shift;
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uint64_t mux_a_val = (uint64_t)QPU_MUX_A << mux_shift;
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uint64_t mux_b_val = (uint64_t)QPU_MUX_B << mux_shift;
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if ((*a & mux_mask) == mux_a_val) {
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*a = (*a & ~mux_mask) | mux_b_val;
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*merge = (*merge & ~mux_mask) | mux_b_val;
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}
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}
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static bool
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try_swap_ra_file(uint64_t *merge, uint64_t *a, uint64_t *b)
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{
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uint32_t raddr_a_a = QPU_GET_FIELD(*a, QPU_RADDR_A);
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uint32_t raddr_a_b = QPU_GET_FIELD(*a, QPU_RADDR_B);
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uint32_t raddr_b_a = QPU_GET_FIELD(*b, QPU_RADDR_A);
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uint32_t raddr_b_b = QPU_GET_FIELD(*b, QPU_RADDR_B);
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if (raddr_a_b != QPU_R_NOP)
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return false;
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switch (raddr_a_a) {
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case QPU_R_UNIF:
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case QPU_R_VARY:
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break;
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default:
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return false;
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}
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if (!(*merge & QPU_PM) &&
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QPU_GET_FIELD(*merge, QPU_UNPACK) != QPU_UNPACK_NOP) {
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return false;
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}
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if (raddr_b_b != QPU_R_NOP &&
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raddr_b_b != raddr_a_a)
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return false;
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/* Move raddr A to B in instruction a. */
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*a = (*a & ~QPU_RADDR_A_MASK) | QPU_SET_FIELD(QPU_R_NOP, QPU_RADDR_A);
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*a = (*a & ~QPU_RADDR_B_MASK) | QPU_SET_FIELD(raddr_a_a, QPU_RADDR_B);
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*merge = QPU_UPDATE_FIELD(*merge, raddr_b_a, QPU_RADDR_A);
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*merge = QPU_UPDATE_FIELD(*merge, raddr_a_a, QPU_RADDR_B);
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swap_ra_file_mux_helper(merge, a, QPU_ADD_A_SHIFT);
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swap_ra_file_mux_helper(merge, a, QPU_ADD_B_SHIFT);
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swap_ra_file_mux_helper(merge, a, QPU_MUL_A_SHIFT);
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swap_ra_file_mux_helper(merge, a, QPU_MUL_B_SHIFT);
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return true;
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}
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static bool
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convert_mov(uint64_t *inst)
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{
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uint32_t add_a = QPU_GET_FIELD(*inst, QPU_ADD_A);
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uint32_t waddr_add = QPU_GET_FIELD(*inst, QPU_WADDR_ADD);
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uint32_t cond_add = QPU_GET_FIELD(*inst, QPU_COND_ADD);
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/* Is it a MOV? */
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if (QPU_GET_FIELD(*inst, QPU_OP_ADD) != QPU_A_OR ||
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(add_a != QPU_GET_FIELD(*inst, QPU_ADD_B))) {
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return false;
|
}
|
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if (QPU_GET_FIELD(*inst, QPU_SIG) != QPU_SIG_NONE)
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return false;
|
|
/* We could maybe support this in the .8888 and .8a-.8d cases. */
|
if (*inst & QPU_PM)
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return false;
|
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*inst = QPU_UPDATE_FIELD(*inst, QPU_A_NOP, QPU_OP_ADD);
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*inst = QPU_UPDATE_FIELD(*inst, QPU_M_V8MIN, QPU_OP_MUL);
|
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*inst = QPU_UPDATE_FIELD(*inst, add_a, QPU_MUL_A);
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*inst = QPU_UPDATE_FIELD(*inst, add_a, QPU_MUL_B);
|
*inst = QPU_UPDATE_FIELD(*inst, QPU_MUX_R0, QPU_ADD_A);
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*inst = QPU_UPDATE_FIELD(*inst, QPU_MUX_R0, QPU_ADD_B);
|
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*inst = QPU_UPDATE_FIELD(*inst, waddr_add, QPU_WADDR_MUL);
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*inst = QPU_UPDATE_FIELD(*inst, QPU_W_NOP, QPU_WADDR_ADD);
|
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*inst = QPU_UPDATE_FIELD(*inst, cond_add, QPU_COND_MUL);
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*inst = QPU_UPDATE_FIELD(*inst, QPU_COND_NEVER, QPU_COND_ADD);
|
|
if (!qpu_waddr_ignores_ws(waddr_add))
|
*inst ^= QPU_WS;
|
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return true;
|
}
|
|
static bool
|
writes_a_file(uint64_t inst)
|
{
|
if (!(inst & QPU_WS))
|
return QPU_GET_FIELD(inst, QPU_WADDR_ADD) < 32;
|
else
|
return QPU_GET_FIELD(inst, QPU_WADDR_MUL) < 32;
|
}
|
|
static bool
|
reads_r4(uint64_t inst)
|
{
|
return (QPU_GET_FIELD(inst, QPU_ADD_A) == QPU_MUX_R4 ||
|
QPU_GET_FIELD(inst, QPU_ADD_B) == QPU_MUX_R4 ||
|
QPU_GET_FIELD(inst, QPU_MUL_A) == QPU_MUX_R4 ||
|
QPU_GET_FIELD(inst, QPU_MUL_B) == QPU_MUX_R4);
|
}
|
|
uint64_t
|
qpu_merge_inst(uint64_t a, uint64_t b)
|
{
|
uint64_t merge = a | b;
|
bool ok = true;
|
uint32_t a_sig = QPU_GET_FIELD(a, QPU_SIG);
|
uint32_t b_sig = QPU_GET_FIELD(b, QPU_SIG);
|
|
if (QPU_GET_FIELD(a, QPU_OP_ADD) != QPU_A_NOP &&
|
QPU_GET_FIELD(b, QPU_OP_ADD) != QPU_A_NOP) {
|
if (QPU_GET_FIELD(a, QPU_OP_MUL) != QPU_M_NOP ||
|
QPU_GET_FIELD(b, QPU_OP_MUL) != QPU_M_NOP ||
|
!(convert_mov(&a) || convert_mov(&b))) {
|
return 0;
|
} else {
|
merge = a | b;
|
}
|
}
|
|
if (QPU_GET_FIELD(a, QPU_OP_MUL) != QPU_M_NOP &&
|
QPU_GET_FIELD(b, QPU_OP_MUL) != QPU_M_NOP)
|
return 0;
|
|
if (qpu_num_sf_accesses(a) && qpu_num_sf_accesses(b))
|
return 0;
|
|
if (a_sig == QPU_SIG_LOAD_IMM ||
|
b_sig == QPU_SIG_LOAD_IMM ||
|
a_sig == QPU_SIG_SMALL_IMM ||
|
b_sig == QPU_SIG_SMALL_IMM ||
|
a_sig == QPU_SIG_BRANCH ||
|
b_sig == QPU_SIG_BRANCH) {
|
return 0;
|
}
|
|
ok = ok && merge_fields(&merge, a, b, QPU_SIG_MASK,
|
QPU_SET_FIELD(QPU_SIG_NONE, QPU_SIG));
|
|
/* Misc fields that have to match exactly. */
|
ok = ok && merge_fields(&merge, a, b, QPU_SF, ~0);
|
|
if (!merge_fields(&merge, a, b, QPU_RADDR_A_MASK,
|
QPU_SET_FIELD(QPU_R_NOP, QPU_RADDR_A))) {
|
/* Since we tend to use regfile A by default both for register
|
* allocation and for our special values (uniforms and
|
* varyings), try swapping uniforms and varyings to regfile B
|
* to resolve raddr A conflicts.
|
*/
|
if (!try_swap_ra_file(&merge, &a, &b) &&
|
!try_swap_ra_file(&merge, &b, &a)) {
|
return 0;
|
}
|
}
|
|
ok = ok && merge_fields(&merge, a, b, QPU_RADDR_B_MASK,
|
QPU_SET_FIELD(QPU_R_NOP, QPU_RADDR_B));
|
|
ok = ok && merge_fields(&merge, a, b, QPU_WADDR_ADD_MASK,
|
QPU_SET_FIELD(QPU_W_NOP, QPU_WADDR_ADD));
|
ok = ok && merge_fields(&merge, a, b, QPU_WADDR_MUL_MASK,
|
QPU_SET_FIELD(QPU_W_NOP, QPU_WADDR_MUL));
|
|
/* Allow disagreement on WS (swapping A vs B physical reg file as the
|
* destination for ADD/MUL) if one of the original instructions
|
* ignores it (probably because it's just writing to accumulators).
|
*/
|
if (qpu_waddr_ignores_ws(QPU_GET_FIELD(a, QPU_WADDR_ADD)) &&
|
qpu_waddr_ignores_ws(QPU_GET_FIELD(a, QPU_WADDR_MUL))) {
|
merge = (merge & ~QPU_WS) | (b & QPU_WS);
|
} else if (qpu_waddr_ignores_ws(QPU_GET_FIELD(b, QPU_WADDR_ADD)) &&
|
qpu_waddr_ignores_ws(QPU_GET_FIELD(b, QPU_WADDR_MUL))) {
|
merge = (merge & ~QPU_WS) | (a & QPU_WS);
|
} else {
|
if ((a & QPU_WS) != (b & QPU_WS))
|
return 0;
|
}
|
|
if (!merge_fields(&merge, a, b, QPU_PM, ~0)) {
|
/* If one instruction has PM bit set and the other not, the
|
* one without PM shouldn't do packing/unpacking, and we
|
* have to make sure non-NOP packing/unpacking from PM
|
* instruction aren't added to it.
|
*/
|
uint64_t temp;
|
|
/* Let a be the one with PM bit */
|
if (!(a & QPU_PM)) {
|
temp = a;
|
a = b;
|
b = temp;
|
}
|
|
if ((b & (QPU_PACK_MASK | QPU_UNPACK_MASK)) != 0)
|
return 0;
|
|
if ((a & QPU_PACK_MASK) != 0 &&
|
QPU_GET_FIELD(b, QPU_OP_MUL) != QPU_M_NOP)
|
return 0;
|
|
if ((a & QPU_UNPACK_MASK) != 0 && reads_r4(b))
|
return 0;
|
} else {
|
/* packing: Make sure that non-NOP packs agree, then deal with
|
* special-case failing of adding a non-NOP pack to something
|
* with a NOP pack.
|
*/
|
if (!merge_fields(&merge, a, b, QPU_PACK_MASK, 0))
|
return 0;
|
bool new_a_pack = (QPU_GET_FIELD(a, QPU_PACK) !=
|
QPU_GET_FIELD(merge, QPU_PACK));
|
bool new_b_pack = (QPU_GET_FIELD(b, QPU_PACK) !=
|
QPU_GET_FIELD(merge, QPU_PACK));
|
if (!(merge & QPU_PM)) {
|
/* Make sure we're not going to be putting a new
|
* a-file packing on either half.
|
*/
|
if (new_a_pack && writes_a_file(a))
|
return 0;
|
|
if (new_b_pack && writes_a_file(b))
|
return 0;
|
} else {
|
/* Make sure we're not going to be putting new MUL
|
* packing oneither half.
|
*/
|
if (new_a_pack &&
|
QPU_GET_FIELD(a, QPU_OP_MUL) != QPU_M_NOP)
|
return 0;
|
|
if (new_b_pack &&
|
QPU_GET_FIELD(b, QPU_OP_MUL) != QPU_M_NOP)
|
return 0;
|
}
|
|
/* unpacking: Make sure that non-NOP unpacks agree, then deal
|
* with special-case failing of adding a non-NOP unpack to
|
* something with a NOP unpack.
|
*/
|
if (!merge_fields(&merge, a, b, QPU_UNPACK_MASK, 0))
|
return 0;
|
bool new_a_unpack = (QPU_GET_FIELD(a, QPU_UNPACK) !=
|
QPU_GET_FIELD(merge, QPU_UNPACK));
|
bool new_b_unpack = (QPU_GET_FIELD(b, QPU_UNPACK) !=
|
QPU_GET_FIELD(merge, QPU_UNPACK));
|
if (!(merge & QPU_PM)) {
|
/* Make sure we're not going to be putting a new
|
* a-file packing on either half.
|
*/
|
if (new_a_unpack &&
|
QPU_GET_FIELD(a, QPU_RADDR_A) != QPU_R_NOP)
|
return 0;
|
|
if (new_b_unpack &&
|
QPU_GET_FIELD(b, QPU_RADDR_A) != QPU_R_NOP)
|
return 0;
|
} else {
|
/* Make sure we're not going to be putting new r4
|
* unpack on either half.
|
*/
|
if (new_a_unpack && reads_r4(a))
|
return 0;
|
|
if (new_b_unpack && reads_r4(b))
|
return 0;
|
}
|
}
|
|
if (ok)
|
return merge;
|
else
|
return 0;
|
}
|
|
uint64_t
|
qpu_set_sig(uint64_t inst, uint32_t sig)
|
{
|
assert(QPU_GET_FIELD(inst, QPU_SIG) == QPU_SIG_NONE);
|
return QPU_UPDATE_FIELD(inst, sig, QPU_SIG);
|
}
|
|
uint64_t
|
qpu_set_cond_add(uint64_t inst, uint32_t cond)
|
{
|
assert(QPU_GET_FIELD(inst, QPU_COND_ADD) == QPU_COND_ALWAYS);
|
return QPU_UPDATE_FIELD(inst, cond, QPU_COND_ADD);
|
}
|
|
uint64_t
|
qpu_set_cond_mul(uint64_t inst, uint32_t cond)
|
{
|
assert(QPU_GET_FIELD(inst, QPU_COND_MUL) == QPU_COND_ALWAYS);
|
return QPU_UPDATE_FIELD(inst, cond, QPU_COND_MUL);
|
}
|
|
bool
|
qpu_waddr_is_tlb(uint32_t waddr)
|
{
|
switch (waddr) {
|
case QPU_W_TLB_COLOR_ALL:
|
case QPU_W_TLB_COLOR_MS:
|
case QPU_W_TLB_Z:
|
return true;
|
default:
|
return false;
|
}
|
}
|
|
bool
|
qpu_inst_is_tlb(uint64_t inst)
|
{
|
uint32_t sig = QPU_GET_FIELD(inst, QPU_SIG);
|
|
return (qpu_waddr_is_tlb(QPU_GET_FIELD(inst, QPU_WADDR_ADD)) ||
|
qpu_waddr_is_tlb(QPU_GET_FIELD(inst, QPU_WADDR_MUL)) ||
|
sig == QPU_SIG_COLOR_LOAD ||
|
sig == QPU_SIG_WAIT_FOR_SCOREBOARD);
|
}
|
|
/**
|
* Returns the small immediate value to be encoded in to the raddr b field if
|
* the argument can be represented as one, or ~0 otherwise.
|
*/
|
uint32_t
|
qpu_encode_small_immediate(uint32_t i)
|
{
|
if (i <= 15)
|
return i;
|
if ((int)i < 0 && (int)i >= -16)
|
return i + 32;
|
|
switch (i) {
|
case 0x3f800000:
|
return 32;
|
case 0x40000000:
|
return 33;
|
case 0x40800000:
|
return 34;
|
case 0x41000000:
|
return 35;
|
case 0x41800000:
|
return 36;
|
case 0x42000000:
|
return 37;
|
case 0x42800000:
|
return 38;
|
case 0x43000000:
|
return 39;
|
case 0x3b800000:
|
return 40;
|
case 0x3c000000:
|
return 41;
|
case 0x3c800000:
|
return 42;
|
case 0x3d000000:
|
return 43;
|
case 0x3d800000:
|
return 44;
|
case 0x3e000000:
|
return 45;
|
case 0x3e800000:
|
return 46;
|
case 0x3f000000:
|
return 47;
|
}
|
|
return ~0;
|
}
|
|
void
|
qpu_serialize_one_inst(struct vc4_compile *c, uint64_t inst)
|
{
|
if (c->qpu_inst_count >= c->qpu_inst_size) {
|
c->qpu_inst_size = MAX2(16, c->qpu_inst_size * 2);
|
c->qpu_insts = reralloc(c, c->qpu_insts,
|
uint64_t, c->qpu_inst_size);
|
}
|
c->qpu_insts[c->qpu_inst_count++] = inst;
|
}
|
