/*
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* Copyright © 2014 Broadcom
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#ifndef VC4_QIR_H
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#define VC4_QIR_H
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#include <assert.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <stdbool.h>
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#include <stdint.h>
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#include <string.h>
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#include "util/macros.h"
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#include "compiler/nir/nir.h"
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#include "util/list.h"
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#include "util/u_math.h"
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#include "vc4_screen.h"
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#include "vc4_qpu_defines.h"
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#include "vc4_qpu.h"
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#include "kernel/vc4_packet.h"
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#include "pipe/p_state.h"
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struct nir_builder;
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enum qfile {
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QFILE_NULL,
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QFILE_TEMP,
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QFILE_VARY,
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QFILE_UNIF,
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QFILE_VPM,
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QFILE_TLB_COLOR_WRITE,
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QFILE_TLB_COLOR_WRITE_MS,
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QFILE_TLB_Z_WRITE,
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QFILE_TLB_STENCIL_SETUP,
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/* If tex_s is written on its own without preceding t/r/b setup, it's
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* a direct memory access using the input value, without the sideband
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* uniform load. We represent these in QIR as a separate write
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* destination so we can tell if the sideband uniform is present.
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*/
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QFILE_TEX_S_DIRECT,
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QFILE_TEX_S,
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QFILE_TEX_T,
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QFILE_TEX_R,
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QFILE_TEX_B,
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/* Payload registers that aren't in the physical register file, so we
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* can just use the corresponding qpu_reg at qpu_emit time.
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*/
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QFILE_FRAG_X,
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QFILE_FRAG_Y,
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QFILE_FRAG_REV_FLAG,
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QFILE_QPU_ELEMENT,
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/**
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* Stores an immediate value in the index field that will be used
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* directly by qpu_load_imm().
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*/
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QFILE_LOAD_IMM,
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/**
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* Stores an immediate value in the index field that can be turned
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* into a small immediate field by qpu_encode_small_immediate().
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*/
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QFILE_SMALL_IMM,
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};
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struct qreg {
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enum qfile file;
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uint32_t index;
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int pack;
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};
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static inline struct qreg qir_reg(enum qfile file, uint32_t index)
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{
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return (struct qreg){file, index};
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}
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enum qop {
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QOP_UNDEF,
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QOP_MOV,
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QOP_FMOV,
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QOP_MMOV,
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QOP_FADD,
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QOP_FSUB,
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QOP_FMUL,
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QOP_V8MULD,
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QOP_V8MIN,
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QOP_V8MAX,
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QOP_V8ADDS,
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QOP_V8SUBS,
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QOP_MUL24,
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QOP_FMIN,
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QOP_FMAX,
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QOP_FMINABS,
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QOP_FMAXABS,
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QOP_ADD,
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QOP_SUB,
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QOP_SHL,
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QOP_SHR,
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QOP_ASR,
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QOP_MIN,
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QOP_MIN_NOIMM,
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QOP_MAX,
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QOP_AND,
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QOP_OR,
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QOP_XOR,
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QOP_NOT,
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QOP_FTOI,
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QOP_ITOF,
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QOP_RCP,
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QOP_RSQ,
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QOP_EXP2,
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QOP_LOG2,
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QOP_VW_SETUP,
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QOP_VR_SETUP,
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QOP_TLB_COLOR_READ,
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QOP_MS_MASK,
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QOP_VARY_ADD_C,
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QOP_FRAG_Z,
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QOP_FRAG_W,
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/**
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* Signal of texture read being necessary and then reading r4 into
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* the destination
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*/
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QOP_TEX_RESULT,
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/**
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* Insert the signal for switching threads in a threaded fragment
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* shader. No value can be live in an accumulator across a thrsw.
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*
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* At the QPU level, this will have several delay slots before the
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* switch happens. Those slots are the responsibility of the
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* scheduler.
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*/
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QOP_THRSW,
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/* 32-bit immediate loaded to each SIMD channel */
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QOP_LOAD_IMM,
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/* 32-bit immediate divided into 16 2-bit unsigned int values and
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* loaded to each corresponding SIMD channel.
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*/
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QOP_LOAD_IMM_U2,
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/* 32-bit immediate divided into 16 2-bit signed int values and
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* loaded to each corresponding SIMD channel.
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*/
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QOP_LOAD_IMM_I2,
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QOP_ROT_MUL,
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/* Jumps to block->successor[0] if the qinst->cond (as a
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* QPU_COND_BRANCH_*) passes, or block->successor[1] if not. Note
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* that block->successor[1] may be unset if the condition is ALWAYS.
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*/
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QOP_BRANCH,
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/* Emits an ADD from src[0] to src[1], where src[0] must be a
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* QOP_LOAD_IMM result and src[1] is a QUNIFORM_UNIFORMS_ADDRESS,
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* required by the kernel as part of its branch validation.
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*/
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QOP_UNIFORMS_RESET,
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};
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struct queued_qpu_inst {
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struct list_head link;
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uint64_t inst;
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};
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struct qinst {
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struct list_head link;
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enum qop op;
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struct qreg dst;
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struct qreg src[3];
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bool sf;
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bool cond_is_exec_mask;
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uint8_t cond;
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};
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enum qstage {
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/**
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* Coordinate shader, runs during binning, before the VS, and just
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* outputs position.
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*/
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QSTAGE_COORD,
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QSTAGE_VERT,
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QSTAGE_FRAG,
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};
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enum quniform_contents {
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/**
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* Indicates that a constant 32-bit value is copied from the program's
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* uniform contents.
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*/
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QUNIFORM_CONSTANT,
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/**
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* Indicates that the program's uniform contents are used as an index
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* into the GL uniform storage.
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*/
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QUNIFORM_UNIFORM,
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/** @{
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* Scaling factors from clip coordinates to relative to the viewport
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* center.
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*
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* This is used by the coordinate and vertex shaders to produce the
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* 32-bit entry consisting of 2 16-bit fields with 12.4 signed fixed
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* point offsets from the viewport ccenter.
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*/
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QUNIFORM_VIEWPORT_X_SCALE,
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QUNIFORM_VIEWPORT_Y_SCALE,
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/** @} */
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QUNIFORM_VIEWPORT_Z_OFFSET,
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QUNIFORM_VIEWPORT_Z_SCALE,
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QUNIFORM_USER_CLIP_PLANE,
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/**
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* A reference to a texture config parameter 0 uniform.
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*
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* This is a uniform implicitly loaded with a QPU_W_TMU* write, which
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* defines texture type, miplevels, and such. It will be found as a
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* parameter to the first QOP_TEX_[STRB] instruction in a sequence.
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*/
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QUNIFORM_TEXTURE_CONFIG_P0,
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/**
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* A reference to a texture config parameter 1 uniform.
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*
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* This is a uniform implicitly loaded with a QPU_W_TMU* write, which
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* defines texture width, height, filters, and wrap modes. It will be
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* found as a parameter to the second QOP_TEX_[STRB] instruction in a
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* sequence.
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*/
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QUNIFORM_TEXTURE_CONFIG_P1,
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/** A reference to a texture config parameter 2 cubemap stride uniform */
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QUNIFORM_TEXTURE_CONFIG_P2,
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QUNIFORM_TEXTURE_FIRST_LEVEL,
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QUNIFORM_TEXTURE_MSAA_ADDR,
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QUNIFORM_UBO_ADDR,
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QUNIFORM_TEXRECT_SCALE_X,
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QUNIFORM_TEXRECT_SCALE_Y,
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QUNIFORM_TEXTURE_BORDER_COLOR,
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QUNIFORM_BLEND_CONST_COLOR_X,
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QUNIFORM_BLEND_CONST_COLOR_Y,
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QUNIFORM_BLEND_CONST_COLOR_Z,
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QUNIFORM_BLEND_CONST_COLOR_W,
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QUNIFORM_BLEND_CONST_COLOR_RGBA,
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QUNIFORM_BLEND_CONST_COLOR_AAAA,
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QUNIFORM_STENCIL,
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QUNIFORM_ALPHA_REF,
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QUNIFORM_SAMPLE_MASK,
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/* Placeholder uniform that will be updated by the kernel when used by
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* an instruction writing to QPU_W_UNIFORMS_ADDRESS.
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*/
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QUNIFORM_UNIFORMS_ADDRESS,
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};
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struct vc4_varying_slot {
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uint8_t slot;
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uint8_t swizzle;
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};
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struct vc4_compiler_ubo_range {
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/**
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* offset in bytes from the start of the ubo where this range is
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* uploaded.
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*
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* Only set once used is set.
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*/
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uint32_t dst_offset;
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/**
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* offset in bytes from the start of the gallium uniforms where the
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* data comes from.
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*/
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uint32_t src_offset;
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/** size in bytes of this ubo range */
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uint32_t size;
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/**
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* Set if this range is used by the shader for indirect uniforms
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* access.
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*/
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bool used;
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};
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struct vc4_key {
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struct vc4_uncompiled_shader *shader_state;
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struct {
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enum pipe_format format;
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uint8_t swizzle[4];
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union {
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struct {
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unsigned compare_mode:1;
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unsigned compare_func:3;
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unsigned wrap_s:3;
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unsigned wrap_t:3;
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bool force_first_level:1;
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};
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struct {
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uint16_t msaa_width, msaa_height;
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};
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};
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} tex[VC4_MAX_TEXTURE_SAMPLERS];
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uint8_t ucp_enables;
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};
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struct vc4_fs_key {
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struct vc4_key base;
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enum pipe_format color_format;
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bool depth_enabled;
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bool stencil_enabled;
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bool stencil_twoside;
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bool stencil_full_writemasks;
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bool is_points;
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bool is_lines;
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bool point_coord_upper_left;
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bool light_twoside;
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bool msaa;
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bool sample_coverage;
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bool sample_alpha_to_coverage;
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bool sample_alpha_to_one;
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uint8_t alpha_test_func;
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uint8_t logicop_func;
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uint32_t point_sprite_mask;
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struct pipe_rt_blend_state blend;
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};
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struct vc4_vs_key {
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struct vc4_key base;
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const struct vc4_fs_inputs *fs_inputs;
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enum pipe_format attr_formats[8];
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bool is_coord;
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bool per_vertex_point_size;
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bool clamp_color;
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};
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/** A basic block of QIR intructions. */
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struct qblock {
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struct list_head link;
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struct list_head instructions;
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struct list_head qpu_inst_list;
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struct set *predecessors;
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struct qblock *successors[2];
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int index;
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/* Instruction IPs for the first and last instruction of the block.
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* Set by vc4_qpu_schedule.c.
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*/
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uint32_t start_qpu_ip;
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uint32_t end_qpu_ip;
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/* Instruction IP for the branch instruction of the block. Set by
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* vc4_qpu_schedule.c.
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*/
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uint32_t branch_qpu_ip;
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/** @{ used by vc4_qir_live_variables.c */
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BITSET_WORD *def;
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BITSET_WORD *use;
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BITSET_WORD *live_in;
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BITSET_WORD *live_out;
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int start_ip, end_ip;
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/** @} */
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};
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struct vc4_compile {
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struct vc4_context *vc4;
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nir_shader *s;
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nir_function_impl *impl;
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struct exec_list *cf_node_list;
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/**
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* Mapping from nir_register * or nir_ssa_def * to array of struct
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* qreg for the values.
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*/
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struct hash_table *def_ht;
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/* For each temp, the instruction generating its value. */
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struct qinst **defs;
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uint32_t defs_array_size;
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/**
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* Inputs to the shader, arranged by TGSI declaration order.
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*
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* Not all fragment shader QFILE_VARY reads are present in this array.
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*/
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struct qreg *inputs;
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struct qreg *outputs;
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bool msaa_per_sample_output;
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struct qreg color_reads[VC4_MAX_SAMPLES];
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struct qreg sample_colors[VC4_MAX_SAMPLES];
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uint32_t inputs_array_size;
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uint32_t outputs_array_size;
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uint32_t uniforms_array_size;
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struct vc4_compiler_ubo_range *ubo_ranges;
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uint32_t ubo_ranges_array_size;
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/** Number of uniform areas declared in ubo_ranges. */
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uint32_t num_uniform_ranges;
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/** Number of uniform areas used for indirect addressed loads. */
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uint32_t num_ubo_ranges;
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uint32_t next_ubo_dst_offset;
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/* State for whether we're executing on each channel currently. 0 if
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* yes, otherwise a block number + 1 that the channel jumped to.
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*/
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struct qreg execute;
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struct qreg line_x, point_x, point_y;
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/** boolean (~0 -> true) if the fragment has been discarded. */
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struct qreg discard;
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struct qreg payload_FRAG_Z;
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struct qreg payload_FRAG_W;
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uint8_t vattr_sizes[8];
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/**
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* Array of the VARYING_SLOT_* of all FS QFILE_VARY reads.
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*
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* This includes those that aren't part of the VPM varyings, like
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* point/line coordinates.
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*/
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struct vc4_varying_slot *input_slots;
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uint32_t num_input_slots;
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uint32_t input_slots_array_size;
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/**
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* An entry per outputs[] in the VS indicating what the VARYING_SLOT_*
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* of the output is. Used to emit from the VS in the order that the
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* FS needs.
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*/
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struct vc4_varying_slot *output_slots;
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struct pipe_shader_state *shader_state;
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struct vc4_key *key;
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struct vc4_fs_key *fs_key;
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struct vc4_vs_key *vs_key;
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/* Live ranges of temps. */
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int *temp_start, *temp_end;
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uint32_t *uniform_data;
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enum quniform_contents *uniform_contents;
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uint32_t uniform_array_size;
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uint32_t num_uniforms;
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uint32_t num_outputs;
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uint32_t num_texture_samples;
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uint32_t output_position_index;
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uint32_t output_color_index;
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uint32_t output_point_size_index;
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uint32_t output_sample_mask_index;
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struct qreg undef;
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enum qstage stage;
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uint32_t num_temps;
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struct list_head blocks;
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int next_block_index;
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struct qblock *cur_block;
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struct qblock *loop_cont_block;
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struct qblock *loop_break_block;
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struct qblock *last_top_block;
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struct list_head qpu_inst_list;
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/* Pre-QPU-scheduled instruction containing the last THRSW */
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uint64_t *last_thrsw;
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uint64_t *qpu_insts;
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uint32_t qpu_inst_count;
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uint32_t qpu_inst_size;
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uint32_t num_inputs;
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/**
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* Number of inputs from num_inputs remaining to be queued to the read
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* FIFO in the VS/CS.
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*/
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uint32_t num_inputs_remaining;
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/* Number of inputs currently in the read FIFO for the VS/CS */
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uint32_t num_inputs_in_fifo;
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/** Next offset in the VPM to read from in the VS/CS */
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uint32_t vpm_read_offset;
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uint32_t program_id;
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uint32_t variant_id;
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/* Set to compile program in threaded FS mode, where SIG_THREAD_SWITCH
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* is used to hide texturing latency at the cost of limiting ourselves
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* to the bottom half of physical reg space.
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*/
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bool fs_threaded;
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bool last_thrsw_at_top_level;
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bool failed;
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};
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/* Special nir_load_input intrinsic index for loading the current TLB
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* destination color.
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*/
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#define VC4_NIR_TLB_COLOR_READ_INPUT 2000000000
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#define VC4_NIR_MS_MASK_OUTPUT 2000000000
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struct vc4_compile *qir_compile_init(void);
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void qir_compile_destroy(struct vc4_compile *c);
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struct qblock *qir_new_block(struct vc4_compile *c);
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void qir_set_emit_block(struct vc4_compile *c, struct qblock *block);
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void qir_link_blocks(struct qblock *predecessor, struct qblock *successor);
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struct qblock *qir_entry_block(struct vc4_compile *c);
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struct qblock *qir_exit_block(struct vc4_compile *c);
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struct qinst *qir_inst(enum qop op, struct qreg dst,
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struct qreg src0, struct qreg src1);
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void qir_remove_instruction(struct vc4_compile *c, struct qinst *qinst);
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struct qreg qir_uniform(struct vc4_compile *c,
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enum quniform_contents contents,
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uint32_t data);
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void qir_schedule_instructions(struct vc4_compile *c);
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void qir_reorder_uniforms(struct vc4_compile *c);
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void qir_emit_uniform_stream_resets(struct vc4_compile *c);
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struct qreg qir_emit_def(struct vc4_compile *c, struct qinst *inst);
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struct qinst *qir_emit_nondef(struct vc4_compile *c, struct qinst *inst);
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struct qreg qir_get_temp(struct vc4_compile *c);
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void qir_calculate_live_intervals(struct vc4_compile *c);
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int qir_get_nsrc(struct qinst *inst);
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int qir_get_non_sideband_nsrc(struct qinst *inst);
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int qir_get_tex_uniform_src(struct qinst *inst);
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bool qir_reg_equals(struct qreg a, struct qreg b);
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bool qir_has_side_effects(struct vc4_compile *c, struct qinst *inst);
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bool qir_has_side_effect_reads(struct vc4_compile *c, struct qinst *inst);
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bool qir_has_uniform_read(struct qinst *inst);
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bool qir_is_mul(struct qinst *inst);
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bool qir_is_raw_mov(struct qinst *inst);
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bool qir_is_tex(struct qinst *inst);
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bool qir_has_implicit_tex_uniform(struct qinst *inst);
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bool qir_is_float_input(struct qinst *inst);
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bool qir_depends_on_flags(struct qinst *inst);
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bool qir_writes_r4(struct qinst *inst);
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struct qreg qir_follow_movs(struct vc4_compile *c, struct qreg reg);
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uint8_t qir_channels_written(struct qinst *inst);
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void qir_dump(struct vc4_compile *c);
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void qir_dump_inst(struct vc4_compile *c, struct qinst *inst);
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const char *qir_get_stage_name(enum qstage stage);
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void qir_validate(struct vc4_compile *c);
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void qir_optimize(struct vc4_compile *c);
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bool qir_opt_algebraic(struct vc4_compile *c);
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bool qir_opt_coalesce_ff_writes(struct vc4_compile *c);
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bool qir_opt_constant_folding(struct vc4_compile *c);
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bool qir_opt_copy_propagation(struct vc4_compile *c);
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bool qir_opt_dead_code(struct vc4_compile *c);
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bool qir_opt_peephole_sf(struct vc4_compile *c);
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bool qir_opt_small_immediates(struct vc4_compile *c);
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bool qir_opt_vpm(struct vc4_compile *c);
|
void vc4_nir_lower_blend(nir_shader *s, struct vc4_compile *c);
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void vc4_nir_lower_io(nir_shader *s, struct vc4_compile *c);
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nir_ssa_def *vc4_nir_get_swizzled_channel(struct nir_builder *b,
|
nir_ssa_def **srcs, int swiz);
|
void vc4_nir_lower_txf_ms(nir_shader *s, struct vc4_compile *c);
|
void qir_lower_uniforms(struct vc4_compile *c);
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uint32_t qpu_schedule_instructions(struct vc4_compile *c);
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void qir_SF(struct vc4_compile *c, struct qreg src);
|
|
static inline struct qreg
|
qir_uniform_ui(struct vc4_compile *c, uint32_t ui)
|
{
|
return qir_uniform(c, QUNIFORM_CONSTANT, ui);
|
}
|
|
static inline struct qreg
|
qir_uniform_f(struct vc4_compile *c, float f)
|
{
|
return qir_uniform(c, QUNIFORM_CONSTANT, fui(f));
|
}
|
|
#define QIR_ALU0(name) \
|
static inline struct qreg \
|
qir_##name(struct vc4_compile *c) \
|
{ \
|
return qir_emit_def(c, qir_inst(QOP_##name, c->undef, \
|
c->undef, c->undef)); \
|
} \
|
static inline struct qinst * \
|
qir_##name##_dest(struct vc4_compile *c, struct qreg dest) \
|
{ \
|
return qir_emit_nondef(c, qir_inst(QOP_##name, dest, \
|
c->undef, c->undef)); \
|
}
|
|
#define QIR_ALU1(name) \
|
static inline struct qreg \
|
qir_##name(struct vc4_compile *c, struct qreg a) \
|
{ \
|
return qir_emit_def(c, qir_inst(QOP_##name, c->undef, \
|
a, c->undef)); \
|
} \
|
static inline struct qinst * \
|
qir_##name##_dest(struct vc4_compile *c, struct qreg dest, \
|
struct qreg a) \
|
{ \
|
return qir_emit_nondef(c, qir_inst(QOP_##name, dest, a, \
|
c->undef)); \
|
}
|
|
#define QIR_ALU2(name) \
|
static inline struct qreg \
|
qir_##name(struct vc4_compile *c, struct qreg a, struct qreg b) \
|
{ \
|
return qir_emit_def(c, qir_inst(QOP_##name, c->undef, a, b)); \
|
} \
|
static inline struct qinst * \
|
qir_##name##_dest(struct vc4_compile *c, struct qreg dest, \
|
struct qreg a, struct qreg b) \
|
{ \
|
return qir_emit_nondef(c, qir_inst(QOP_##name, dest, a, b)); \
|
}
|
|
#define QIR_NODST_1(name) \
|
static inline struct qinst * \
|
qir_##name(struct vc4_compile *c, struct qreg a) \
|
{ \
|
return qir_emit_nondef(c, qir_inst(QOP_##name, c->undef, \
|
a, c->undef)); \
|
}
|
|
#define QIR_NODST_2(name) \
|
static inline struct qinst * \
|
qir_##name(struct vc4_compile *c, struct qreg a, struct qreg b) \
|
{ \
|
return qir_emit_nondef(c, qir_inst(QOP_##name, c->undef, \
|
a, b)); \
|
}
|
|
#define QIR_PAYLOAD(name) \
|
static inline struct qreg \
|
qir_##name(struct vc4_compile *c) \
|
{ \
|
struct qreg *payload = &c->payload_##name; \
|
if (payload->file != QFILE_NULL) \
|
return *payload; \
|
*payload = qir_get_temp(c); \
|
struct qinst *inst = qir_inst(QOP_##name, *payload, \
|
c->undef, c->undef); \
|
struct qblock *entry = qir_entry_block(c); \
|
list_add(&inst->link, &entry->instructions); \
|
c->defs[payload->index] = inst; \
|
return *payload; \
|
}
|
|
QIR_ALU1(MOV)
|
QIR_ALU1(FMOV)
|
QIR_ALU1(MMOV)
|
QIR_ALU2(FADD)
|
QIR_ALU2(FSUB)
|
QIR_ALU2(FMUL)
|
QIR_ALU2(V8MULD)
|
QIR_ALU2(V8MIN)
|
QIR_ALU2(V8MAX)
|
QIR_ALU2(V8ADDS)
|
QIR_ALU2(V8SUBS)
|
QIR_ALU2(MUL24)
|
QIR_ALU2(FMIN)
|
QIR_ALU2(FMAX)
|
QIR_ALU2(FMINABS)
|
QIR_ALU2(FMAXABS)
|
QIR_ALU1(FTOI)
|
QIR_ALU1(ITOF)
|
|
QIR_ALU2(ADD)
|
QIR_ALU2(SUB)
|
QIR_ALU2(SHL)
|
QIR_ALU2(SHR)
|
QIR_ALU2(ASR)
|
QIR_ALU2(MIN)
|
QIR_ALU2(MIN_NOIMM)
|
QIR_ALU2(MAX)
|
QIR_ALU2(AND)
|
QIR_ALU2(OR)
|
QIR_ALU2(XOR)
|
QIR_ALU1(NOT)
|
|
QIR_ALU1(RCP)
|
QIR_ALU1(RSQ)
|
QIR_ALU1(EXP2)
|
QIR_ALU1(LOG2)
|
QIR_ALU1(VARY_ADD_C)
|
QIR_PAYLOAD(FRAG_Z)
|
QIR_PAYLOAD(FRAG_W)
|
QIR_ALU0(TEX_RESULT)
|
QIR_ALU0(TLB_COLOR_READ)
|
QIR_NODST_1(MS_MASK)
|
|
static inline struct qreg
|
qir_SEL(struct vc4_compile *c, uint8_t cond, struct qreg src0, struct qreg src1)
|
{
|
struct qreg t = qir_get_temp(c);
|
qir_MOV_dest(c, t, src1);
|
qir_MOV_dest(c, t, src0)->cond = cond;
|
return t;
|
}
|
|
static inline struct qreg
|
qir_UNPACK_8_F(struct vc4_compile *c, struct qreg src, int i)
|
{
|
struct qreg t = qir_FMOV(c, src);
|
c->defs[t.index]->src[0].pack = QPU_UNPACK_8A + i;
|
return t;
|
}
|
|
static inline struct qreg
|
qir_UNPACK_8_I(struct vc4_compile *c, struct qreg src, int i)
|
{
|
struct qreg t = qir_MOV(c, src);
|
c->defs[t.index]->src[0].pack = QPU_UNPACK_8A + i;
|
return t;
|
}
|
|
static inline struct qreg
|
qir_UNPACK_16_F(struct vc4_compile *c, struct qreg src, int i)
|
{
|
struct qreg t = qir_FMOV(c, src);
|
c->defs[t.index]->src[0].pack = QPU_UNPACK_16A + i;
|
return t;
|
}
|
|
static inline struct qreg
|
qir_UNPACK_16_I(struct vc4_compile *c, struct qreg src, int i)
|
{
|
struct qreg t = qir_MOV(c, src);
|
c->defs[t.index]->src[0].pack = QPU_UNPACK_16A + i;
|
return t;
|
}
|
|
static inline void
|
qir_PACK_8_F(struct vc4_compile *c, struct qreg dest, struct qreg val, int chan)
|
{
|
assert(!dest.pack);
|
dest.pack = QPU_PACK_MUL_8A + chan;
|
qir_emit_nondef(c, qir_inst(QOP_MMOV, dest, val, c->undef));
|
}
|
|
static inline struct qreg
|
qir_PACK_8888_F(struct vc4_compile *c, struct qreg val)
|
{
|
struct qreg dest = qir_MMOV(c, val);
|
c->defs[dest.index]->dst.pack = QPU_PACK_MUL_8888;
|
return dest;
|
}
|
|
static inline struct qreg
|
qir_POW(struct vc4_compile *c, struct qreg x, struct qreg y)
|
{
|
return qir_EXP2(c, qir_FMUL(c,
|
y,
|
qir_LOG2(c, x)));
|
}
|
|
static inline void
|
qir_VPM_WRITE(struct vc4_compile *c, struct qreg val)
|
{
|
qir_MOV_dest(c, qir_reg(QFILE_VPM, 0), val);
|
}
|
|
static inline struct qreg
|
qir_LOAD_IMM(struct vc4_compile *c, uint32_t val)
|
{
|
return qir_emit_def(c, qir_inst(QOP_LOAD_IMM, c->undef,
|
qir_reg(QFILE_LOAD_IMM, val), c->undef));
|
}
|
|
static inline struct qreg
|
qir_LOAD_IMM_U2(struct vc4_compile *c, uint32_t val)
|
{
|
return qir_emit_def(c, qir_inst(QOP_LOAD_IMM_U2, c->undef,
|
qir_reg(QFILE_LOAD_IMM, val),
|
c->undef));
|
}
|
|
static inline struct qreg
|
qir_LOAD_IMM_I2(struct vc4_compile *c, uint32_t val)
|
{
|
return qir_emit_def(c, qir_inst(QOP_LOAD_IMM_I2, c->undef,
|
qir_reg(QFILE_LOAD_IMM, val),
|
c->undef));
|
}
|
|
/** Shifts the multiply output to the right by rot channels */
|
static inline struct qreg
|
qir_ROT_MUL(struct vc4_compile *c, struct qreg val, uint32_t rot)
|
{
|
return qir_emit_def(c, qir_inst(QOP_ROT_MUL, c->undef,
|
val,
|
qir_reg(QFILE_LOAD_IMM,
|
QPU_SMALL_IMM_MUL_ROT + rot)));
|
}
|
|
static inline struct qinst *
|
qir_MOV_cond(struct vc4_compile *c, uint8_t cond,
|
struct qreg dest, struct qreg src)
|
{
|
struct qinst *mov = qir_MOV_dest(c, dest, src);
|
mov->cond = cond;
|
return mov;
|
}
|
|
static inline struct qinst *
|
qir_BRANCH(struct vc4_compile *c, uint8_t cond)
|
{
|
struct qinst *inst = qir_inst(QOP_BRANCH, c->undef, c->undef, c->undef);
|
inst->cond = cond;
|
qir_emit_nondef(c, inst);
|
return inst;
|
}
|
|
#define qir_for_each_block(block, c) \
|
list_for_each_entry(struct qblock, block, &c->blocks, link)
|
|
#define qir_for_each_block_rev(block, c) \
|
list_for_each_entry_rev(struct qblock, block, &c->blocks, link)
|
|
/* Loop over the non-NULL members of the successors array. */
|
#define qir_for_each_successor(succ, block) \
|
for (struct qblock *succ = block->successors[0]; \
|
succ != NULL; \
|
succ = (succ == block->successors[1] ? NULL : \
|
block->successors[1]))
|
|
#define qir_for_each_inst(inst, block) \
|
list_for_each_entry(struct qinst, inst, &block->instructions, link)
|
|
#define qir_for_each_inst_rev(inst, block) \
|
list_for_each_entry_rev(struct qinst, inst, &block->instructions, link)
|
|
#define qir_for_each_inst_safe(inst, block) \
|
list_for_each_entry_safe(struct qinst, inst, &block->instructions, link)
|
|
#define qir_for_each_inst_inorder(inst, c) \
|
qir_for_each_block(_block, c) \
|
qir_for_each_inst_safe(inst, _block)
|
|
#endif /* VC4_QIR_H */
|
