/*
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* Copyright (c) 2014 Scott Mansell
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* Copyright © 2014 Broadcom
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include "util/u_blitter.h"
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#include "util/u_prim.h"
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#include "util/u_format.h"
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#include "util/u_pack_color.h"
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#include "util/u_upload_mgr.h"
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#include "indices/u_primconvert.h"
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#include "vc4_context.h"
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#include "vc4_resource.h"
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#define VC4_HW_2116_COUNT 0x1ef0
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static void
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vc4_get_draw_cl_space(struct vc4_job *job, int vert_count)
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{
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/* The SW-5891 workaround may cause us to emit multiple shader recs
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* and draw packets.
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*/
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int num_draws = DIV_ROUND_UP(vert_count, 65535 - 2) + 1;
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/* Binner gets our packet state -- vc4_emit.c contents,
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* and the primitive itself.
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*/
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cl_ensure_space(&job->bcl,
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256 + (VC4_PACKET_GL_ARRAY_PRIMITIVE_SIZE +
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VC4_PACKET_GL_SHADER_STATE_SIZE) * num_draws);
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/* Nothing for rcl -- that's covered by vc4_context.c */
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/* shader_rec gets up to 12 dwords of reloc handles plus a maximally
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* sized shader_rec (104 bytes base for 8 vattrs plus 32 bytes of
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* vattr stride).
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*/
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cl_ensure_space(&job->shader_rec,
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(12 * sizeof(uint32_t) + 104 + 8 * 32) * num_draws);
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/* Uniforms are covered by vc4_write_uniforms(). */
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/* There could be up to 16 textures per stage, plus misc other
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* pointers.
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*/
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cl_ensure_space(&job->bo_handles, (2 * 16 + 20) * sizeof(uint32_t));
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cl_ensure_space(&job->bo_pointers,
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(2 * 16 + 20) * sizeof(struct vc4_bo *));
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}
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/**
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* Does the initial bining command list setup for drawing to a given FBO.
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*/
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static void
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vc4_start_draw(struct vc4_context *vc4)
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{
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struct vc4_job *job = vc4->job;
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if (job->needs_flush)
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return;
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vc4_get_draw_cl_space(job, 0);
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cl_emit(&job->bcl, TILE_BINNING_MODE_CONFIGURATION, bin) {
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bin.width_in_tiles = job->draw_tiles_x;
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bin.height_in_tiles = job->draw_tiles_y;
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bin.multisample_mode_4x = job->msaa;
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}
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/* START_TILE_BINNING resets the statechange counters in the hardware,
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* which are what is used when a primitive is binned to a tile to
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* figure out what new state packets need to be written to that tile's
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* command list.
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*/
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cl_emit(&job->bcl, START_TILE_BINNING, start);
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/* Reset the current compressed primitives format. This gets modified
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* by VC4_PACKET_GL_INDEXED_PRIMITIVE and
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* VC4_PACKET_GL_ARRAY_PRIMITIVE, so it needs to be reset at the start
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* of every tile.
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*/
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cl_emit(&job->bcl, PRIMITIVE_LIST_FORMAT, list) {
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list.data_type = _16_BIT_INDEX;
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list.primitive_type = TRIANGLES_LIST;
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}
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job->needs_flush = true;
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job->draw_width = vc4->framebuffer.width;
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job->draw_height = vc4->framebuffer.height;
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}
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static void
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vc4_predraw_check_textures(struct pipe_context *pctx,
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struct vc4_texture_stateobj *stage_tex)
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{
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struct vc4_context *vc4 = vc4_context(pctx);
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for (int i = 0; i < stage_tex->num_textures; i++) {
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struct vc4_sampler_view *view =
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vc4_sampler_view(stage_tex->textures[i]);
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if (!view)
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continue;
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if (view->texture != view->base.texture)
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vc4_update_shadow_baselevel_texture(pctx, &view->base);
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vc4_flush_jobs_writing_resource(vc4, view->texture);
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}
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}
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static void
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vc4_emit_gl_shader_state(struct vc4_context *vc4,
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const struct pipe_draw_info *info,
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uint32_t extra_index_bias)
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{
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struct vc4_job *job = vc4->job;
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/* VC4_DIRTY_VTXSTATE */
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struct vc4_vertex_stateobj *vtx = vc4->vtx;
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/* VC4_DIRTY_VTXBUF */
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struct vc4_vertexbuf_stateobj *vertexbuf = &vc4->vertexbuf;
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/* The simulator throws a fit if VS or CS don't read an attribute, so
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* we emit a dummy read.
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*/
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uint32_t num_elements_emit = MAX2(vtx->num_elements, 1);
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/* Emit the shader record. */
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cl_start_shader_reloc(&job->shader_rec, 3 + num_elements_emit);
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cl_emit(&job->shader_rec, SHADER_RECORD, rec) {
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rec.enable_clipping = true;
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/* VC4_DIRTY_COMPILED_FS */
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rec.fragment_shader_is_single_threaded =
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!vc4->prog.fs->fs_threaded;
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/* VC4_DIRTY_PRIM_MODE | VC4_DIRTY_RASTERIZER */
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rec.point_size_included_in_shaded_vertex_data =
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(info->mode == PIPE_PRIM_POINTS &&
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vc4->rasterizer->base.point_size_per_vertex);
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/* VC4_DIRTY_COMPILED_FS */
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rec.fragment_shader_number_of_varyings =
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vc4->prog.fs->num_inputs;
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rec.fragment_shader_code_address =
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cl_address(vc4->prog.fs->bo, 0);
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rec.coordinate_shader_attribute_array_select_bits =
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vc4->prog.cs->vattrs_live;
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rec.coordinate_shader_total_attributes_size =
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vc4->prog.cs->vattr_offsets[8];
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rec.coordinate_shader_code_address =
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cl_address(vc4->prog.cs->bo, 0);
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rec.vertex_shader_attribute_array_select_bits =
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vc4->prog.vs->vattrs_live;
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rec.vertex_shader_total_attributes_size =
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vc4->prog.vs->vattr_offsets[8];
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rec.vertex_shader_code_address =
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cl_address(vc4->prog.vs->bo, 0);
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};
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uint32_t max_index = 0xffff;
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for (int i = 0; i < vtx->num_elements; i++) {
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struct pipe_vertex_element *elem = &vtx->pipe[i];
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struct pipe_vertex_buffer *vb =
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&vertexbuf->vb[elem->vertex_buffer_index];
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struct vc4_resource *rsc = vc4_resource(vb->buffer.resource);
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/* not vc4->dirty tracked: vc4->last_index_bias */
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uint32_t offset = (vb->buffer_offset +
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elem->src_offset +
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vb->stride * (info->index_bias +
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extra_index_bias));
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uint32_t vb_size = rsc->bo->size - offset;
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uint32_t elem_size =
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util_format_get_blocksize(elem->src_format);
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cl_emit(&job->shader_rec, ATTRIBUTE_RECORD, attr) {
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attr.address = cl_address(rsc->bo, offset);
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attr.number_of_bytes_minus_1 = elem_size - 1;
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attr.stride = vb->stride;
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attr.coordinate_shader_vpm_offset =
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vc4->prog.cs->vattr_offsets[i];
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attr.vertex_shader_vpm_offset =
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vc4->prog.vs->vattr_offsets[i];
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}
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if (vb->stride > 0) {
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max_index = MIN2(max_index,
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(vb_size - elem_size) / vb->stride);
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}
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}
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if (vtx->num_elements == 0) {
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assert(num_elements_emit == 1);
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struct vc4_bo *bo = vc4_bo_alloc(vc4->screen, 4096, "scratch VBO");
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cl_emit(&job->shader_rec, ATTRIBUTE_RECORD, attr) {
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attr.address = cl_address(bo, 0);
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attr.number_of_bytes_minus_1 = 16 - 1;
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attr.stride = 0;
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attr.coordinate_shader_vpm_offset = 0;
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attr.vertex_shader_vpm_offset = 0;
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}
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}
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cl_emit(&job->bcl, GL_SHADER_STATE, shader_state) {
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/* Note that number of attributes == 0 in the packet means 8
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* attributes. This field also contains the offset into
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* shader_rec.
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*/
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assert(vtx->num_elements <= 8);
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shader_state.number_of_attribute_arrays =
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num_elements_emit & 0x7;
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}
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vc4_write_uniforms(vc4, vc4->prog.fs,
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&vc4->constbuf[PIPE_SHADER_FRAGMENT],
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&vc4->fragtex);
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vc4_write_uniforms(vc4, vc4->prog.vs,
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&vc4->constbuf[PIPE_SHADER_VERTEX],
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&vc4->verttex);
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vc4_write_uniforms(vc4, vc4->prog.cs,
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&vc4->constbuf[PIPE_SHADER_VERTEX],
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&vc4->verttex);
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vc4->last_index_bias = info->index_bias + extra_index_bias;
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vc4->max_index = max_index;
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job->shader_rec_count++;
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}
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/**
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* HW-2116 workaround: Flush the batch before triggering the hardware state
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* counter wraparound behavior.
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*
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* State updates are tracked by a global counter which increments at the first
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* state update after a draw or a START_BINNING. Tiles can then have their
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* state updated at draw time with a set of cheap checks for whether the
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* state's copy of the global counter matches the global counter the last time
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* that state was written to the tile.
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*
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* The state counters are relatively small and wrap around quickly, so you
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* could get false negatives for needing to update a particular state in the
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* tile. To avoid this, the hardware attempts to write all of the state in
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* the tile at wraparound time. This apparently is broken, so we just flush
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* everything before that behavior is triggered. A batch flush is sufficient
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* to get our current contents drawn and reset the counters to 0.
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*
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* Note that we can't just use VC4_PACKET_FLUSH_ALL, because that caps the
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* tiles with VC4_PACKET_RETURN_FROM_LIST.
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*/
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static void
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vc4_hw_2116_workaround(struct pipe_context *pctx, int vert_count)
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{
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struct vc4_context *vc4 = vc4_context(pctx);
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struct vc4_job *job = vc4_get_job_for_fbo(vc4);
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if (job->draw_calls_queued + vert_count / 65535 >= VC4_HW_2116_COUNT) {
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perf_debug("Flushing batch due to HW-2116 workaround "
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"(too many draw calls per scene\n");
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vc4_job_submit(vc4, job);
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}
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}
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static void
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vc4_draw_vbo(struct pipe_context *pctx, const struct pipe_draw_info *info)
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{
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struct vc4_context *vc4 = vc4_context(pctx);
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struct pipe_draw_info local_info;
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if (!info->count_from_stream_output && !info->indirect &&
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!info->primitive_restart &&
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!u_trim_pipe_prim(info->mode, (unsigned*)&info->count))
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return;
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if (info->mode >= PIPE_PRIM_QUADS) {
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if (info->mode == PIPE_PRIM_QUADS &&
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info->count == 4 &&
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!vc4->rasterizer->base.flatshade) {
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local_info = *info;
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local_info.mode = PIPE_PRIM_TRIANGLE_FAN;
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info = &local_info;
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} else {
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util_primconvert_save_rasterizer_state(vc4->primconvert, &vc4->rasterizer->base);
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util_primconvert_draw_vbo(vc4->primconvert, info);
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perf_debug("Fallback conversion for %d %s vertices\n",
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info->count, u_prim_name(info->mode));
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return;
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}
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}
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/* Before setting up the draw, do any fixup blits necessary. */
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vc4_predraw_check_textures(pctx, &vc4->verttex);
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vc4_predraw_check_textures(pctx, &vc4->fragtex);
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vc4_hw_2116_workaround(pctx, info->count);
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struct vc4_job *job = vc4_get_job_for_fbo(vc4);
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/* Make sure that the raster order flags haven't changed, which can
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* only be set at job granularity.
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*/
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if (job->flags != vc4->rasterizer->tile_raster_order_flags) {
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vc4_job_submit(vc4, job);
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job = vc4_get_job_for_fbo(vc4);
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}
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vc4_get_draw_cl_space(job, info->count);
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if (vc4->prim_mode != info->mode) {
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vc4->prim_mode = info->mode;
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vc4->dirty |= VC4_DIRTY_PRIM_MODE;
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}
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vc4_start_draw(vc4);
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if (!vc4_update_compiled_shaders(vc4, info->mode)) {
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debug_warn_once("shader compile failed, skipping draw call.\n");
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return;
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}
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vc4_emit_state(pctx);
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bool needs_drawarrays_shader_state = false;
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if ((vc4->dirty & (VC4_DIRTY_VTXBUF |
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VC4_DIRTY_VTXSTATE |
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VC4_DIRTY_PRIM_MODE |
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VC4_DIRTY_RASTERIZER |
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VC4_DIRTY_COMPILED_CS |
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VC4_DIRTY_COMPILED_VS |
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VC4_DIRTY_COMPILED_FS |
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vc4->prog.cs->uniform_dirty_bits |
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vc4->prog.vs->uniform_dirty_bits |
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vc4->prog.fs->uniform_dirty_bits)) ||
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vc4->last_index_bias != info->index_bias) {
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if (info->index_size)
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vc4_emit_gl_shader_state(vc4, info, 0);
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else
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needs_drawarrays_shader_state = true;
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}
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vc4->dirty = 0;
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/* Note that the primitive type fields match with OpenGL/gallium
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* definitions, up to but not including QUADS.
|
*/
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if (info->index_size) {
|
uint32_t index_size = info->index_size;
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uint32_t offset = info->start * index_size;
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struct pipe_resource *prsc;
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if (info->index_size == 4) {
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prsc = vc4_get_shadow_index_buffer(pctx, info,
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offset,
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info->count, &offset);
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index_size = 2;
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} else {
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if (info->has_user_indices) {
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prsc = NULL;
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u_upload_data(vc4->uploader, 0,
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info->count * index_size, 4,
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info->index.user,
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&offset, &prsc);
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} else {
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prsc = info->index.resource;
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}
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}
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struct vc4_resource *rsc = vc4_resource(prsc);
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struct vc4_cl_out *bcl = cl_start(&job->bcl);
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/* The original design for the VC4 kernel UABI had multiple
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* packets that used relocations in the BCL (some of which
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* needed two BOs), but later modifications eliminated all but
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* this one usage. We have an arbitrary 32-bit offset value,
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* and need to also supply an arbitrary 32-bit index buffer
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* GEM handle, so we have this fake packet we emit in our BCL
|
* to be validated, which the kernel uses at validation time
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* to perform the relocation in the IB packet (without
|
* emitting to the actual HW).
|
*/
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uint32_t hindex = vc4_gem_hindex(job, rsc->bo);
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if (job->last_gem_handle_hindex != hindex) {
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cl_u8(&bcl, VC4_PACKET_GEM_HANDLES);
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cl_u32(&bcl, hindex);
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cl_u32(&bcl, 0);
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job->last_gem_handle_hindex = hindex;
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}
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cl_u8(&bcl, VC4_PACKET_GL_INDEXED_PRIMITIVE);
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cl_u8(&bcl,
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info->mode |
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(index_size == 2 ?
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VC4_INDEX_BUFFER_U16:
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VC4_INDEX_BUFFER_U8));
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cl_u32(&bcl, info->count);
|
cl_u32(&bcl, offset);
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cl_u32(&bcl, vc4->max_index);
|
|
cl_end(&job->bcl, bcl);
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job->draw_calls_queued++;
|
|
if (info->index_size == 4 || info->has_user_indices)
|
pipe_resource_reference(&prsc, NULL);
|
} else {
|
uint32_t count = info->count;
|
uint32_t start = info->start;
|
uint32_t extra_index_bias = 0;
|
static const uint32_t max_verts = 65535;
|
|
/* GFXH-515 / SW-5891: The binner emits 16 bit indices for
|
* drawarrays, which means that if start + count > 64k it
|
* would truncate the top bits. Work around this by emitting
|
* a limited number of primitives at a time and reemitting the
|
* shader state pointing farther down the vertex attribute
|
* arrays.
|
*
|
* To do this properly for line loops or trifans, we'd need to
|
* make a new VB containing the first vertex plus whatever
|
* remainder.
|
*/
|
if (start + count > max_verts) {
|
extra_index_bias = start;
|
start = 0;
|
needs_drawarrays_shader_state = true;
|
}
|
|
while (count) {
|
uint32_t this_count = count;
|
uint32_t step = count;
|
|
if (needs_drawarrays_shader_state) {
|
vc4_emit_gl_shader_state(vc4, info,
|
extra_index_bias);
|
}
|
|
if (count > max_verts) {
|
switch (info->mode) {
|
case PIPE_PRIM_POINTS:
|
this_count = step = max_verts;
|
break;
|
case PIPE_PRIM_LINES:
|
this_count = step = max_verts - (max_verts % 2);
|
break;
|
case PIPE_PRIM_LINE_STRIP:
|
this_count = max_verts;
|
step = max_verts - 1;
|
break;
|
case PIPE_PRIM_LINE_LOOP:
|
this_count = max_verts;
|
step = max_verts - 1;
|
debug_warn_once("unhandled line loop "
|
"looping behavior with "
|
">65535 verts\n");
|
break;
|
case PIPE_PRIM_TRIANGLES:
|
this_count = step = max_verts - (max_verts % 3);
|
break;
|
case PIPE_PRIM_TRIANGLE_STRIP:
|
this_count = max_verts;
|
step = max_verts - 2;
|
break;
|
default:
|
debug_warn_once("unhandled primitive "
|
"max vert count, truncating\n");
|
this_count = step = max_verts;
|
}
|
}
|
|
cl_emit(&job->bcl, VERTEX_ARRAY_PRIMITIVES, array) {
|
array.primitive_mode = info->mode;
|
array.length = this_count;
|
array.index_of_first_vertex = start;
|
}
|
job->draw_calls_queued++;
|
|
count -= step;
|
extra_index_bias += start + step;
|
start = 0;
|
needs_drawarrays_shader_state = true;
|
}
|
}
|
|
/* We shouldn't have tripped the HW_2116 bug with the GFXH-515
|
* workaround.
|
*/
|
assert(job->draw_calls_queued <= VC4_HW_2116_COUNT);
|
|
if (vc4->zsa && vc4->framebuffer.zsbuf) {
|
struct vc4_resource *rsc =
|
vc4_resource(vc4->framebuffer.zsbuf->texture);
|
|
if (vc4->zsa->base.depth.enabled) {
|
job->resolve |= PIPE_CLEAR_DEPTH;
|
rsc->initialized_buffers = PIPE_CLEAR_DEPTH;
|
}
|
|
if (vc4->zsa->base.stencil[0].enabled) {
|
job->resolve |= PIPE_CLEAR_STENCIL;
|
rsc->initialized_buffers |= PIPE_CLEAR_STENCIL;
|
}
|
}
|
|
job->resolve |= PIPE_CLEAR_COLOR0;
|
|
/* If we've used half of the presumably 256MB CMA area, flush the job
|
* so that we don't accumulate a job that will end up not being
|
* executable.
|
*/
|
if (job->bo_space > 128 * 1024 * 1024)
|
vc4_flush(pctx);
|
|
if (vc4_debug & VC4_DEBUG_ALWAYS_FLUSH)
|
vc4_flush(pctx);
|
}
|
|
static uint32_t
|
pack_rgba(enum pipe_format format, const float *rgba)
|
{
|
union util_color uc;
|
util_pack_color(rgba, format, &uc);
|
if (util_format_get_blocksize(format) == 2)
|
return uc.us;
|
else
|
return uc.ui[0];
|
}
|
|
static void
|
vc4_clear(struct pipe_context *pctx, unsigned buffers,
|
const union pipe_color_union *color, double depth, unsigned stencil)
|
{
|
struct vc4_context *vc4 = vc4_context(pctx);
|
struct vc4_job *job = vc4_get_job_for_fbo(vc4);
|
|
if (buffers & PIPE_CLEAR_DEPTHSTENCIL) {
|
struct vc4_resource *rsc =
|
vc4_resource(vc4->framebuffer.zsbuf->texture);
|
unsigned zsclear = buffers & PIPE_CLEAR_DEPTHSTENCIL;
|
|
/* Clearing ZS will clear both Z and stencil, so if we're
|
* trying to clear just one then we need to draw a quad to do
|
* it instead. We need to do this before setting up
|
* tile-based clears in vc4->job, because the blitter may
|
* submit the current job.
|
*/
|
if ((zsclear == PIPE_CLEAR_DEPTH ||
|
zsclear == PIPE_CLEAR_STENCIL) &&
|
(rsc->initialized_buffers & ~(zsclear | job->cleared)) &&
|
util_format_is_depth_and_stencil(vc4->framebuffer.zsbuf->format)) {
|
static const union pipe_color_union dummy_color = {};
|
|
perf_debug("Partial clear of Z+stencil buffer, "
|
"drawing a quad instead of fast clearing\n");
|
vc4_blitter_save(vc4);
|
util_blitter_clear(vc4->blitter,
|
vc4->framebuffer.width,
|
vc4->framebuffer.height,
|
1,
|
zsclear,
|
&dummy_color, depth, stencil);
|
buffers &= ~zsclear;
|
if (!buffers)
|
return;
|
job = vc4_get_job_for_fbo(vc4);
|
}
|
}
|
|
/* We can't flag new buffers for clearing once we've queued draws. We
|
* could avoid this by using the 3d engine to clear.
|
*/
|
if (job->draw_calls_queued) {
|
perf_debug("Flushing rendering to process new clear.\n");
|
vc4_job_submit(vc4, job);
|
job = vc4_get_job_for_fbo(vc4);
|
}
|
|
if (buffers & PIPE_CLEAR_COLOR0) {
|
struct vc4_resource *rsc =
|
vc4_resource(vc4->framebuffer.cbufs[0]->texture);
|
uint32_t clear_color;
|
|
if (vc4_rt_format_is_565(vc4->framebuffer.cbufs[0]->format)) {
|
/* In 565 mode, the hardware will be packing our color
|
* for us.
|
*/
|
clear_color = pack_rgba(PIPE_FORMAT_R8G8B8A8_UNORM,
|
color->f);
|
} else {
|
/* Otherwise, we need to do this packing because we
|
* support multiple swizzlings of RGBA8888.
|
*/
|
clear_color =
|
pack_rgba(vc4->framebuffer.cbufs[0]->format,
|
color->f);
|
}
|
job->clear_color[0] = job->clear_color[1] = clear_color;
|
rsc->initialized_buffers |= (buffers & PIPE_CLEAR_COLOR0);
|
}
|
|
if (buffers & PIPE_CLEAR_DEPTHSTENCIL) {
|
struct vc4_resource *rsc =
|
vc4_resource(vc4->framebuffer.zsbuf->texture);
|
|
/* Though the depth buffer is stored with Z in the high 24,
|
* for this field we just need to store it in the low 24.
|
*/
|
if (buffers & PIPE_CLEAR_DEPTH) {
|
job->clear_depth = util_pack_z(PIPE_FORMAT_Z24X8_UNORM,
|
depth);
|
}
|
if (buffers & PIPE_CLEAR_STENCIL)
|
job->clear_stencil = stencil;
|
|
rsc->initialized_buffers |= (buffers & PIPE_CLEAR_DEPTHSTENCIL);
|
}
|
|
job->draw_min_x = 0;
|
job->draw_min_y = 0;
|
job->draw_max_x = vc4->framebuffer.width;
|
job->draw_max_y = vc4->framebuffer.height;
|
job->cleared |= buffers;
|
job->resolve |= buffers;
|
|
vc4_start_draw(vc4);
|
}
|
|
static void
|
vc4_clear_render_target(struct pipe_context *pctx, struct pipe_surface *ps,
|
const union pipe_color_union *color,
|
unsigned x, unsigned y, unsigned w, unsigned h,
|
bool render_condition_enabled)
|
{
|
fprintf(stderr, "unimpl: clear RT\n");
|
}
|
|
static void
|
vc4_clear_depth_stencil(struct pipe_context *pctx, struct pipe_surface *ps,
|
unsigned buffers, double depth, unsigned stencil,
|
unsigned x, unsigned y, unsigned w, unsigned h,
|
bool render_condition_enabled)
|
{
|
fprintf(stderr, "unimpl: clear DS\n");
|
}
|
|
void
|
vc4_draw_init(struct pipe_context *pctx)
|
{
|
pctx->draw_vbo = vc4_draw_vbo;
|
pctx->clear = vc4_clear;
|
pctx->clear_render_target = vc4_clear_render_target;
|
pctx->clear_depth_stencil = vc4_clear_depth_stencil;
|
}
|
