/*
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* Copyright © 2014 Broadcom
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* Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#ifndef VC4_CONTEXT_H
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#define VC4_CONTEXT_H
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#include <stdio.h>
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#include "pipe/p_context.h"
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#include "pipe/p_state.h"
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#include "util/slab.h"
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#include "xf86drm.h"
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#define __user
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#include "vc4_drm.h"
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#include "vc4_bufmgr.h"
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#include "vc4_resource.h"
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#include "vc4_cl.h"
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#include "vc4_qir.h"
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#ifndef DRM_VC4_PARAM_SUPPORTS_ETC1
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#define DRM_VC4_PARAM_SUPPORTS_ETC1 4
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#endif
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#ifndef DRM_VC4_PARAM_SUPPORTS_THREADED_FS
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#define DRM_VC4_PARAM_SUPPORTS_THREADED_FS 5
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#endif
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#ifdef USE_VC4_SIMULATOR
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#define using_vc4_simulator true
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#else
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#define using_vc4_simulator false
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#endif
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#define VC4_DIRTY_BLEND (1 << 0)
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#define VC4_DIRTY_RASTERIZER (1 << 1)
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#define VC4_DIRTY_ZSA (1 << 2)
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#define VC4_DIRTY_FRAGTEX (1 << 3)
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#define VC4_DIRTY_VERTTEX (1 << 4)
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#define VC4_DIRTY_BLEND_COLOR (1 << 7)
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#define VC4_DIRTY_STENCIL_REF (1 << 8)
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#define VC4_DIRTY_SAMPLE_MASK (1 << 9)
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#define VC4_DIRTY_FRAMEBUFFER (1 << 10)
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#define VC4_DIRTY_STIPPLE (1 << 11)
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#define VC4_DIRTY_VIEWPORT (1 << 12)
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#define VC4_DIRTY_CONSTBUF (1 << 13)
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#define VC4_DIRTY_VTXSTATE (1 << 14)
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#define VC4_DIRTY_VTXBUF (1 << 15)
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#define VC4_DIRTY_SCISSOR (1 << 17)
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#define VC4_DIRTY_FLAT_SHADE_FLAGS (1 << 18)
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#define VC4_DIRTY_PRIM_MODE (1 << 19)
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#define VC4_DIRTY_CLIP (1 << 20)
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#define VC4_DIRTY_UNCOMPILED_VS (1 << 21)
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#define VC4_DIRTY_UNCOMPILED_FS (1 << 22)
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#define VC4_DIRTY_COMPILED_CS (1 << 23)
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#define VC4_DIRTY_COMPILED_VS (1 << 24)
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#define VC4_DIRTY_COMPILED_FS (1 << 25)
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#define VC4_DIRTY_FS_INPUTS (1 << 26)
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struct vc4_sampler_view {
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struct pipe_sampler_view base;
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uint32_t texture_p0;
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uint32_t texture_p1;
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bool force_first_level;
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/**
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* Resource containing the actual texture that will be sampled.
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*
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* We may need to rebase the .base.texture resource to work around the
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* lack of GL_TEXTURE_BASE_LEVEL, or to upload the texture as tiled.
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*/
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struct pipe_resource *texture;
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};
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struct vc4_sampler_state {
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struct pipe_sampler_state base;
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uint32_t texture_p1;
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};
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struct vc4_texture_stateobj {
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struct pipe_sampler_view *textures[PIPE_MAX_SAMPLERS];
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unsigned num_textures;
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struct pipe_sampler_state *samplers[PIPE_MAX_SAMPLERS];
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unsigned num_samplers;
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};
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struct vc4_shader_uniform_info {
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enum quniform_contents *contents;
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uint32_t *data;
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uint32_t count;
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uint32_t num_texture_samples;
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};
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struct vc4_uncompiled_shader {
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/** A name for this program, so you can track it in shader-db output. */
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uint32_t program_id;
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/** How many variants of this program were compiled, for shader-db. */
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uint32_t compiled_variant_count;
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struct pipe_shader_state base;
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};
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struct vc4_ubo_range {
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/**
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* offset in bytes from the start of the ubo where this range is
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* uploaded.
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*
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* Only set once used is set.
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*/
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uint32_t dst_offset;
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/**
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* offset in bytes from the start of the gallium uniforms where the
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* data comes from.
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*/
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uint32_t src_offset;
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/** size in bytes of this ubo range */
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uint32_t size;
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};
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struct vc4_fs_inputs {
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/**
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* Array of the meanings of the VPM inputs this shader needs.
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*
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* It doesn't include those that aren't part of the VPM, like
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* point/line coordinates.
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*/
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struct vc4_varying_slot *input_slots;
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uint32_t num_inputs;
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};
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struct vc4_compiled_shader {
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uint64_t program_id;
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struct vc4_bo *bo;
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struct vc4_shader_uniform_info uniforms;
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struct vc4_ubo_range *ubo_ranges;
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uint32_t num_ubo_ranges;
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uint32_t ubo_size;
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/**
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* VC4_DIRTY_* flags that, when set in vc4->dirty, mean that the
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* uniforms have to be rewritten (and therefore the shader state
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* reemitted).
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*/
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uint32_t uniform_dirty_bits;
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/** bitmask of which inputs are color inputs, for flat shade handling. */
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uint32_t color_inputs;
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bool disable_early_z;
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/* Set if the compile failed, likely due to register allocation
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* failure. In this case, we have no shader to run and should not try
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* to do any draws.
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*/
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bool failed;
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bool fs_threaded;
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uint8_t num_inputs;
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/* Byte offsets for the start of the vertex attributes 0-7, and the
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* total size as "attribute" 8.
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*/
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uint8_t vattr_offsets[9];
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uint8_t vattrs_live;
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const struct vc4_fs_inputs *fs_inputs;
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};
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struct vc4_program_stateobj {
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struct vc4_uncompiled_shader *bind_vs, *bind_fs;
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struct vc4_compiled_shader *cs, *vs, *fs;
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};
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struct vc4_constbuf_stateobj {
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struct pipe_constant_buffer cb[PIPE_MAX_CONSTANT_BUFFERS];
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uint32_t enabled_mask;
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uint32_t dirty_mask;
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};
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struct vc4_vertexbuf_stateobj {
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struct pipe_vertex_buffer vb[PIPE_MAX_ATTRIBS];
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unsigned count;
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uint32_t enabled_mask;
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uint32_t dirty_mask;
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};
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struct vc4_vertex_stateobj {
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struct pipe_vertex_element pipe[PIPE_MAX_ATTRIBS];
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unsigned num_elements;
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};
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/* Hash table key for vc4->jobs */
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struct vc4_job_key {
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struct pipe_surface *cbuf;
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struct pipe_surface *zsbuf;
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};
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/**
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* A complete bin/render job.
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*
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* This is all of the state necessary to submit a bin/render to the kernel.
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* We want to be able to have multiple in progress at a time, so that we don't
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* need to flush an existing CL just to switch to rendering to a new render
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* target (which would mean reading back from the old render target when
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* starting to render to it again).
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*/
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struct vc4_job {
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struct vc4_cl bcl;
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struct vc4_cl shader_rec;
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struct vc4_cl uniforms;
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struct vc4_cl bo_handles;
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struct vc4_cl bo_pointers;
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uint32_t shader_rec_count;
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/**
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* Amount of memory used by the BOs in bo_pointers.
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*
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* Used for checking when we should flush the job early so we don't
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* OOM.
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*/
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uint32_t bo_space;
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/* Last BO hindex referenced from VC4_PACKET_GEM_HANDLES. */
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uint32_t last_gem_handle_hindex;
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/** @{ Surfaces to submit rendering for. */
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struct pipe_surface *color_read;
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struct pipe_surface *color_write;
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struct pipe_surface *zs_read;
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struct pipe_surface *zs_write;
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struct pipe_surface *msaa_color_write;
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struct pipe_surface *msaa_zs_write;
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/** @} */
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/** @{
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* Bounding box of the scissor across all queued drawing.
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*
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* Note that the max values are exclusive.
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*/
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uint32_t draw_min_x;
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uint32_t draw_min_y;
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uint32_t draw_max_x;
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uint32_t draw_max_y;
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/** @} */
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/** @{
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* Width/height of the color framebuffer being rendered to,
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* for VC4_TILE_RENDERING_MODE_CONFIG.
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*/
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uint32_t draw_width;
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uint32_t draw_height;
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/** @} */
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/** @{ Tile information, depending on MSAA and float color buffer. */
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uint32_t draw_tiles_x; /** @< Number of tiles wide for framebuffer. */
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uint32_t draw_tiles_y; /** @< Number of tiles high for framebuffer. */
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uint32_t tile_width; /** @< Width of a tile. */
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uint32_t tile_height; /** @< Height of a tile. */
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/** Whether the current rendering is in a 4X MSAA tile buffer. */
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bool msaa;
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/** @} */
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/* Bitmask of PIPE_CLEAR_* of buffers that were cleared before the
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* first rendering.
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*/
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uint32_t cleared;
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/* Bitmask of PIPE_CLEAR_* of buffers that have been rendered to
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* (either clears or draws).
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*/
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uint32_t resolve;
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uint32_t clear_color[2];
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uint32_t clear_depth; /**< 24-bit unorm depth */
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uint8_t clear_stencil;
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/**
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* Set if some drawing (triangles, blits, or just a glClear()) has
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* been done to the FBO, meaning that we need to
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* DRM_IOCTL_VC4_SUBMIT_CL.
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*/
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bool needs_flush;
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/**
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* Number of draw calls (not counting full buffer clears) queued in
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* the current job.
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*/
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uint32_t draw_calls_queued;
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/** Any flags to be passed in drm_vc4_submit_cl.flags. */
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uint32_t flags;
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struct vc4_job_key key;
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};
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struct vc4_context {
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struct pipe_context base;
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int fd;
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struct vc4_screen *screen;
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/** The 3D rendering job for the currently bound FBO. */
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struct vc4_job *job;
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/* Map from struct vc4_job_key to the job for that FBO.
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*/
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struct hash_table *jobs;
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/**
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* Map from vc4_resource to a job writing to that resource.
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*
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* Primarily for flushing jobs rendering to textures that are now
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* being read from.
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*/
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struct hash_table *write_jobs;
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struct slab_child_pool transfer_pool;
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struct blitter_context *blitter;
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/** bitfield of VC4_DIRTY_* */
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uint32_t dirty;
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struct primconvert_context *primconvert;
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struct hash_table *fs_cache, *vs_cache;
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struct set *fs_inputs_set;
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uint32_t next_uncompiled_program_id;
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uint64_t next_compiled_program_id;
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struct ra_regs *regs;
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unsigned int reg_class_any[2];
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unsigned int reg_class_a_or_b[2];
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unsigned int reg_class_a_or_b_or_acc[2];
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unsigned int reg_class_r0_r3;
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unsigned int reg_class_r4_or_a[2];
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unsigned int reg_class_a[2];
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uint8_t prim_mode;
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/** Maximum index buffer valid for the current shader_rec. */
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uint32_t max_index;
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/** Last index bias baked into the current shader_rec. */
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uint32_t last_index_bias;
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/** Seqno of the last CL flush's job. */
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uint64_t last_emit_seqno;
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struct u_upload_mgr *uploader;
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/** @{ Current pipeline state objects */
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struct pipe_scissor_state scissor;
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struct pipe_blend_state *blend;
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struct vc4_rasterizer_state *rasterizer;
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struct vc4_depth_stencil_alpha_state *zsa;
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struct vc4_texture_stateobj verttex, fragtex;
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struct vc4_program_stateobj prog;
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struct vc4_vertex_stateobj *vtx;
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struct {
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struct pipe_blend_color f;
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uint8_t ub[4];
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} blend_color;
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struct pipe_stencil_ref stencil_ref;
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unsigned sample_mask;
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struct pipe_framebuffer_state framebuffer;
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struct pipe_poly_stipple stipple;
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struct pipe_clip_state clip;
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struct pipe_viewport_state viewport;
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struct vc4_constbuf_stateobj constbuf[PIPE_SHADER_TYPES];
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struct vc4_vertexbuf_stateobj vertexbuf;
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/** @} */
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};
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struct vc4_rasterizer_state {
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struct pipe_rasterizer_state base;
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/* VC4_CONFIGURATION_BITS */
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uint8_t config_bits[V3D21_CONFIGURATION_BITS_length];
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struct PACKED {
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uint8_t depth_offset[V3D21_DEPTH_OFFSET_length];
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uint8_t point_size[V3D21_POINT_SIZE_length];
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uint8_t line_width[V3D21_LINE_WIDTH_length];
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} packed;
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/** Raster order flags to be passed in struct drm_vc4_submit_cl.flags. */
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uint32_t tile_raster_order_flags;
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};
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struct vc4_depth_stencil_alpha_state {
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struct pipe_depth_stencil_alpha_state base;
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/* VC4_CONFIGURATION_BITS */
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uint8_t config_bits[V3D21_CONFIGURATION_BITS_length];
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/** Uniforms for stencil state.
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*
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* Index 0 is either the front config, or the front-and-back config.
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* Index 1 is the back config if doing separate back stencil.
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* Index 2 is the writemask config if it's not a common mask value.
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*/
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uint32_t stencil_uniforms[3];
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};
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#define perf_debug(...) do { \
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if (unlikely(vc4_debug & VC4_DEBUG_PERF)) \
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fprintf(stderr, __VA_ARGS__); \
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} while (0)
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static inline struct vc4_context *
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vc4_context(struct pipe_context *pcontext)
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{
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return (struct vc4_context *)pcontext;
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}
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static inline struct vc4_sampler_view *
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vc4_sampler_view(struct pipe_sampler_view *psview)
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{
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return (struct vc4_sampler_view *)psview;
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}
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static inline struct vc4_sampler_state *
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vc4_sampler_state(struct pipe_sampler_state *psampler)
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{
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return (struct vc4_sampler_state *)psampler;
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}
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struct pipe_context *vc4_context_create(struct pipe_screen *pscreen,
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void *priv, unsigned flags);
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void vc4_draw_init(struct pipe_context *pctx);
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void vc4_state_init(struct pipe_context *pctx);
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void vc4_program_init(struct pipe_context *pctx);
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void vc4_program_fini(struct pipe_context *pctx);
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void vc4_query_init(struct pipe_context *pctx);
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void vc4_simulator_init(struct vc4_screen *screen);
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void vc4_simulator_destroy(struct vc4_screen *screen);
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int vc4_simulator_flush(struct vc4_context *vc4,
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struct drm_vc4_submit_cl *args,
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struct vc4_job *job);
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int vc4_simulator_ioctl(int fd, unsigned long request, void *arg);
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void vc4_simulator_open_from_handle(int fd, uint32_t winsys_stride,
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int handle, uint32_t size);
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static inline int
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vc4_ioctl(int fd, unsigned long request, void *arg)
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{
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if (using_vc4_simulator)
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return vc4_simulator_ioctl(fd, request, arg);
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else
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return drmIoctl(fd, request, arg);
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}
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void vc4_set_shader_uniform_dirty_flags(struct vc4_compiled_shader *shader);
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void vc4_write_uniforms(struct vc4_context *vc4,
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struct vc4_compiled_shader *shader,
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struct vc4_constbuf_stateobj *cb,
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struct vc4_texture_stateobj *texstate);
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void vc4_flush(struct pipe_context *pctx);
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void vc4_job_init(struct vc4_context *vc4);
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struct vc4_job *vc4_get_job(struct vc4_context *vc4,
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struct pipe_surface *cbuf,
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struct pipe_surface *zsbuf);
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struct vc4_job *vc4_get_job_for_fbo(struct vc4_context *vc4);
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void vc4_job_submit(struct vc4_context *vc4, struct vc4_job *job);
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void vc4_flush_jobs_writing_resource(struct vc4_context *vc4,
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struct pipe_resource *prsc);
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void vc4_flush_jobs_reading_resource(struct vc4_context *vc4,
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struct pipe_resource *prsc);
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void vc4_emit_state(struct pipe_context *pctx);
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void vc4_generate_code(struct vc4_context *vc4, struct vc4_compile *c);
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struct qpu_reg *vc4_register_allocate(struct vc4_context *vc4, struct vc4_compile *c);
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bool vc4_update_compiled_shaders(struct vc4_context *vc4, uint8_t prim_mode);
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bool vc4_rt_format_supported(enum pipe_format f);
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bool vc4_rt_format_is_565(enum pipe_format f);
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bool vc4_tex_format_supported(enum pipe_format f);
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uint8_t vc4_get_tex_format(enum pipe_format f);
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const uint8_t *vc4_get_format_swizzle(enum pipe_format f);
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void vc4_init_query_functions(struct vc4_context *vc4);
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void vc4_blit(struct pipe_context *pctx, const struct pipe_blit_info *blit_info);
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void vc4_blitter_save(struct vc4_context *vc4);
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#endif /* VC4_CONTEXT_H */
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