/**************************************************************************
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*
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* Copyright 2011 Advanced Micro Devices, Inc.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
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* IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
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* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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**************************************************************************/
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#include "si_pipe.h"
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#include "radeon/radeon_video.h"
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#include "radeon/radeon_uvd.h"
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#include "radeon/radeon_vce.h"
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#include "radeon/radeon_vcn_dec.h"
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#include "radeon/radeon_vcn_enc.h"
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/**
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* creates an video buffer with an UVD compatible memory layout
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*/
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struct pipe_video_buffer *si_video_buffer_create(struct pipe_context *pipe,
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const struct pipe_video_buffer *tmpl)
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{
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struct si_context *ctx = (struct si_context *)pipe;
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struct r600_texture *resources[VL_NUM_COMPONENTS] = {};
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struct radeon_surf *surfaces[VL_NUM_COMPONENTS] = {};
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struct pb_buffer **pbs[VL_NUM_COMPONENTS] = {};
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const enum pipe_format *resource_formats;
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struct pipe_video_buffer vidtemplate;
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struct pipe_resource templ;
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unsigned i, array_size;
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assert(pipe);
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/* first create the needed resources as "normal" textures */
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resource_formats = vl_video_buffer_formats(pipe->screen, tmpl->buffer_format);
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if (!resource_formats)
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return NULL;
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array_size = tmpl->interlaced ? 2 : 1;
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vidtemplate = *tmpl;
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vidtemplate.width = align(tmpl->width, VL_MACROBLOCK_WIDTH);
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vidtemplate.height = align(tmpl->height / array_size, VL_MACROBLOCK_HEIGHT);
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assert(resource_formats[0] != PIPE_FORMAT_NONE);
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for (i = 0; i < VL_NUM_COMPONENTS; ++i) {
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if (resource_formats[i] != PIPE_FORMAT_NONE) {
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vl_video_buffer_template(&templ, &vidtemplate,
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resource_formats[i], 1,
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array_size, PIPE_USAGE_DEFAULT, i);
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/* Set PIPE_BIND_SHARED to avoid reallocation in r600_texture_get_handle,
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* which can't handle joined surfaces. */
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/* TODO: get tiling working */
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templ.bind = PIPE_BIND_LINEAR | PIPE_BIND_SHARED;
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resources[i] = (struct r600_texture *)
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pipe->screen->resource_create(pipe->screen, &templ);
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if (!resources[i])
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goto error;
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}
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}
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for (i = 0; i < VL_NUM_COMPONENTS; ++i) {
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if (!resources[i])
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continue;
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surfaces[i] = & resources[i]->surface;
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pbs[i] = &resources[i]->resource.buf;
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}
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si_vid_join_surfaces(&ctx->b, pbs, surfaces);
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for (i = 0; i < VL_NUM_COMPONENTS; ++i) {
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if (!resources[i])
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continue;
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/* reset the address */
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resources[i]->resource.gpu_address = ctx->b.ws->buffer_get_virtual_address(
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resources[i]->resource.buf);
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}
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vidtemplate.height *= array_size;
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return vl_video_buffer_create_ex2(pipe, &vidtemplate, (struct pipe_resource **)resources);
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error:
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for (i = 0; i < VL_NUM_COMPONENTS; ++i)
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r600_texture_reference(&resources[i], NULL);
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return NULL;
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}
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/* set the decoding target buffer offsets */
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static struct pb_buffer* si_uvd_set_dtb(struct ruvd_msg *msg, struct vl_video_buffer *buf)
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{
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struct si_screen *sscreen = (struct si_screen*)buf->base.context->screen;
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struct r600_texture *luma = (struct r600_texture *)buf->resources[0];
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struct r600_texture *chroma = (struct r600_texture *)buf->resources[1];
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enum ruvd_surface_type type = (sscreen->info.chip_class >= GFX9) ?
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RUVD_SURFACE_TYPE_GFX9 :
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RUVD_SURFACE_TYPE_LEGACY;
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msg->body.decode.dt_field_mode = buf->base.interlaced;
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si_uvd_set_dt_surfaces(msg, &luma->surface, (chroma) ? &chroma->surface : NULL, type);
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return luma->resource.buf;
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}
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/* get the radeon resources for VCE */
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static void si_vce_get_buffer(struct pipe_resource *resource,
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struct pb_buffer **handle,
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struct radeon_surf **surface)
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{
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struct r600_texture *res = (struct r600_texture *)resource;
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if (handle)
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*handle = res->resource.buf;
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if (surface)
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*surface = &res->surface;
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}
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/**
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* creates an UVD compatible decoder
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*/
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struct pipe_video_codec *si_uvd_create_decoder(struct pipe_context *context,
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const struct pipe_video_codec *templ)
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{
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struct si_context *ctx = (struct si_context *)context;
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bool vcn = (ctx->b.family == CHIP_RAVEN) ? true : false;
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if (templ->entrypoint == PIPE_VIDEO_ENTRYPOINT_ENCODE)
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return (vcn) ? radeon_create_encoder(context, templ, ctx->b.ws, si_vce_get_buffer) :
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si_vce_create_encoder(context, templ, ctx->b.ws, si_vce_get_buffer);
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return (vcn) ? radeon_create_decoder(context, templ) :
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si_common_uvd_create_decoder(context, templ, si_uvd_set_dtb);
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}
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