/*
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* Copyright 2012 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* on the rights to use, copy, modify, merge, publish, distribute, sub
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* license, and/or sell copies of the Software, and to permit persons to whom
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* the Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
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* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
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* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
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* USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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#ifndef SI_STATE_H
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#define SI_STATE_H
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#include "si_pm4.h"
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#include "radeon/r600_pipe_common.h"
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#include "pipebuffer/pb_slab.h"
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#define SI_NUM_GRAPHICS_SHADERS (PIPE_SHADER_TESS_EVAL+1)
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#define SI_NUM_SHADERS (PIPE_SHADER_COMPUTE+1)
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#define SI_MAX_ATTRIBS 16
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#define SI_NUM_VERTEX_BUFFERS SI_MAX_ATTRIBS
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#define SI_NUM_SAMPLERS 32 /* OpenGL textures units per shader */
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#define SI_NUM_CONST_BUFFERS 16
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#define SI_NUM_IMAGES 16
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#define SI_NUM_SHADER_BUFFERS 16
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struct si_screen;
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struct si_shader;
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struct si_shader_selector;
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struct si_state_blend {
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struct si_pm4_state pm4;
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uint32_t cb_target_mask;
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/* Set 0xf or 0x0 (4 bits) per render target if the following is
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* true. ANDed with spi_shader_col_format.
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*/
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unsigned cb_target_enabled_4bit;
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unsigned blend_enable_4bit;
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unsigned need_src_alpha_4bit;
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unsigned commutative_4bit;
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bool alpha_to_coverage:1;
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bool alpha_to_one:1;
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bool dual_src_blend:1;
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bool logicop_enable:1;
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};
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struct si_state_rasterizer {
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struct si_pm4_state pm4;
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/* poly offset states for 16-bit, 24-bit, and 32-bit zbuffers */
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struct si_pm4_state *pm4_poly_offset;
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unsigned pa_sc_line_stipple;
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unsigned pa_cl_clip_cntl;
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float line_width;
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float max_point_size;
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unsigned sprite_coord_enable:8;
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unsigned clip_plane_enable:8;
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unsigned flatshade:1;
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unsigned two_side:1;
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unsigned multisample_enable:1;
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unsigned force_persample_interp:1;
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unsigned line_stipple_enable:1;
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unsigned poly_stipple_enable:1;
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unsigned line_smooth:1;
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unsigned poly_smooth:1;
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unsigned uses_poly_offset:1;
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unsigned clamp_fragment_color:1;
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unsigned clamp_vertex_color:1;
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unsigned rasterizer_discard:1;
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unsigned scissor_enable:1;
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unsigned clip_halfz:1;
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};
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struct si_dsa_stencil_ref_part {
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uint8_t valuemask[2];
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uint8_t writemask[2];
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};
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struct si_dsa_order_invariance {
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/** Whether the final result in Z/S buffers is guaranteed to be
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* invariant under changes to the order in which fragments arrive. */
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bool zs:1;
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/** Whether the set of fragments that pass the combined Z/S test is
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* guaranteed to be invariant under changes to the order in which
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* fragments arrive. */
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bool pass_set:1;
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/** Whether the last fragment that passes the combined Z/S test at each
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* sample is guaranteed to be invariant under changes to the order in
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* which fragments arrive. */
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bool pass_last:1;
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};
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struct si_state_dsa {
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struct si_pm4_state pm4;
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struct si_dsa_stencil_ref_part stencil_ref;
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/* 0 = without stencil buffer, 1 = when both Z and S buffers are present */
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struct si_dsa_order_invariance order_invariance[2];
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ubyte alpha_func:3;
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bool depth_enabled:1;
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bool depth_write_enabled:1;
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bool stencil_enabled:1;
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bool stencil_write_enabled:1;
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bool db_can_write:1;
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};
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struct si_stencil_ref {
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struct r600_atom atom;
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struct pipe_stencil_ref state;
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struct si_dsa_stencil_ref_part dsa_part;
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};
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struct si_vertex_elements
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{
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uint32_t instance_divisors[SI_MAX_ATTRIBS];
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uint32_t rsrc_word3[SI_MAX_ATTRIBS];
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uint16_t src_offset[SI_MAX_ATTRIBS];
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uint8_t fix_fetch[SI_MAX_ATTRIBS];
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uint8_t format_size[SI_MAX_ATTRIBS];
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uint8_t vertex_buffer_index[SI_MAX_ATTRIBS];
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uint8_t count;
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bool uses_instance_divisors;
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uint16_t first_vb_use_mask;
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/* Vertex buffer descriptor list size aligned for optimal prefetch. */
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uint16_t desc_list_byte_size;
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uint16_t instance_divisor_is_one; /* bitmask of inputs */
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uint16_t instance_divisor_is_fetched; /* bitmask of inputs */
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};
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union si_state {
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struct {
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struct si_state_blend *blend;
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struct si_state_rasterizer *rasterizer;
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struct si_state_dsa *dsa;
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struct si_pm4_state *poly_offset;
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struct si_pm4_state *ls;
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struct si_pm4_state *hs;
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struct si_pm4_state *es;
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struct si_pm4_state *gs;
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struct si_pm4_state *vgt_shader_config;
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struct si_pm4_state *vs;
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struct si_pm4_state *ps;
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} named;
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struct si_pm4_state *array[0];
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};
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#define SI_NUM_STATES (sizeof(union si_state) / sizeof(struct si_pm4_state *))
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union si_state_atoms {
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struct {
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/* The order matters. */
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struct r600_atom *render_cond;
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struct r600_atom *streamout_begin;
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struct r600_atom *streamout_enable; /* must be after streamout_begin */
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struct r600_atom *framebuffer;
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struct r600_atom *msaa_sample_locs;
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struct r600_atom *db_render_state;
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struct r600_atom *dpbb_state;
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struct r600_atom *msaa_config;
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struct r600_atom *sample_mask;
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struct r600_atom *cb_render_state;
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struct r600_atom *blend_color;
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struct r600_atom *clip_regs;
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struct r600_atom *clip_state;
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struct r600_atom *shader_pointers;
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struct r600_atom *scissors;
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struct r600_atom *viewports;
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struct r600_atom *stencil_ref;
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struct r600_atom *spi_map;
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struct r600_atom *scratch_state;
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} s;
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struct r600_atom *array[0];
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};
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#define SI_NUM_ATOMS (sizeof(union si_state_atoms)/sizeof(struct r600_atom*))
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struct si_shader_data {
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struct r600_atom atom;
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uint32_t sh_base[SI_NUM_SHADERS];
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};
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/* Private read-write buffer slots. */
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enum {
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SI_ES_RING_ESGS,
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SI_GS_RING_ESGS,
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SI_RING_GSVS,
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SI_VS_STREAMOUT_BUF0,
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SI_VS_STREAMOUT_BUF1,
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SI_VS_STREAMOUT_BUF2,
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SI_VS_STREAMOUT_BUF3,
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SI_HS_CONST_DEFAULT_TESS_LEVELS,
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SI_VS_CONST_INSTANCE_DIVISORS,
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SI_VS_CONST_CLIP_PLANES,
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SI_PS_CONST_POLY_STIPPLE,
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SI_PS_CONST_SAMPLE_POSITIONS,
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SI_NUM_RW_BUFFERS,
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};
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/* Indices into sctx->descriptors, laid out so that gfx and compute pipelines
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* are contiguous:
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*
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* 0 - rw buffers
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* 1 - vertex const and shader buffers
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* 2 - vertex samplers and images
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* 3 - fragment const and shader buffer
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* ...
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* 11 - compute const and shader buffers
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* 12 - compute samplers and images
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*/
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enum {
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SI_SHADER_DESCS_CONST_AND_SHADER_BUFFERS,
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SI_SHADER_DESCS_SAMPLERS_AND_IMAGES,
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SI_NUM_SHADER_DESCS,
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};
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#define SI_DESCS_RW_BUFFERS 0
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#define SI_DESCS_FIRST_SHADER 1
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#define SI_DESCS_FIRST_COMPUTE (SI_DESCS_FIRST_SHADER + \
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PIPE_SHADER_COMPUTE * SI_NUM_SHADER_DESCS)
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#define SI_NUM_DESCS (SI_DESCS_FIRST_SHADER + \
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SI_NUM_SHADERS * SI_NUM_SHADER_DESCS)
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#define SI_DESCS_SHADER_MASK(name) \
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u_bit_consecutive(SI_DESCS_FIRST_SHADER + \
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PIPE_SHADER_##name * SI_NUM_SHADER_DESCS, \
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SI_NUM_SHADER_DESCS)
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/* This represents descriptors in memory, such as buffer resources,
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* image resources, and sampler states.
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*/
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struct si_descriptors {
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/* The list of descriptors in malloc'd memory. */
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uint32_t *list;
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/* The list in mapped GPU memory. */
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uint32_t *gpu_list;
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/* The buffer where the descriptors have been uploaded. */
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struct r600_resource *buffer;
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uint64_t gpu_address;
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/* The maximum number of descriptors. */
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uint32_t num_elements;
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/* Slots that are used by currently-bound shaders.
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* It determines which slots are uploaded.
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*/
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uint32_t first_active_slot;
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uint32_t num_active_slots;
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/* The SGPR index where the 64-bit pointer to the descriptor array will
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* be stored. */
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ubyte shader_userdata_offset;
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/* The size of one descriptor. */
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ubyte element_dw_size;
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/* If there is only one slot enabled, bind it directly instead of
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* uploading descriptors. -1 if disabled. */
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signed char slot_index_to_bind_directly;
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};
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struct si_buffer_resources {
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struct pipe_resource **buffers; /* this has num_buffers elements */
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enum radeon_bo_usage shader_usage:4; /* READ, WRITE, or READWRITE */
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enum radeon_bo_usage shader_usage_constbuf:4;
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enum radeon_bo_priority priority:6;
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enum radeon_bo_priority priority_constbuf:6;
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/* The i-th bit is set if that element is enabled (non-NULL resource). */
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unsigned enabled_mask;
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};
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#define si_pm4_block_idx(member) \
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(offsetof(union si_state, named.member) / sizeof(struct si_pm4_state *))
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#define si_pm4_state_changed(sctx, member) \
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((sctx)->queued.named.member != (sctx)->emitted.named.member)
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#define si_pm4_state_enabled_and_changed(sctx, member) \
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((sctx)->queued.named.member && si_pm4_state_changed(sctx, member))
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#define si_pm4_bind_state(sctx, member, value) \
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do { \
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(sctx)->queued.named.member = (value); \
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(sctx)->dirty_states |= 1 << si_pm4_block_idx(member); \
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} while(0)
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#define si_pm4_delete_state(sctx, member, value) \
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do { \
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if ((sctx)->queued.named.member == (value)) { \
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(sctx)->queued.named.member = NULL; \
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} \
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si_pm4_free_state(sctx, (struct si_pm4_state *)(value), \
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si_pm4_block_idx(member)); \
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} while(0)
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/* si_descriptors.c */
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void si_set_mutable_tex_desc_fields(struct si_screen *sscreen,
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struct r600_texture *tex,
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const struct legacy_surf_level *base_level_info,
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unsigned base_level, unsigned first_level,
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unsigned block_width, bool is_stencil,
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uint32_t *state);
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void si_get_pipe_constant_buffer(struct si_context *sctx, uint shader,
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uint slot, struct pipe_constant_buffer *cbuf);
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void si_get_shader_buffers(struct si_context *sctx,
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enum pipe_shader_type shader,
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uint start_slot, uint count,
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struct pipe_shader_buffer *sbuf);
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void si_set_ring_buffer(struct pipe_context *ctx, uint slot,
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struct pipe_resource *buffer,
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unsigned stride, unsigned num_records,
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bool add_tid, bool swizzle,
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unsigned element_size, unsigned index_stride, uint64_t offset);
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void si_init_all_descriptors(struct si_context *sctx);
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bool si_upload_vertex_buffer_descriptors(struct si_context *sctx);
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bool si_upload_graphics_shader_descriptors(struct si_context *sctx);
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bool si_upload_compute_shader_descriptors(struct si_context *sctx);
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void si_release_all_descriptors(struct si_context *sctx);
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void si_all_descriptors_begin_new_cs(struct si_context *sctx);
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void si_all_resident_buffers_begin_new_cs(struct si_context *sctx);
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void si_upload_const_buffer(struct si_context *sctx, struct r600_resource **rbuffer,
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const uint8_t *ptr, unsigned size, uint32_t *const_offset);
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void si_update_all_texture_descriptors(struct si_context *sctx);
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void si_shader_change_notify(struct si_context *sctx);
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void si_update_needs_color_decompress_masks(struct si_context *sctx);
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void si_emit_graphics_shader_pointers(struct si_context *sctx,
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struct r600_atom *atom);
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void si_emit_compute_shader_pointers(struct si_context *sctx);
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void si_set_rw_buffer(struct si_context *sctx,
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uint slot, const struct pipe_constant_buffer *input);
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void si_set_active_descriptors(struct si_context *sctx, unsigned desc_idx,
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uint64_t new_active_mask);
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void si_set_active_descriptors_for_shader(struct si_context *sctx,
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struct si_shader_selector *sel);
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bool si_bindless_descriptor_can_reclaim_slab(void *priv,
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struct pb_slab_entry *entry);
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struct pb_slab *si_bindless_descriptor_slab_alloc(void *priv, unsigned heap,
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unsigned entry_size,
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unsigned group_index);
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void si_bindless_descriptor_slab_free(void *priv, struct pb_slab *pslab);
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/* si_state.c */
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struct si_shader_selector;
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void si_init_atom(struct si_context *sctx, struct r600_atom *atom,
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struct r600_atom **list_elem,
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void (*emit_func)(struct si_context *ctx, struct r600_atom *state));
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void si_init_state_functions(struct si_context *sctx);
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void si_init_screen_state_functions(struct si_screen *sscreen);
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void
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si_make_buffer_descriptor(struct si_screen *screen, struct r600_resource *buf,
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enum pipe_format format,
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unsigned offset, unsigned size,
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uint32_t *state);
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void
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si_make_texture_descriptor(struct si_screen *screen,
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struct r600_texture *tex,
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bool sampler,
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enum pipe_texture_target target,
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enum pipe_format pipe_format,
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const unsigned char state_swizzle[4],
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unsigned first_level, unsigned last_level,
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unsigned first_layer, unsigned last_layer,
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unsigned width, unsigned height, unsigned depth,
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uint32_t *state,
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uint32_t *fmask_state);
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struct pipe_sampler_view *
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si_create_sampler_view_custom(struct pipe_context *ctx,
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struct pipe_resource *texture,
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const struct pipe_sampler_view *state,
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unsigned width0, unsigned height0,
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unsigned force_level);
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void si_update_fb_dirtiness_after_rendering(struct si_context *sctx);
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/* si_state_binning.c */
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void si_emit_dpbb_state(struct si_context *sctx, struct r600_atom *state);
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/* si_state_shaders.c */
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bool si_update_shaders(struct si_context *sctx);
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void si_init_shader_functions(struct si_context *sctx);
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bool si_init_shader_cache(struct si_screen *sscreen);
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void si_destroy_shader_cache(struct si_screen *sscreen);
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void si_get_active_slot_masks(const struct tgsi_shader_info *info,
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uint32_t *const_and_shader_buffers,
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uint64_t *samplers_and_images);
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void *si_get_blit_vs(struct si_context *sctx, enum blitter_attrib_type type,
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unsigned num_layers);
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/* si_state_draw.c */
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void si_init_ia_multi_vgt_param_table(struct si_context *sctx);
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void si_emit_cache_flush(struct si_context *sctx);
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void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo);
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void si_draw_rectangle(struct blitter_context *blitter,
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void *vertex_elements_cso,
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blitter_get_vs_func get_vs,
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int x1, int y1, int x2, int y2,
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float depth, unsigned num_instances,
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enum blitter_attrib_type type,
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const union blitter_attrib *attrib);
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void si_trace_emit(struct si_context *sctx);
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/* si_state_msaa.c */
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void si_init_msaa_functions(struct si_context *sctx);
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void si_emit_sample_locations(struct radeon_winsys_cs *cs, int nr_samples);
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/* si_state_streamout.c */
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void si_streamout_buffers_dirty(struct si_context *sctx);
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void si_emit_streamout_end(struct si_context *sctx);
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void si_update_prims_generated_query_state(struct si_context *sctx,
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unsigned type, int diff);
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void si_init_streamout_functions(struct si_context *sctx);
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static inline unsigned
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si_tile_mode_index(struct r600_texture *rtex, unsigned level, bool stencil)
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{
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if (stencil)
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return rtex->surface.u.legacy.stencil_tiling_index[level];
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else
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return rtex->surface.u.legacy.tiling_index[level];
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}
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static inline unsigned si_get_constbuf_slot(unsigned slot)
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{
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/* Constant buffers are in slots [16..31], ascending */
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return SI_NUM_SHADER_BUFFERS + slot;
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}
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static inline unsigned si_get_shaderbuf_slot(unsigned slot)
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{
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/* shader buffers are in slots [15..0], descending */
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return SI_NUM_SHADER_BUFFERS - 1 - slot;
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}
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static inline unsigned si_get_sampler_slot(unsigned slot)
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{
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/* samplers are in slots [8..39], ascending */
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return SI_NUM_IMAGES / 2 + slot;
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}
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static inline unsigned si_get_image_slot(unsigned slot)
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{
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/* images are in slots [15..0] (sampler slots [7..0]), descending */
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return SI_NUM_IMAGES - 1 - slot;
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}
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#endif
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