/*
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* Copyright 2013-2017 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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*/
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#include <libsync.h>
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#include "util/os_time.h"
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#include "util/u_memory.h"
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#include "util/u_queue.h"
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#include "util/u_upload_mgr.h"
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#include "si_pipe.h"
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#include "radeon/r600_cs.h"
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struct si_fine_fence {
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struct r600_resource *buf;
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unsigned offset;
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};
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struct si_multi_fence {
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struct pipe_reference reference;
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struct pipe_fence_handle *gfx;
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struct pipe_fence_handle *sdma;
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struct tc_unflushed_batch_token *tc_token;
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struct util_queue_fence ready;
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/* If the context wasn't flushed at fence creation, this is non-NULL. */
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struct {
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struct r600_common_context *ctx;
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unsigned ib_index;
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} gfx_unflushed;
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struct si_fine_fence fine;
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};
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static void si_add_fence_dependency(struct r600_common_context *rctx,
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struct pipe_fence_handle *fence)
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{
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struct radeon_winsys *ws = rctx->ws;
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if (rctx->dma.cs)
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ws->cs_add_fence_dependency(rctx->dma.cs, fence);
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ws->cs_add_fence_dependency(rctx->gfx.cs, fence);
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}
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static void si_fence_reference(struct pipe_screen *screen,
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struct pipe_fence_handle **dst,
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struct pipe_fence_handle *src)
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{
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struct radeon_winsys *ws = ((struct si_screen*)screen)->ws;
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struct si_multi_fence **rdst = (struct si_multi_fence **)dst;
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struct si_multi_fence *rsrc = (struct si_multi_fence *)src;
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if (pipe_reference(&(*rdst)->reference, &rsrc->reference)) {
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ws->fence_reference(&(*rdst)->gfx, NULL);
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ws->fence_reference(&(*rdst)->sdma, NULL);
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tc_unflushed_batch_token_reference(&(*rdst)->tc_token, NULL);
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r600_resource_reference(&(*rdst)->fine.buf, NULL);
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FREE(*rdst);
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}
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*rdst = rsrc;
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}
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static struct si_multi_fence *si_create_multi_fence()
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{
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struct si_multi_fence *fence = CALLOC_STRUCT(si_multi_fence);
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if (!fence)
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return NULL;
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pipe_reference_init(&fence->reference, 1);
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util_queue_fence_init(&fence->ready);
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return fence;
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}
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struct pipe_fence_handle *si_create_fence(struct pipe_context *ctx,
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struct tc_unflushed_batch_token *tc_token)
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{
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struct si_multi_fence *fence = si_create_multi_fence();
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if (!fence)
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return NULL;
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util_queue_fence_reset(&fence->ready);
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tc_unflushed_batch_token_reference(&fence->tc_token, tc_token);
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return (struct pipe_fence_handle *)fence;
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}
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static void si_fence_server_sync(struct pipe_context *ctx,
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struct pipe_fence_handle *fence)
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{
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struct r600_common_context *rctx = (struct r600_common_context *)ctx;
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struct si_multi_fence *rfence = (struct si_multi_fence *)fence;
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util_queue_fence_wait(&rfence->ready);
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/* Unflushed fences from the same context are no-ops. */
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if (rfence->gfx_unflushed.ctx &&
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rfence->gfx_unflushed.ctx == rctx)
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return;
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/* All unflushed commands will not start execution before
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* this fence dependency is signalled.
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*
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* Should we flush the context to allow more GPU parallelism?
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*/
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if (rfence->sdma)
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si_add_fence_dependency(rctx, rfence->sdma);
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if (rfence->gfx)
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si_add_fence_dependency(rctx, rfence->gfx);
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}
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static bool si_fine_fence_signaled(struct radeon_winsys *rws,
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const struct si_fine_fence *fine)
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{
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char *map = rws->buffer_map(fine->buf->buf, NULL, PIPE_TRANSFER_READ |
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PIPE_TRANSFER_UNSYNCHRONIZED);
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if (!map)
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return false;
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uint32_t *fence = (uint32_t*)(map + fine->offset);
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return *fence != 0;
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}
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static void si_fine_fence_set(struct si_context *ctx,
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struct si_fine_fence *fine,
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unsigned flags)
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{
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uint32_t *fence_ptr;
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assert(util_bitcount(flags & (PIPE_FLUSH_TOP_OF_PIPE | PIPE_FLUSH_BOTTOM_OF_PIPE)) == 1);
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/* Use uncached system memory for the fence. */
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u_upload_alloc(ctx->b.cached_gtt_allocator, 0, 4, 4,
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&fine->offset, (struct pipe_resource **)&fine->buf, (void **)&fence_ptr);
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if (!fine->buf)
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return;
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*fence_ptr = 0;
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uint64_t fence_va = fine->buf->gpu_address + fine->offset;
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radeon_add_to_buffer_list(&ctx->b, &ctx->b.gfx, fine->buf,
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RADEON_USAGE_WRITE, RADEON_PRIO_QUERY);
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if (flags & PIPE_FLUSH_TOP_OF_PIPE) {
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struct radeon_winsys_cs *cs = ctx->b.gfx.cs;
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radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
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radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
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S_370_WR_CONFIRM(1) |
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S_370_ENGINE_SEL(V_370_PFP));
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radeon_emit(cs, fence_va);
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radeon_emit(cs, fence_va >> 32);
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radeon_emit(cs, 0x80000000);
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} else if (flags & PIPE_FLUSH_BOTTOM_OF_PIPE) {
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si_gfx_write_event_eop(&ctx->b, V_028A90_BOTTOM_OF_PIPE_TS, 0,
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EOP_DATA_SEL_VALUE_32BIT,
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NULL, fence_va, 0x80000000,
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PIPE_QUERY_GPU_FINISHED);
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} else {
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assert(false);
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}
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}
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static boolean si_fence_finish(struct pipe_screen *screen,
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struct pipe_context *ctx,
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struct pipe_fence_handle *fence,
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uint64_t timeout)
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{
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struct radeon_winsys *rws = ((struct si_screen*)screen)->ws;
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struct si_multi_fence *rfence = (struct si_multi_fence *)fence;
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int64_t abs_timeout = os_time_get_absolute_timeout(timeout);
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if (!util_queue_fence_is_signalled(&rfence->ready)) {
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if (rfence->tc_token) {
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/* Ensure that si_flush_from_st will be called for
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* this fence, but only if we're in the API thread
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* where the context is current.
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*
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* Note that the batch containing the flush may already
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* be in flight in the driver thread, so the fence
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* may not be ready yet when this call returns.
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*/
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threaded_context_flush(ctx, rfence->tc_token,
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timeout == 0);
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}
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if (!timeout)
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return false;
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if (timeout == PIPE_TIMEOUT_INFINITE) {
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util_queue_fence_wait(&rfence->ready);
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} else {
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if (!util_queue_fence_wait_timeout(&rfence->ready, abs_timeout))
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return false;
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}
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if (timeout && timeout != PIPE_TIMEOUT_INFINITE) {
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int64_t time = os_time_get_nano();
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timeout = abs_timeout > time ? abs_timeout - time : 0;
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}
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}
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if (rfence->sdma) {
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if (!rws->fence_wait(rws, rfence->sdma, timeout))
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return false;
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/* Recompute the timeout after waiting. */
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if (timeout && timeout != PIPE_TIMEOUT_INFINITE) {
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int64_t time = os_time_get_nano();
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timeout = abs_timeout > time ? abs_timeout - time : 0;
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}
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}
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if (!rfence->gfx)
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return true;
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if (rfence->fine.buf &&
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si_fine_fence_signaled(rws, &rfence->fine)) {
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rws->fence_reference(&rfence->gfx, NULL);
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r600_resource_reference(&rfence->fine.buf, NULL);
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return true;
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}
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/* Flush the gfx IB if it hasn't been flushed yet. */
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if (ctx && rfence->gfx_unflushed.ctx) {
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struct si_context *sctx;
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sctx = (struct si_context *)threaded_context_unwrap_unsync(ctx);
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if (rfence->gfx_unflushed.ctx == &sctx->b &&
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rfence->gfx_unflushed.ib_index == sctx->b.num_gfx_cs_flushes) {
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/* Section 4.1.2 (Signaling) of the OpenGL 4.6 (Core profile)
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* spec says:
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*
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* "If the sync object being blocked upon will not be
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* signaled in finite time (for example, by an associated
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* fence command issued previously, but not yet flushed to
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* the graphics pipeline), then ClientWaitSync may hang
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* forever. To help prevent this behavior, if
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* ClientWaitSync is called and all of the following are
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* true:
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*
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* * the SYNC_FLUSH_COMMANDS_BIT bit is set in flags,
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* * sync is unsignaled when ClientWaitSync is called,
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* * and the calls to ClientWaitSync and FenceSync were
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* issued from the same context,
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*
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* then the GL will behave as if the equivalent of Flush
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* were inserted immediately after the creation of sync."
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*
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* This means we need to flush for such fences even when we're
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* not going to wait.
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*/
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threaded_context_unwrap_sync(ctx);
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sctx->b.gfx.flush(&sctx->b, timeout ? 0 : PIPE_FLUSH_ASYNC, NULL);
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rfence->gfx_unflushed.ctx = NULL;
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if (!timeout)
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return false;
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/* Recompute the timeout after all that. */
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if (timeout && timeout != PIPE_TIMEOUT_INFINITE) {
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int64_t time = os_time_get_nano();
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timeout = abs_timeout > time ? abs_timeout - time : 0;
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}
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}
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}
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if (rws->fence_wait(rws, rfence->gfx, timeout))
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return true;
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/* Re-check in case the GPU is slow or hangs, but the commands before
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* the fine-grained fence have completed. */
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if (rfence->fine.buf &&
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si_fine_fence_signaled(rws, &rfence->fine))
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return true;
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return false;
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}
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static void si_create_fence_fd(struct pipe_context *ctx,
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struct pipe_fence_handle **pfence, int fd)
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{
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struct si_screen *sscreen = (struct si_screen*)ctx->screen;
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struct radeon_winsys *ws = sscreen->ws;
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struct si_multi_fence *rfence;
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*pfence = NULL;
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if (!sscreen->info.has_fence_to_handle)
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return;
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rfence = si_create_multi_fence();
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if (!rfence)
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return;
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rfence->gfx = ws->fence_import_sync_file(ws, fd);
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if (!rfence->gfx) {
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FREE(rfence);
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return;
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}
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*pfence = (struct pipe_fence_handle*)rfence;
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}
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static int si_fence_get_fd(struct pipe_screen *screen,
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struct pipe_fence_handle *fence)
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{
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struct si_screen *sscreen = (struct si_screen*)screen;
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struct radeon_winsys *ws = sscreen->ws;
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struct si_multi_fence *rfence = (struct si_multi_fence *)fence;
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int gfx_fd = -1, sdma_fd = -1;
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if (!sscreen->info.has_fence_to_handle)
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return -1;
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util_queue_fence_wait(&rfence->ready);
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/* Deferred fences aren't supported. */
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assert(!rfence->gfx_unflushed.ctx);
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if (rfence->gfx_unflushed.ctx)
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return -1;
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if (rfence->sdma) {
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sdma_fd = ws->fence_export_sync_file(ws, rfence->sdma);
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if (sdma_fd == -1)
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return -1;
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}
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if (rfence->gfx) {
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gfx_fd = ws->fence_export_sync_file(ws, rfence->gfx);
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if (gfx_fd == -1) {
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if (sdma_fd != -1)
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close(sdma_fd);
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return -1;
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}
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}
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/* If we don't have FDs at this point, it means we don't have fences
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* either. */
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if (sdma_fd == -1 && gfx_fd == -1)
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return ws->export_signalled_sync_file(ws);
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if (sdma_fd == -1)
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return gfx_fd;
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if (gfx_fd == -1)
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return sdma_fd;
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/* Get a fence that will be a combination of both fences. */
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sync_accumulate("radeonsi", &gfx_fd, sdma_fd);
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close(sdma_fd);
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return gfx_fd;
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}
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static void si_flush_from_st(struct pipe_context *ctx,
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struct pipe_fence_handle **fence,
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unsigned flags)
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{
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struct pipe_screen *screen = ctx->screen;
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struct r600_common_context *rctx = (struct r600_common_context *)ctx;
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struct radeon_winsys *ws = rctx->ws;
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struct pipe_fence_handle *gfx_fence = NULL;
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struct pipe_fence_handle *sdma_fence = NULL;
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bool deferred_fence = false;
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struct si_fine_fence fine = {};
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unsigned rflags = PIPE_FLUSH_ASYNC;
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if (flags & PIPE_FLUSH_END_OF_FRAME)
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rflags |= PIPE_FLUSH_END_OF_FRAME;
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if (flags & (PIPE_FLUSH_TOP_OF_PIPE | PIPE_FLUSH_BOTTOM_OF_PIPE)) {
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assert(flags & PIPE_FLUSH_DEFERRED);
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assert(fence);
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si_fine_fence_set((struct si_context *)rctx, &fine, flags);
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}
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/* DMA IBs are preambles to gfx IBs, therefore must be flushed first. */
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if (rctx->dma.cs)
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rctx->dma.flush(rctx, rflags, fence ? &sdma_fence : NULL);
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if (!radeon_emitted(rctx->gfx.cs, rctx->initial_gfx_cs_size)) {
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if (fence)
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ws->fence_reference(&gfx_fence, rctx->last_gfx_fence);
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if (!(flags & PIPE_FLUSH_DEFERRED))
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ws->cs_sync_flush(rctx->gfx.cs);
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} else {
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/* Instead of flushing, create a deferred fence. Constraints:
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* - The state tracker must allow a deferred flush.
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* - The state tracker must request a fence.
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* - fence_get_fd is not allowed.
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* Thread safety in fence_finish must be ensured by the state tracker.
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*/
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if (flags & PIPE_FLUSH_DEFERRED &&
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!(flags & PIPE_FLUSH_FENCE_FD) &&
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fence) {
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gfx_fence = rctx->ws->cs_get_next_fence(rctx->gfx.cs);
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deferred_fence = true;
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} else {
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rctx->gfx.flush(rctx, rflags, fence ? &gfx_fence : NULL);
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}
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}
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/* Both engines can signal out of order, so we need to keep both fences. */
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if (fence) {
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struct si_multi_fence *multi_fence;
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if (flags & TC_FLUSH_ASYNC) {
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multi_fence = (struct si_multi_fence *)*fence;
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assert(multi_fence);
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} else {
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multi_fence = si_create_multi_fence();
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if (!multi_fence) {
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ws->fence_reference(&sdma_fence, NULL);
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ws->fence_reference(&gfx_fence, NULL);
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goto finish;
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}
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screen->fence_reference(screen, fence, NULL);
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*fence = (struct pipe_fence_handle*)multi_fence;
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}
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/* If both fences are NULL, fence_finish will always return true. */
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multi_fence->gfx = gfx_fence;
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multi_fence->sdma = sdma_fence;
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if (deferred_fence) {
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multi_fence->gfx_unflushed.ctx = rctx;
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multi_fence->gfx_unflushed.ib_index = rctx->num_gfx_cs_flushes;
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}
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multi_fence->fine = fine;
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fine.buf = NULL;
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if (flags & TC_FLUSH_ASYNC) {
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util_queue_fence_signal(&multi_fence->ready);
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tc_unflushed_batch_token_reference(&multi_fence->tc_token, NULL);
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}
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}
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assert(!fine.buf);
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finish:
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if (!(flags & PIPE_FLUSH_DEFERRED)) {
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if (rctx->dma.cs)
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ws->cs_sync_flush(rctx->dma.cs);
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ws->cs_sync_flush(rctx->gfx.cs);
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}
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}
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void si_init_fence_functions(struct si_context *ctx)
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{
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ctx->b.b.flush = si_flush_from_st;
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ctx->b.b.create_fence_fd = si_create_fence_fd;
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ctx->b.b.fence_server_sync = si_fence_server_sync;
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}
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void si_init_screen_fence_functions(struct si_screen *screen)
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{
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screen->b.fence_finish = si_fence_finish;
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screen->b.fence_reference = si_fence_reference;
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screen->b.fence_get_fd = si_fence_get_fd;
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}
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