/*
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* Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* on the rights to use, copy, modify, merge, publish, distribute, sub
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* license, and/or sell copies of the Software, and to permit persons to whom
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* the Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
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* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
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* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
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* USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include "sid.h"
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#include "si_pipe.h"
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#include "util/u_format.h"
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static void si_dma_copy_buffer(struct si_context *ctx,
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struct pipe_resource *dst,
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struct pipe_resource *src,
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uint64_t dst_offset,
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uint64_t src_offset,
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uint64_t size)
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{
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struct radeon_winsys_cs *cs = ctx->b.dma.cs;
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unsigned i, ncopy, count, max_size, sub_cmd, shift;
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struct r600_resource *rdst = (struct r600_resource*)dst;
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struct r600_resource *rsrc = (struct r600_resource*)src;
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/* Mark the buffer range of destination as valid (initialized),
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* so that transfer_map knows it should wait for the GPU when mapping
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* that range. */
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util_range_add(&rdst->valid_buffer_range, dst_offset,
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dst_offset + size);
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dst_offset += rdst->gpu_address;
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src_offset += rsrc->gpu_address;
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/* see whether we should use the dword-aligned or byte-aligned copy */
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if (!(dst_offset % 4) && !(src_offset % 4) && !(size % 4)) {
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sub_cmd = SI_DMA_COPY_DWORD_ALIGNED;
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shift = 2;
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max_size = SI_DMA_COPY_MAX_DWORD_ALIGNED_SIZE;
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} else {
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sub_cmd = SI_DMA_COPY_BYTE_ALIGNED;
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shift = 0;
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max_size = SI_DMA_COPY_MAX_BYTE_ALIGNED_SIZE;
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}
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ncopy = DIV_ROUND_UP(size, max_size);
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si_need_dma_space(&ctx->b, ncopy * 5, rdst, rsrc);
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for (i = 0; i < ncopy; i++) {
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count = MIN2(size, max_size);
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radeon_emit(cs, SI_DMA_PACKET(SI_DMA_PACKET_COPY, sub_cmd,
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count >> shift));
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radeon_emit(cs, dst_offset);
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radeon_emit(cs, src_offset);
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radeon_emit(cs, (dst_offset >> 32UL) & 0xff);
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radeon_emit(cs, (src_offset >> 32UL) & 0xff);
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dst_offset += count;
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src_offset += count;
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size -= count;
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}
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}
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static void si_dma_clear_buffer(struct pipe_context *ctx,
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struct pipe_resource *dst,
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uint64_t offset,
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uint64_t size,
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unsigned clear_value)
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{
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struct si_context *sctx = (struct si_context *)ctx;
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struct radeon_winsys_cs *cs = sctx->b.dma.cs;
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unsigned i, ncopy, csize;
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struct r600_resource *rdst = r600_resource(dst);
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if (!cs || offset % 4 != 0 || size % 4 != 0 ||
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dst->flags & PIPE_RESOURCE_FLAG_SPARSE) {
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ctx->clear_buffer(ctx, dst, offset, size, &clear_value, 4);
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return;
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}
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/* Mark the buffer range of destination as valid (initialized),
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* so that transfer_map knows it should wait for the GPU when mapping
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* that range. */
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util_range_add(&rdst->valid_buffer_range, offset, offset + size);
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offset += rdst->gpu_address;
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/* the same maximum size as for copying */
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ncopy = DIV_ROUND_UP(size, SI_DMA_COPY_MAX_DWORD_ALIGNED_SIZE);
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si_need_dma_space(&sctx->b, ncopy * 4, rdst, NULL);
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for (i = 0; i < ncopy; i++) {
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csize = MIN2(size, SI_DMA_COPY_MAX_DWORD_ALIGNED_SIZE);
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radeon_emit(cs, SI_DMA_PACKET(SI_DMA_PACKET_CONSTANT_FILL, 0,
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csize / 4));
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radeon_emit(cs, offset);
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radeon_emit(cs, clear_value);
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radeon_emit(cs, (offset >> 32) << 16);
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offset += csize;
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size -= csize;
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}
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}
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static void si_dma_copy_tile(struct si_context *ctx,
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struct pipe_resource *dst,
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unsigned dst_level,
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unsigned dst_x,
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unsigned dst_y,
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unsigned dst_z,
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struct pipe_resource *src,
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unsigned src_level,
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unsigned src_x,
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unsigned src_y,
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unsigned src_z,
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unsigned copy_height,
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unsigned pitch,
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unsigned bpp)
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{
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struct radeon_winsys_cs *cs = ctx->b.dma.cs;
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struct r600_texture *rsrc = (struct r600_texture*)src;
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struct r600_texture *rdst = (struct r600_texture*)dst;
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unsigned dst_mode = rdst->surface.u.legacy.level[dst_level].mode;
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bool detile = dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED;
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struct r600_texture *rlinear = detile ? rdst : rsrc;
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struct r600_texture *rtiled = detile ? rsrc : rdst;
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unsigned linear_lvl = detile ? dst_level : src_level;
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unsigned tiled_lvl = detile ? src_level : dst_level;
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struct radeon_info *info = &ctx->screen->info;
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unsigned index = rtiled->surface.u.legacy.tiling_index[tiled_lvl];
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unsigned tile_mode = info->si_tile_mode_array[index];
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unsigned array_mode, lbpp, pitch_tile_max, slice_tile_max, size;
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unsigned ncopy, height, cheight, i;
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unsigned linear_x, linear_y, linear_z, tiled_x, tiled_y, tiled_z;
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unsigned sub_cmd, bank_h, bank_w, mt_aspect, nbanks, tile_split, mt;
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uint64_t base, addr;
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unsigned pipe_config;
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assert(dst_mode != rsrc->surface.u.legacy.level[src_level].mode);
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sub_cmd = SI_DMA_COPY_TILED;
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lbpp = util_logbase2(bpp);
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pitch_tile_max = ((pitch / bpp) / 8) - 1;
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linear_x = detile ? dst_x : src_x;
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linear_y = detile ? dst_y : src_y;
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linear_z = detile ? dst_z : src_z;
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tiled_x = detile ? src_x : dst_x;
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tiled_y = detile ? src_y : dst_y;
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tiled_z = detile ? src_z : dst_z;
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assert(!util_format_is_depth_and_stencil(rtiled->resource.b.b.format));
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array_mode = G_009910_ARRAY_MODE(tile_mode);
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slice_tile_max = (rtiled->surface.u.legacy.level[tiled_lvl].nblk_x *
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rtiled->surface.u.legacy.level[tiled_lvl].nblk_y) / (8*8) - 1;
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/* linear height must be the same as the slice tile max height, it's ok even
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* if the linear destination/source have smaller heigh as the size of the
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* dma packet will be using the copy_height which is always smaller or equal
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* to the linear height
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*/
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height = rtiled->surface.u.legacy.level[tiled_lvl].nblk_y;
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base = rtiled->surface.u.legacy.level[tiled_lvl].offset;
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addr = rlinear->surface.u.legacy.level[linear_lvl].offset;
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addr += (uint64_t)rlinear->surface.u.legacy.level[linear_lvl].slice_size_dw * 4 * linear_z;
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addr += linear_y * pitch + linear_x * bpp;
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bank_h = G_009910_BANK_HEIGHT(tile_mode);
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bank_w = G_009910_BANK_WIDTH(tile_mode);
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mt_aspect = G_009910_MACRO_TILE_ASPECT(tile_mode);
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/* Non-depth modes don't have TILE_SPLIT set. */
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tile_split = util_logbase2(rtiled->surface.u.legacy.tile_split >> 6);
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nbanks = G_009910_NUM_BANKS(tile_mode);
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base += rtiled->resource.gpu_address;
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addr += rlinear->resource.gpu_address;
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pipe_config = G_009910_PIPE_CONFIG(tile_mode);
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mt = G_009910_MICRO_TILE_MODE(tile_mode);
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size = copy_height * pitch;
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ncopy = DIV_ROUND_UP(size, SI_DMA_COPY_MAX_DWORD_ALIGNED_SIZE);
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si_need_dma_space(&ctx->b, ncopy * 9, &rdst->resource, &rsrc->resource);
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for (i = 0; i < ncopy; i++) {
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cheight = copy_height;
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if (cheight * pitch > SI_DMA_COPY_MAX_DWORD_ALIGNED_SIZE) {
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cheight = SI_DMA_COPY_MAX_DWORD_ALIGNED_SIZE / pitch;
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}
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size = cheight * pitch;
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radeon_emit(cs, SI_DMA_PACKET(SI_DMA_PACKET_COPY, sub_cmd, size / 4));
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radeon_emit(cs, base >> 8);
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radeon_emit(cs, (detile << 31) | (array_mode << 27) |
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(lbpp << 24) | (bank_h << 21) |
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(bank_w << 18) | (mt_aspect << 16));
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radeon_emit(cs, (pitch_tile_max << 0) | ((height - 1) << 16));
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radeon_emit(cs, (slice_tile_max << 0) | (pipe_config << 26));
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radeon_emit(cs, (tiled_x << 0) | (tiled_z << 18));
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radeon_emit(cs, (tiled_y << 0) | (tile_split << 21) | (nbanks << 25) | (mt << 27));
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radeon_emit(cs, addr & 0xfffffffc);
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radeon_emit(cs, (addr >> 32UL) & 0xff);
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copy_height -= cheight;
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addr += cheight * pitch;
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tiled_y += cheight;
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}
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}
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static void si_dma_copy(struct pipe_context *ctx,
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struct pipe_resource *dst,
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unsigned dst_level,
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unsigned dstx, unsigned dsty, unsigned dstz,
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struct pipe_resource *src,
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unsigned src_level,
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const struct pipe_box *src_box)
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{
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struct si_context *sctx = (struct si_context *)ctx;
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struct r600_texture *rsrc = (struct r600_texture*)src;
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struct r600_texture *rdst = (struct r600_texture*)dst;
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unsigned dst_pitch, src_pitch, bpp, dst_mode, src_mode;
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unsigned src_w, dst_w;
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unsigned src_x, src_y;
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unsigned dst_x = dstx, dst_y = dsty, dst_z = dstz;
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if (sctx->b.dma.cs == NULL ||
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src->flags & PIPE_RESOURCE_FLAG_SPARSE ||
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dst->flags & PIPE_RESOURCE_FLAG_SPARSE) {
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goto fallback;
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}
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if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) {
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si_dma_copy_buffer(sctx, dst, src, dst_x, src_box->x, src_box->width);
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return;
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}
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/* XXX: Using the asynchronous DMA engine for multi-dimensional
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* operations seems to cause random GPU lockups for various people.
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* While the root cause for this might need to be fixed in the kernel,
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* let's disable it for now.
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*
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* Before re-enabling this, please make sure you can hit all newly
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* enabled paths in your testing, preferably with both piglit and real
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* world apps, and get in touch with people on the bug reports below
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* for stability testing.
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*
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* https://bugs.freedesktop.org/show_bug.cgi?id=85647
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* https://bugs.freedesktop.org/show_bug.cgi?id=83500
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*/
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goto fallback;
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if (src_box->depth > 1 ||
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!si_prepare_for_dma_blit(&sctx->b, rdst, dst_level, dstx, dsty,
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dstz, rsrc, src_level, src_box))
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goto fallback;
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src_x = util_format_get_nblocksx(src->format, src_box->x);
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dst_x = util_format_get_nblocksx(src->format, dst_x);
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src_y = util_format_get_nblocksy(src->format, src_box->y);
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dst_y = util_format_get_nblocksy(src->format, dst_y);
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bpp = rdst->surface.bpe;
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dst_pitch = rdst->surface.u.legacy.level[dst_level].nblk_x * rdst->surface.bpe;
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src_pitch = rsrc->surface.u.legacy.level[src_level].nblk_x * rsrc->surface.bpe;
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src_w = u_minify(rsrc->resource.b.b.width0, src_level);
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dst_w = u_minify(rdst->resource.b.b.width0, dst_level);
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dst_mode = rdst->surface.u.legacy.level[dst_level].mode;
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src_mode = rsrc->surface.u.legacy.level[src_level].mode;
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if (src_pitch != dst_pitch || src_box->x || dst_x || src_w != dst_w ||
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src_box->width != src_w ||
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src_box->height != u_minify(rsrc->resource.b.b.height0, src_level) ||
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src_box->height != u_minify(rdst->resource.b.b.height0, dst_level) ||
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rsrc->surface.u.legacy.level[src_level].nblk_y !=
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rdst->surface.u.legacy.level[dst_level].nblk_y) {
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/* FIXME si can do partial blit */
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goto fallback;
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}
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/* the x test here are currently useless (because we don't support partial blit)
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* but keep them around so we don't forget about those
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*/
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if ((src_pitch % 8) || (src_box->x % 8) || (dst_x % 8) ||
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(src_box->y % 8) || (dst_y % 8) || (src_box->height % 8)) {
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goto fallback;
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}
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if (src_mode == dst_mode) {
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uint64_t dst_offset, src_offset;
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/* simple dma blit would do NOTE code here assume :
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* src_box.x/y == 0
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* dst_x/y == 0
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* dst_pitch == src_pitch
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*/
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src_offset= rsrc->surface.u.legacy.level[src_level].offset;
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src_offset += (uint64_t)rsrc->surface.u.legacy.level[src_level].slice_size_dw * 4 * src_box->z;
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src_offset += src_y * src_pitch + src_x * bpp;
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dst_offset = rdst->surface.u.legacy.level[dst_level].offset;
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dst_offset += (uint64_t)rdst->surface.u.legacy.level[dst_level].slice_size_dw * 4 * dst_z;
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dst_offset += dst_y * dst_pitch + dst_x * bpp;
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si_dma_copy_buffer(sctx, dst, src, dst_offset, src_offset,
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(uint64_t)rsrc->surface.u.legacy.level[src_level].slice_size_dw * 4);
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} else {
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si_dma_copy_tile(sctx, dst, dst_level, dst_x, dst_y, dst_z,
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src, src_level, src_x, src_y, src_box->z,
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src_box->height / rsrc->surface.blk_h,
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dst_pitch, bpp);
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}
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return;
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fallback:
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si_resource_copy_region(ctx, dst, dst_level, dstx, dsty, dstz,
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src, src_level, src_box);
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}
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void si_init_dma_functions(struct si_context *sctx)
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{
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sctx->b.dma_copy = si_dma_copy;
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sctx->b.dma_clear_buffer = si_dma_clear_buffer;
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}
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