/*
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* Copyright 2017 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* on the rights to use, copy, modify, merge, publish, distribute, sub
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* license, and/or sell copies of the Software, and to permit persons to whom
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* the Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
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* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
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* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
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* USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include "si_pipe.h"
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#include "sid.h"
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#include "util/u_format.h"
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#include "util/u_pack_color.h"
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#include "util/u_surface.h"
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enum {
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SI_CLEAR = SI_SAVE_FRAGMENT_STATE,
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SI_CLEAR_SURFACE = SI_SAVE_FRAMEBUFFER | SI_SAVE_FRAGMENT_STATE,
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};
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static void si_alloc_separate_cmask(struct si_screen *sscreen,
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struct r600_texture *rtex)
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{
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if (rtex->cmask_buffer)
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return;
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assert(rtex->cmask.size == 0);
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si_texture_get_cmask_info(sscreen, rtex, &rtex->cmask);
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if (!rtex->cmask.size)
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return;
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rtex->cmask_buffer = (struct r600_resource *)
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si_aligned_buffer_create(&sscreen->b,
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R600_RESOURCE_FLAG_UNMAPPABLE,
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PIPE_USAGE_DEFAULT,
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rtex->cmask.size,
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rtex->cmask.alignment);
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if (rtex->cmask_buffer == NULL) {
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rtex->cmask.size = 0;
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return;
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}
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/* update colorbuffer state bits */
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rtex->cmask.base_address_reg = rtex->cmask_buffer->gpu_address >> 8;
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rtex->cb_color_info |= S_028C70_FAST_CLEAR(1);
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p_atomic_inc(&sscreen->compressed_colortex_counter);
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}
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static void si_set_clear_color(struct r600_texture *rtex,
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enum pipe_format surface_format,
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const union pipe_color_union *color)
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{
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union util_color uc;
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memset(&uc, 0, sizeof(uc));
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if (rtex->surface.bpe == 16) {
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/* DCC fast clear only:
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* CLEAR_WORD0 = R = G = B
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* CLEAR_WORD1 = A
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*/
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assert(color->ui[0] == color->ui[1] &&
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color->ui[0] == color->ui[2]);
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uc.ui[0] = color->ui[0];
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uc.ui[1] = color->ui[3];
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} else if (util_format_is_pure_uint(surface_format)) {
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util_format_write_4ui(surface_format, color->ui, 0, &uc, 0, 0, 0, 1, 1);
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} else if (util_format_is_pure_sint(surface_format)) {
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util_format_write_4i(surface_format, color->i, 0, &uc, 0, 0, 0, 1, 1);
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} else {
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util_pack_color(color->f, surface_format, &uc);
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}
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memcpy(rtex->color_clear_value, &uc, 2 * sizeof(uint32_t));
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}
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static bool vi_get_fast_clear_parameters(enum pipe_format surface_format,
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const union pipe_color_union *color,
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uint32_t* reset_value,
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bool* clear_words_needed)
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{
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bool values[4] = {};
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int i;
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bool main_value = false;
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bool extra_value = false;
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int extra_channel;
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/* This is needed to get the correct DCC clear value for luminance formats.
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* 1) Get the linear format (because the next step can't handle L8_SRGB).
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* 2) Convert luminance to red. (the real hw format for luminance)
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*/
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surface_format = util_format_linear(surface_format);
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surface_format = util_format_luminance_to_red(surface_format);
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const struct util_format_description *desc = util_format_description(surface_format);
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if (desc->block.bits == 128 &&
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(color->ui[0] != color->ui[1] ||
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color->ui[0] != color->ui[2]))
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return false;
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*clear_words_needed = true;
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*reset_value = 0x20202020U;
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/* If we want to clear without needing a fast clear eliminate step, we
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* can set each channel to 0 or 1 (or 0/max for integer formats). We
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* have two sets of flags, one for the last or first channel(extra) and
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* one for the other channels(main).
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*/
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if (surface_format == PIPE_FORMAT_R11G11B10_FLOAT ||
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surface_format == PIPE_FORMAT_B5G6R5_UNORM ||
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surface_format == PIPE_FORMAT_B5G6R5_SRGB ||
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util_format_is_alpha(surface_format)) {
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extra_channel = -1;
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} else if (desc->layout == UTIL_FORMAT_LAYOUT_PLAIN) {
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if (si_translate_colorswap(surface_format, false) <= 1)
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extra_channel = desc->nr_channels - 1;
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else
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extra_channel = 0;
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} else
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return true;
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for (i = 0; i < 4; ++i) {
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int index = desc->swizzle[i] - PIPE_SWIZZLE_X;
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if (desc->swizzle[i] < PIPE_SWIZZLE_X ||
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desc->swizzle[i] > PIPE_SWIZZLE_W)
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continue;
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if (desc->channel[i].pure_integer &&
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desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
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/* Use the maximum value for clamping the clear color. */
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int max = u_bit_consecutive(0, desc->channel[i].size - 1);
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values[i] = color->i[i] != 0;
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if (color->i[i] != 0 && MIN2(color->i[i], max) != max)
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return true;
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} else if (desc->channel[i].pure_integer &&
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desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
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/* Use the maximum value for clamping the clear color. */
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unsigned max = u_bit_consecutive(0, desc->channel[i].size);
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values[i] = color->ui[i] != 0U;
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if (color->ui[i] != 0U && MIN2(color->ui[i], max) != max)
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return true;
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} else {
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values[i] = color->f[i] != 0.0F;
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if (color->f[i] != 0.0F && color->f[i] != 1.0F)
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return true;
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}
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if (index == extra_channel)
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extra_value = values[i];
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else
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main_value = values[i];
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}
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for (int i = 0; i < 4; ++i)
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if (values[i] != main_value &&
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desc->swizzle[i] - PIPE_SWIZZLE_X != extra_channel &&
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desc->swizzle[i] >= PIPE_SWIZZLE_X &&
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desc->swizzle[i] <= PIPE_SWIZZLE_W)
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return true;
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*clear_words_needed = false;
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if (main_value)
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*reset_value |= 0x80808080U;
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if (extra_value)
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*reset_value |= 0x40404040U;
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return true;
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}
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void vi_dcc_clear_level(struct si_context *sctx,
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struct r600_texture *rtex,
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unsigned level, unsigned clear_value)
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{
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struct pipe_resource *dcc_buffer;
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uint64_t dcc_offset, clear_size;
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assert(vi_dcc_enabled(rtex, level));
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if (rtex->dcc_separate_buffer) {
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dcc_buffer = &rtex->dcc_separate_buffer->b.b;
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dcc_offset = 0;
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} else {
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dcc_buffer = &rtex->resource.b.b;
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dcc_offset = rtex->dcc_offset;
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}
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if (sctx->b.chip_class >= GFX9) {
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/* Mipmap level clears aren't implemented. */
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assert(rtex->resource.b.b.last_level == 0);
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/* MSAA needs a different clear size. */
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assert(rtex->resource.b.b.nr_samples <= 1);
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clear_size = rtex->surface.dcc_size;
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} else {
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unsigned num_layers = util_num_layers(&rtex->resource.b.b, level);
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/* If this is 0, fast clear isn't possible. (can occur with MSAA) */
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assert(rtex->surface.u.legacy.level[level].dcc_fast_clear_size);
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/* Layered MSAA DCC fast clears need to clear dcc_fast_clear_size
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* bytes for each layer. This is not currently implemented, and
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* therefore MSAA DCC isn't even enabled with multiple layers.
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*/
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assert(rtex->resource.b.b.nr_samples <= 1 || num_layers == 1);
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dcc_offset += rtex->surface.u.legacy.level[level].dcc_offset;
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clear_size = rtex->surface.u.legacy.level[level].dcc_fast_clear_size *
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num_layers;
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}
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si_clear_buffer(&sctx->b.b, dcc_buffer, dcc_offset, clear_size,
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clear_value, R600_COHERENCY_CB_META);
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}
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/* Set the same micro tile mode as the destination of the last MSAA resolve.
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* This allows hitting the MSAA resolve fast path, which requires that both
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* src and dst micro tile modes match.
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*/
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static void si_set_optimal_micro_tile_mode(struct si_screen *sscreen,
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struct r600_texture *rtex)
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{
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if (rtex->resource.b.is_shared ||
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rtex->resource.b.b.nr_samples <= 1 ||
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rtex->surface.micro_tile_mode == rtex->last_msaa_resolve_target_micro_mode)
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return;
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assert(sscreen->info.chip_class >= GFX9 ||
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rtex->surface.u.legacy.level[0].mode == RADEON_SURF_MODE_2D);
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assert(rtex->resource.b.b.last_level == 0);
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if (sscreen->info.chip_class >= GFX9) {
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/* 4K or larger tiles only. 0 is linear. 1-3 are 256B tiles. */
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assert(rtex->surface.u.gfx9.surf.swizzle_mode >= 4);
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/* If you do swizzle_mode % 4, you'll get:
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* 0 = Depth
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* 1 = Standard,
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* 2 = Displayable
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* 3 = Rotated
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*
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* Depth-sample order isn't allowed:
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*/
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assert(rtex->surface.u.gfx9.surf.swizzle_mode % 4 != 0);
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switch (rtex->last_msaa_resolve_target_micro_mode) {
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case RADEON_MICRO_MODE_DISPLAY:
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rtex->surface.u.gfx9.surf.swizzle_mode &= ~0x3;
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rtex->surface.u.gfx9.surf.swizzle_mode += 2; /* D */
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break;
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case RADEON_MICRO_MODE_THIN:
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rtex->surface.u.gfx9.surf.swizzle_mode &= ~0x3;
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rtex->surface.u.gfx9.surf.swizzle_mode += 1; /* S */
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break;
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case RADEON_MICRO_MODE_ROTATED:
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rtex->surface.u.gfx9.surf.swizzle_mode &= ~0x3;
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rtex->surface.u.gfx9.surf.swizzle_mode += 3; /* R */
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break;
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default: /* depth */
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assert(!"unexpected micro mode");
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return;
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}
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} else if (sscreen->info.chip_class >= CIK) {
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/* These magic numbers were copied from addrlib. It doesn't use
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* any definitions for them either. They are all 2D_TILED_THIN1
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* modes with different bpp and micro tile mode.
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*/
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switch (rtex->last_msaa_resolve_target_micro_mode) {
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case RADEON_MICRO_MODE_DISPLAY:
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rtex->surface.u.legacy.tiling_index[0] = 10;
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break;
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case RADEON_MICRO_MODE_THIN:
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rtex->surface.u.legacy.tiling_index[0] = 14;
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break;
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case RADEON_MICRO_MODE_ROTATED:
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rtex->surface.u.legacy.tiling_index[0] = 28;
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break;
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default: /* depth, thick */
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assert(!"unexpected micro mode");
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return;
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}
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} else { /* SI */
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switch (rtex->last_msaa_resolve_target_micro_mode) {
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case RADEON_MICRO_MODE_DISPLAY:
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switch (rtex->surface.bpe) {
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case 1:
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rtex->surface.u.legacy.tiling_index[0] = 10;
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break;
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case 2:
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rtex->surface.u.legacy.tiling_index[0] = 11;
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break;
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default: /* 4, 8 */
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rtex->surface.u.legacy.tiling_index[0] = 12;
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break;
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}
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break;
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case RADEON_MICRO_MODE_THIN:
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switch (rtex->surface.bpe) {
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case 1:
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rtex->surface.u.legacy.tiling_index[0] = 14;
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break;
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case 2:
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rtex->surface.u.legacy.tiling_index[0] = 15;
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break;
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case 4:
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rtex->surface.u.legacy.tiling_index[0] = 16;
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break;
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default: /* 8, 16 */
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rtex->surface.u.legacy.tiling_index[0] = 17;
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break;
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}
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break;
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default: /* depth, thick */
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assert(!"unexpected micro mode");
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return;
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}
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}
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rtex->surface.micro_tile_mode = rtex->last_msaa_resolve_target_micro_mode;
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p_atomic_inc(&sscreen->dirty_tex_counter);
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}
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static void si_do_fast_color_clear(struct si_context *sctx,
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unsigned *buffers,
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const union pipe_color_union *color)
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{
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struct pipe_framebuffer_state *fb = &sctx->framebuffer.state;
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int i;
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/* This function is broken in BE, so just disable this path for now */
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#ifdef PIPE_ARCH_BIG_ENDIAN
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return;
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#endif
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if (sctx->b.render_cond)
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return;
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for (i = 0; i < fb->nr_cbufs; i++) {
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struct r600_texture *tex;
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unsigned clear_bit = PIPE_CLEAR_COLOR0 << i;
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if (!fb->cbufs[i])
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continue;
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/* if this colorbuffer is not being cleared */
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if (!(*buffers & clear_bit))
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continue;
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unsigned level = fb->cbufs[i]->u.tex.level;
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tex = (struct r600_texture *)fb->cbufs[i]->texture;
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/* the clear is allowed if all layers are bound */
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if (fb->cbufs[i]->u.tex.first_layer != 0 ||
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fb->cbufs[i]->u.tex.last_layer != util_max_layer(&tex->resource.b.b, 0)) {
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continue;
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}
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/* cannot clear mipmapped textures */
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if (fb->cbufs[i]->texture->last_level != 0) {
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continue;
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}
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/* only supported on tiled surfaces */
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if (tex->surface.is_linear) {
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continue;
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}
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/* shared textures can't use fast clear without an explicit flush,
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* because there is no way to communicate the clear color among
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* all clients
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*/
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if (tex->resource.b.is_shared &&
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!(tex->resource.external_usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH))
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continue;
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/* fast color clear with 1D tiling doesn't work on old kernels and CIK */
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if (sctx->b.chip_class == CIK &&
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tex->surface.u.legacy.level[0].mode == RADEON_SURF_MODE_1D &&
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sctx->screen->info.drm_major == 2 &&
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sctx->screen->info.drm_minor < 38) {
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continue;
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}
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/* Fast clear is the most appropriate place to enable DCC for
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* displayable surfaces.
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*/
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if (sctx->b.chip_class >= VI &&
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!(sctx->screen->debug_flags & DBG(NO_DCC_FB))) {
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vi_separate_dcc_try_enable(&sctx->b, tex);
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/* RB+ isn't supported with a CMASK clear only on Stoney,
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* so all clears are considered to be hypothetically slow
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* clears, which is weighed when determining whether to
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* enable separate DCC.
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*/
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if (tex->dcc_gather_statistics &&
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sctx->b.family == CHIP_STONEY)
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tex->num_slow_clears++;
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}
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bool need_decompress_pass = false;
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/* Use a slow clear for small surfaces where the cost of
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* the eliminate pass can be higher than the benefit of fast
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* clear. The closed driver does this, but the numbers may differ.
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*
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* This helps on both dGPUs and APUs, even small APUs like Mullins.
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*/
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bool too_small = tex->resource.b.b.nr_samples <= 1 &&
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tex->resource.b.b.width0 *
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tex->resource.b.b.height0 <= 512 * 512;
|
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/* Try to clear DCC first, otherwise try CMASK. */
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if (vi_dcc_enabled(tex, 0)) {
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uint32_t reset_value;
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bool clear_words_needed;
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if (sctx->screen->debug_flags & DBG(NO_DCC_CLEAR))
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continue;
|
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/* This can only occur with MSAA. */
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if (sctx->b.chip_class == VI &&
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!tex->surface.u.legacy.level[level].dcc_fast_clear_size)
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continue;
|
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if (!vi_get_fast_clear_parameters(fb->cbufs[i]->format,
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color, &reset_value,
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&clear_words_needed))
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continue;
|
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if (clear_words_needed && too_small)
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continue;
|
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/* DCC fast clear with MSAA should clear CMASK to 0xC. */
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if (tex->resource.b.b.nr_samples >= 2 && tex->cmask.size) {
|
/* TODO: This doesn't work with MSAA. */
|
if (clear_words_needed)
|
continue;
|
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si_clear_buffer(&sctx->b.b, &tex->cmask_buffer->b.b,
|
tex->cmask.offset, tex->cmask.size,
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0xCCCCCCCC, R600_COHERENCY_CB_META);
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need_decompress_pass = true;
|
}
|
|
vi_dcc_clear_level(sctx, tex, 0, reset_value);
|
|
if (clear_words_needed)
|
need_decompress_pass = true;
|
|
tex->separate_dcc_dirty = true;
|
} else {
|
if (too_small)
|
continue;
|
|
/* 128-bit formats are unusupported */
|
if (tex->surface.bpe > 8) {
|
continue;
|
}
|
|
/* RB+ doesn't work with CMASK fast clear on Stoney. */
|
if (sctx->b.family == CHIP_STONEY)
|
continue;
|
|
/* ensure CMASK is enabled */
|
si_alloc_separate_cmask(sctx->screen, tex);
|
if (tex->cmask.size == 0) {
|
continue;
|
}
|
|
/* Do the fast clear. */
|
si_clear_buffer(&sctx->b.b, &tex->cmask_buffer->b.b,
|
tex->cmask.offset, tex->cmask.size, 0,
|
R600_COHERENCY_CB_META);
|
need_decompress_pass = true;
|
}
|
|
if (need_decompress_pass &&
|
!(tex->dirty_level_mask & (1 << level))) {
|
tex->dirty_level_mask |= 1 << level;
|
p_atomic_inc(&sctx->screen->compressed_colortex_counter);
|
}
|
|
/* We can change the micro tile mode before a full clear. */
|
si_set_optimal_micro_tile_mode(sctx->screen, tex);
|
|
si_set_clear_color(tex, fb->cbufs[i]->format, color);
|
|
sctx->framebuffer.dirty_cbufs |= 1 << i;
|
si_mark_atom_dirty(sctx, &sctx->framebuffer.atom);
|
*buffers &= ~clear_bit;
|
}
|
}
|
|
static void si_clear(struct pipe_context *ctx, unsigned buffers,
|
const union pipe_color_union *color,
|
double depth, unsigned stencil)
|
{
|
struct si_context *sctx = (struct si_context *)ctx;
|
struct pipe_framebuffer_state *fb = &sctx->framebuffer.state;
|
struct pipe_surface *zsbuf = fb->zsbuf;
|
struct r600_texture *zstex =
|
zsbuf ? (struct r600_texture*)zsbuf->texture : NULL;
|
|
if (buffers & PIPE_CLEAR_COLOR) {
|
si_do_fast_color_clear(sctx, &buffers, color);
|
if (!buffers)
|
return; /* all buffers have been fast cleared */
|
}
|
|
if (buffers & PIPE_CLEAR_COLOR) {
|
int i;
|
|
/* These buffers cannot use fast clear, make sure to disable expansion. */
|
for (i = 0; i < fb->nr_cbufs; i++) {
|
struct r600_texture *tex;
|
|
/* If not clearing this buffer, skip. */
|
if (!(buffers & (PIPE_CLEAR_COLOR0 << i)))
|
continue;
|
|
if (!fb->cbufs[i])
|
continue;
|
|
tex = (struct r600_texture *)fb->cbufs[i]->texture;
|
if (tex->fmask.size == 0)
|
tex->dirty_level_mask &= ~(1 << fb->cbufs[i]->u.tex.level);
|
}
|
}
|
|
if (zstex &&
|
si_htile_enabled(zstex, zsbuf->u.tex.level) &&
|
zsbuf->u.tex.first_layer == 0 &&
|
zsbuf->u.tex.last_layer == util_max_layer(&zstex->resource.b.b, 0)) {
|
/* TC-compatible HTILE only supports depth clears to 0 or 1. */
|
if (buffers & PIPE_CLEAR_DEPTH &&
|
(!zstex->tc_compatible_htile ||
|
depth == 0 || depth == 1)) {
|
/* Need to disable EXPCLEAR temporarily if clearing
|
* to a new value. */
|
if (!zstex->depth_cleared || zstex->depth_clear_value != depth) {
|
sctx->db_depth_disable_expclear = true;
|
}
|
|
zstex->depth_clear_value = depth;
|
sctx->framebuffer.dirty_zsbuf = true;
|
si_mark_atom_dirty(sctx, &sctx->framebuffer.atom); /* updates DB_DEPTH_CLEAR */
|
sctx->db_depth_clear = true;
|
si_mark_atom_dirty(sctx, &sctx->db_render_state);
|
}
|
|
/* TC-compatible HTILE only supports stencil clears to 0. */
|
if (buffers & PIPE_CLEAR_STENCIL &&
|
(!zstex->tc_compatible_htile || stencil == 0)) {
|
stencil &= 0xff;
|
|
/* Need to disable EXPCLEAR temporarily if clearing
|
* to a new value. */
|
if (!zstex->stencil_cleared || zstex->stencil_clear_value != stencil) {
|
sctx->db_stencil_disable_expclear = true;
|
}
|
|
zstex->stencil_clear_value = stencil;
|
sctx->framebuffer.dirty_zsbuf = true;
|
si_mark_atom_dirty(sctx, &sctx->framebuffer.atom); /* updates DB_STENCIL_CLEAR */
|
sctx->db_stencil_clear = true;
|
si_mark_atom_dirty(sctx, &sctx->db_render_state);
|
}
|
|
/* TODO: Find out what's wrong here. Fast depth clear leads to
|
* corruption in ARK: Survival Evolved, but that may just be
|
* a coincidence and the root cause is elsewhere.
|
*
|
* The corruption can be fixed by putting the DB flush before
|
* or after the depth clear. (surprisingly)
|
*
|
* https://bugs.freedesktop.org/show_bug.cgi?id=102955 (apitrace)
|
*
|
* This hack decreases back-to-back ClearDepth performance.
|
*/
|
if (sctx->screen->clear_db_cache_before_clear) {
|
sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_DB;
|
}
|
}
|
|
si_blitter_begin(ctx, SI_CLEAR);
|
util_blitter_clear(sctx->blitter, fb->width, fb->height,
|
util_framebuffer_get_num_layers(fb),
|
buffers, color, depth, stencil);
|
si_blitter_end(ctx);
|
|
if (sctx->db_depth_clear) {
|
sctx->db_depth_clear = false;
|
sctx->db_depth_disable_expclear = false;
|
zstex->depth_cleared = true;
|
si_mark_atom_dirty(sctx, &sctx->db_render_state);
|
}
|
|
if (sctx->db_stencil_clear) {
|
sctx->db_stencil_clear = false;
|
sctx->db_stencil_disable_expclear = false;
|
zstex->stencil_cleared = true;
|
si_mark_atom_dirty(sctx, &sctx->db_render_state);
|
}
|
}
|
|
static void si_clear_render_target(struct pipe_context *ctx,
|
struct pipe_surface *dst,
|
const union pipe_color_union *color,
|
unsigned dstx, unsigned dsty,
|
unsigned width, unsigned height,
|
bool render_condition_enabled)
|
{
|
struct si_context *sctx = (struct si_context *)ctx;
|
|
si_blitter_begin(ctx, SI_CLEAR_SURFACE |
|
(render_condition_enabled ? 0 : SI_DISABLE_RENDER_COND));
|
util_blitter_clear_render_target(sctx->blitter, dst, color,
|
dstx, dsty, width, height);
|
si_blitter_end(ctx);
|
}
|
|
static void si_clear_depth_stencil(struct pipe_context *ctx,
|
struct pipe_surface *dst,
|
unsigned clear_flags,
|
double depth,
|
unsigned stencil,
|
unsigned dstx, unsigned dsty,
|
unsigned width, unsigned height,
|
bool render_condition_enabled)
|
{
|
struct si_context *sctx = (struct si_context *)ctx;
|
|
si_blitter_begin(ctx, SI_CLEAR_SURFACE |
|
(render_condition_enabled ? 0 : SI_DISABLE_RENDER_COND));
|
util_blitter_clear_depth_stencil(sctx->blitter, dst, clear_flags, depth, stencil,
|
dstx, dsty, width, height);
|
si_blitter_end(ctx);
|
}
|
|
static void si_clear_texture(struct pipe_context *pipe,
|
struct pipe_resource *tex,
|
unsigned level,
|
const struct pipe_box *box,
|
const void *data)
|
{
|
struct pipe_screen *screen = pipe->screen;
|
struct r600_texture *rtex = (struct r600_texture*)tex;
|
struct pipe_surface tmpl = {{0}};
|
struct pipe_surface *sf;
|
const struct util_format_description *desc =
|
util_format_description(tex->format);
|
|
tmpl.format = tex->format;
|
tmpl.u.tex.first_layer = box->z;
|
tmpl.u.tex.last_layer = box->z + box->depth - 1;
|
tmpl.u.tex.level = level;
|
sf = pipe->create_surface(pipe, tex, &tmpl);
|
if (!sf)
|
return;
|
|
if (rtex->is_depth) {
|
unsigned clear;
|
float depth;
|
uint8_t stencil = 0;
|
|
/* Depth is always present. */
|
clear = PIPE_CLEAR_DEPTH;
|
desc->unpack_z_float(&depth, 0, data, 0, 1, 1);
|
|
if (rtex->surface.has_stencil) {
|
clear |= PIPE_CLEAR_STENCIL;
|
desc->unpack_s_8uint(&stencil, 0, data, 0, 1, 1);
|
}
|
|
si_clear_depth_stencil(pipe, sf, clear, depth, stencil,
|
box->x, box->y,
|
box->width, box->height, false);
|
} else {
|
union pipe_color_union color;
|
|
/* pipe_color_union requires the full vec4 representation. */
|
if (util_format_is_pure_uint(tex->format))
|
desc->unpack_rgba_uint(color.ui, 0, data, 0, 1, 1);
|
else if (util_format_is_pure_sint(tex->format))
|
desc->unpack_rgba_sint(color.i, 0, data, 0, 1, 1);
|
else
|
desc->unpack_rgba_float(color.f, 0, data, 0, 1, 1);
|
|
if (screen->is_format_supported(screen, tex->format,
|
tex->target, 0,
|
PIPE_BIND_RENDER_TARGET)) {
|
si_clear_render_target(pipe, sf, &color,
|
box->x, box->y,
|
box->width, box->height, false);
|
} else {
|
/* Software fallback - just for R9G9B9E5_FLOAT */
|
util_clear_render_target(pipe, sf, &color,
|
box->x, box->y,
|
box->width, box->height);
|
}
|
}
|
pipe_surface_reference(&sf, NULL);
|
}
|
|
void si_init_clear_functions(struct si_context *sctx)
|
{
|
sctx->b.b.clear = si_clear;
|
sctx->b.b.clear_render_target = si_clear_render_target;
|
sctx->b.b.clear_depth_stencil = si_clear_depth_stencil;
|
sctx->b.b.clear_texture = si_clear_texture;
|
}
|
