/*
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* Copyright 2012 Vadim Girlin <vadimgirlin@gmail.com>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* on the rights to use, copy, modify, merge, publish, distribute, sub
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* license, and/or sell copies of the Software, and to permit persons to whom
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* the Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
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* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
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* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
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* USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors:
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* Vadim Girlin
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*/
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#ifndef R600_ISA_H_
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#define R600_ISA_H_
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#include "util/u_debug.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* ALU flags */
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enum alu_op_flags
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{
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AF_V = (1<<0), /* allowed in vector slots */
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/* allowed in scalar(trans) slot (slots xyz on cayman, may be replicated
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* to w) */
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AF_S = (1<<1),
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AF_4SLOT = (1<<2), /* uses four vector slots (e.g. DOT4) */
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AF_4V = (AF_V | AF_4SLOT),
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AF_VS = (AF_V | AF_S), /* allowed in any slot */
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AF_KILL = (1<<4),
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AF_PRED = (1<<5),
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AF_SET = (1<<6),
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/* e.g. MUL_PREV instructions, allowed in x/y, depends on z/w */
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AF_PREV_INTERLEAVE = (1<<7),
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AF_MOVA = (1<<8), /* all MOVA instructions */
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AF_IEEE = (1<<10),
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AF_DST_TYPE_MASK = (3<<11),
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AF_FLOAT_DST = 0,
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AF_INT_DST = (1<<11),
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AF_UINT_DST = (3<<11),
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/* DP instructions, 2-slot pairs */
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AF_64 = (1<<13),
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/* 24 bit instructions */
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AF_24 = (1<<14),
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/* DX10 variants */
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AF_DX10 = (1<<15),
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/* result is replicated to all channels (only if AF_4V is also set -
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* for special handling of MULLO_INT on CM) */
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AF_REPL = (1<<16),
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/* interpolation instructions */
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AF_INTERP = (1<<17),
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/* LDS instructions */
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AF_LDS = (1<<20),
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/* e.g. DOT - depends on the next slot in the same group (x<=y/y<=z/z<=w) */
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AF_PREV_NEXT = (1<<21),
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/* int<->flt conversions */
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AF_CVT = (1<<22),
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/* commutative operation on src0 and src1 ( a op b = b op a),
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* includes MULADDs (considering the MUL part on src0 and src1 only) */
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AF_M_COMM = (1 << 23),
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/* associative operation ((a op b) op c) == (a op (b op c)),
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* includes MULADDs (considering the MUL part on src0 and src1 only) */
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AF_M_ASSOC = (1 << 24),
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AF_PRED_PUSH = (1 << 25),
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AF_ANY_PRED = (AF_PRED | AF_PRED_PUSH),
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AF_CMOV = (1 << 26),
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// for SETcc, PREDSETcc, ... - type of comparison
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AF_CMP_TYPE_MASK = (3 << 27),
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AF_FLOAT_CMP = 0,
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AF_INT_CMP = (1 << 27),
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AF_UINT_CMP = (3 << 27),
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/* condition codes - 3 bits */
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AF_CC_SHIFT = 29,
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AF_CC_MASK = (7U << AF_CC_SHIFT),
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AF_CC_E = (0U << AF_CC_SHIFT),
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AF_CC_GT = (1U << AF_CC_SHIFT),
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AF_CC_GE = (2U << AF_CC_SHIFT),
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AF_CC_NE = (3U << AF_CC_SHIFT),
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AF_CC_LT = (4U << AF_CC_SHIFT),
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AF_CC_LE = (5U << AF_CC_SHIFT),
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};
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/* flags for FETCH instructions (TEX/VTX/GDS) */
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enum fetch_op_flags
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{
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FF_GDS = (1<<0),
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FF_TEX = (1<<1),
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FF_SETGRAD = (1<<2),
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FF_GETGRAD = (1<<3),
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FF_USEGRAD = (1<<4),
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FF_VTX = (1<<5),
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FF_MEM = (1<<6),
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FF_SET_TEXTURE_OFFSETS = (1<<7),
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FF_USE_TEXTURE_OFFSETS = (1<<8),
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};
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/* flags for CF instructions */
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enum cf_op_flags
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{
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CF_CLAUSE = (1<<0), /* execute clause (alu/fetch ...) */
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CF_ACK = (1<<1), /* acked versions of some instructions */
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CF_ALU = (1<<2), /* alu clause execution */
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CF_ALU_EXT = (1<<3), /* ALU_EXTENDED */
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CF_EXP = (1<<4), /* export (CF_ALLOC_EXPORT_WORD1_SWIZ) */
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CF_BRANCH = (1<<5), /* branch instructions */
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CF_LOOP = (1<<6), /* loop instructions */
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CF_CALL = (1<<7), /* call instructions */
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CF_MEM = (1<<8), /* export_mem (CF_ALLOC_EXPORT_WORD1_BUF) */
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CF_FETCH = (1<<9), /* fetch clause */
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CF_UNCOND = (1<<10), /* COND = ACTIVE required */
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CF_EMIT = (1<<11),
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CF_STRM = (1<<12), /* MEM_STREAM* */
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CF_RAT = (1<<13), /* MEM_RAT* */
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CF_LOOP_START = (1<<14)
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};
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/* ALU instruction info */
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struct alu_op_info
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{
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/* instruction name */
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const char *name;
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/* number of source operands */
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int src_count;
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/* opcodes, [0] - for r6xx/r7xx, [1] - for evergreen/cayman
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* (-1) if instruction doesn't exist (more precise info in "slots") */
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int opcode[2];
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/* slots for r6xx, r7xx, evergreen, cayman
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* (0 if instruction doesn't exist for chip class) */
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int slots[4];
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/* flags (mostly autogenerated from instruction name) */
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unsigned int flags;
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};
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/* FETCH instruction info */
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struct fetch_op_info
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{
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const char * name;
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/* for every chip class */
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int opcode[4];
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int flags;
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};
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/* CF instruction info */
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struct cf_op_info
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{
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const char * name;
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/* for every chip class */
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int opcode[4];
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int flags;
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};
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#define ALU_OP2_ADD 0
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#define ALU_OP2_MUL 1
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#define ALU_OP2_MUL_IEEE 2
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#define ALU_OP2_MAX 3
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#define ALU_OP2_MIN 4
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#define ALU_OP2_MAX_DX10 5
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#define ALU_OP2_MIN_DX10 6
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#define ALU_OP2_SETE 7
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#define ALU_OP2_SETGT 8
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#define ALU_OP2_SETGE 9
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#define ALU_OP2_SETNE 10
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#define ALU_OP2_SETE_DX10 11
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#define ALU_OP2_SETGT_DX10 12
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#define ALU_OP2_SETGE_DX10 13
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#define ALU_OP2_SETNE_DX10 14
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#define ALU_OP1_FRACT 15
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#define ALU_OP1_TRUNC 16
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#define ALU_OP1_CEIL 17
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#define ALU_OP1_RNDNE 18
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#define ALU_OP1_FLOOR 19
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#define ALU_OP2_ASHR_INT 20
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#define ALU_OP2_LSHR_INT 21
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#define ALU_OP2_LSHL_INT 22
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#define ALU_OP1_MOV 23
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#define ALU_OP0_NOP 24
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#define ALU_OP2_PRED_SETGT_UINT 25
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#define ALU_OP2_PRED_SETGE_UINT 26
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#define ALU_OP2_PRED_SETE 27
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#define ALU_OP2_PRED_SETGT 28
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#define ALU_OP2_PRED_SETGE 29
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#define ALU_OP2_PRED_SETNE 30
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#define ALU_OP1_PRED_SET_INV 31
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#define ALU_OP2_PRED_SET_POP 32
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#define ALU_OP0_PRED_SET_CLR 33
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#define ALU_OP1_PRED_SET_RESTORE 34
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#define ALU_OP2_PRED_SETE_PUSH 35
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#define ALU_OP2_PRED_SETGT_PUSH 36
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#define ALU_OP2_PRED_SETGE_PUSH 37
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#define ALU_OP2_PRED_SETNE_PUSH 38
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#define ALU_OP2_KILLE 39
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#define ALU_OP2_KILLGT 40
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#define ALU_OP2_KILLGE 41
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#define ALU_OP2_KILLNE 42
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#define ALU_OP2_AND_INT 43
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#define ALU_OP2_OR_INT 44
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#define ALU_OP2_XOR_INT 45
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#define ALU_OP1_NOT_INT 46
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#define ALU_OP2_ADD_INT 47
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#define ALU_OP2_SUB_INT 48
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#define ALU_OP2_MAX_INT 49
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#define ALU_OP2_MIN_INT 50
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#define ALU_OP2_MAX_UINT 51
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#define ALU_OP2_MIN_UINT 52
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#define ALU_OP2_SETE_INT 53
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#define ALU_OP2_SETGT_INT 54
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#define ALU_OP2_SETGE_INT 55
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#define ALU_OP2_SETNE_INT 56
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#define ALU_OP2_SETGT_UINT 57
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#define ALU_OP2_SETGE_UINT 58
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#define ALU_OP2_KILLGT_UINT 59
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#define ALU_OP2_KILLGE_UINT 60
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#define ALU_OP2_PRED_SETE_INT 61
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#define ALU_OP2_PRED_SETGT_INT 62
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#define ALU_OP2_PRED_SETGE_INT 63
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#define ALU_OP2_PRED_SETNE_INT 64
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#define ALU_OP2_KILLE_INT 65
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#define ALU_OP2_KILLGT_INT 66
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#define ALU_OP2_KILLGE_INT 67
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#define ALU_OP2_KILLNE_INT 68
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#define ALU_OP2_PRED_SETE_PUSH_INT 69
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#define ALU_OP2_PRED_SETGT_PUSH_INT 70
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#define ALU_OP2_PRED_SETGE_PUSH_INT 71
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#define ALU_OP2_PRED_SETNE_PUSH_INT 72
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#define ALU_OP2_PRED_SETLT_PUSH_INT 73
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#define ALU_OP2_PRED_SETLE_PUSH_INT 74
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#define ALU_OP1_FLT_TO_INT 75
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#define ALU_OP1_BFREV_INT 76
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#define ALU_OP2_ADDC_UINT 77
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#define ALU_OP2_SUBB_UINT 78
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#define ALU_OP0_GROUP_BARRIER 79
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#define ALU_OP0_GROUP_SEQ_BEGIN 80
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#define ALU_OP0_GROUP_SEQ_END 81
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#define ALU_OP2_SET_MODE 82
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#define ALU_OP0_SET_CF_IDX0 83
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#define ALU_OP0_SET_CF_IDX1 84
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#define ALU_OP2_SET_LDS_SIZE 85
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#define ALU_OP2_MUL_INT24 86
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#define ALU_OP2_MULHI_INT24 87
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#define ALU_OP1_FLT_TO_INT_TRUNC 88
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#define ALU_OP1_EXP_IEEE 89
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#define ALU_OP1_LOG_CLAMPED 90
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#define ALU_OP1_LOG_IEEE 91
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#define ALU_OP1_RECIP_CLAMPED 92
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#define ALU_OP1_RECIP_FF 93
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#define ALU_OP1_RECIP_IEEE 94
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#define ALU_OP1_RECIPSQRT_CLAMPED 95
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#define ALU_OP1_RECIPSQRT_FF 96
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#define ALU_OP1_RECIPSQRT_IEEE 97
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#define ALU_OP1_SQRT_IEEE 98
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#define ALU_OP1_SIN 99
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#define ALU_OP1_COS 100
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#define ALU_OP2_MULLO_INT 101
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#define ALU_OP2_MULHI_INT 102
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#define ALU_OP2_MULLO_UINT 103
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#define ALU_OP2_MULHI_UINT 104
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#define ALU_OP1_RECIP_INT 105
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#define ALU_OP1_RECIP_UINT 106
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#define ALU_OP2_RECIP_64 107
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#define ALU_OP2_RECIP_CLAMPED_64 108
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#define ALU_OP2_RECIPSQRT_64 109
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#define ALU_OP2_RECIPSQRT_CLAMPED_64 110
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#define ALU_OP2_SQRT_64 111
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#define ALU_OP1_FLT_TO_UINT 112
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#define ALU_OP1_INT_TO_FLT 113
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#define ALU_OP1_UINT_TO_FLT 114
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#define ALU_OP2_BFM_INT 115
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#define ALU_OP1_FLT32_TO_FLT16 116
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#define ALU_OP1_FLT16_TO_FLT32 117
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#define ALU_OP1_UBYTE0_FLT 118
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#define ALU_OP1_UBYTE1_FLT 119
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#define ALU_OP1_UBYTE2_FLT 120
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#define ALU_OP1_UBYTE3_FLT 121
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#define ALU_OP1_BCNT_INT 122
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#define ALU_OP1_FFBH_UINT 123
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#define ALU_OP1_FFBL_INT 124
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#define ALU_OP1_FFBH_INT 125
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#define ALU_OP1_FLT_TO_UINT4 126
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#define ALU_OP2_DOT_IEEE 127
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#define ALU_OP1_FLT_TO_INT_RPI 128
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#define ALU_OP1_FLT_TO_INT_FLOOR 129
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#define ALU_OP2_MULHI_UINT24 130
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#define ALU_OP1_MBCNT_32HI_INT 131
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#define ALU_OP1_OFFSET_TO_FLT 132
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#define ALU_OP2_MUL_UINT24 133
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#define ALU_OP1_BCNT_ACCUM_PREV_INT 134
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#define ALU_OP1_MBCNT_32LO_ACCUM_PREV_INT 135
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#define ALU_OP2_SETE_64 136
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#define ALU_OP2_SETNE_64 137
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#define ALU_OP2_SETGT_64 138
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#define ALU_OP2_SETGE_64 139
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#define ALU_OP2_MIN_64 140
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#define ALU_OP2_MAX_64 141
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#define ALU_OP2_DOT4 142
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#define ALU_OP2_DOT4_IEEE 143
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#define ALU_OP2_CUBE 144
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#define ALU_OP1_MAX4 145
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#define ALU_OP1_FREXP_64 146
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#define ALU_OP2_LDEXP_64 147
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#define ALU_OP1_FRACT_64 148
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#define ALU_OP2_PRED_SETGT_64 149
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#define ALU_OP2_PRED_SETE_64 150
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#define ALU_OP2_PRED_SETGE_64 151
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#define ALU_OP2_MUL_64 152
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#define ALU_OP2_ADD_64 153
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#define ALU_OP1_MOVA_INT 154
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#define ALU_OP1_FLT64_TO_FLT32 155
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#define ALU_OP1_FLT32_TO_FLT64 156
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#define ALU_OP2_SAD_ACCUM_PREV_UINT 157
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#define ALU_OP2_DOT 158
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#define ALU_OP1_MUL_PREV 159
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#define ALU_OP1_MUL_IEEE_PREV 160
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#define ALU_OP1_ADD_PREV 161
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#define ALU_OP2_MULADD_PREV 162
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#define ALU_OP2_MULADD_IEEE_PREV 163
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#define ALU_OP2_INTERP_XY 164
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#define ALU_OP2_INTERP_ZW 165
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#define ALU_OP2_INTERP_X 166
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#define ALU_OP2_INTERP_Z 167
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#define ALU_OP1_STORE_FLAGS 168
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#define ALU_OP1_LOAD_STORE_FLAGS 169
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#define ALU_OP2_LDS_1A 170
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#define ALU_OP2_LDS_1A1D 171
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#define ALU_OP2_LDS_2A 172
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#define ALU_OP1_INTERP_LOAD_P0 173
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#define ALU_OP1_INTERP_LOAD_P10 174
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#define ALU_OP1_INTERP_LOAD_P20 175
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#define ALU_OP3_BFE_UINT 176
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#define ALU_OP3_BFE_INT 177
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#define ALU_OP3_BFI_INT 178
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#define ALU_OP3_FMA 179
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#define ALU_OP3_MULADD_INT24 180
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#define ALU_OP3_CNDNE_64 181
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#define ALU_OP3_FMA_64 182
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#define ALU_OP3_LERP_UINT 183
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#define ALU_OP3_BIT_ALIGN_INT 184
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#define ALU_OP3_BYTE_ALIGN_INT 185
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#define ALU_OP3_SAD_ACCUM_UINT 186
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#define ALU_OP3_SAD_ACCUM_HI_UINT 187
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#define ALU_OP3_MULADD_UINT24 188
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#define ALU_OP3_LDS_IDX_OP 189
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#define ALU_OP3_MULADD 190
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#define ALU_OP3_MULADD_M2 191
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#define ALU_OP3_MULADD_M4 192
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#define ALU_OP3_MULADD_D2 193
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#define ALU_OP3_MULADD_IEEE 194
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#define ALU_OP3_CNDE 195
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#define ALU_OP3_CNDGT 196
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#define ALU_OP3_CNDGE 197
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#define ALU_OP3_CNDE_INT 198
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#define ALU_OP3_CNDGT_INT 199
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#define ALU_OP3_CNDGE_INT 200
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#define ALU_OP3_MUL_LIT 201
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#define ALU_OP1_MOVA 202
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#define ALU_OP1_MOVA_FLOOR 203
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#define ALU_OP1_MOVA_GPR_INT 204
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#define ALU_OP3_MULADD_64 205
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#define ALU_OP3_MULADD_64_M2 206
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#define ALU_OP3_MULADD_64_M4 207
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#define ALU_OP3_MULADD_64_D2 208
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#define ALU_OP3_MUL_LIT_M2 209
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#define ALU_OP3_MUL_LIT_M4 210
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#define ALU_OP3_MUL_LIT_D2 211
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#define ALU_OP3_MULADD_IEEE_M2 212
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#define ALU_OP3_MULADD_IEEE_M4 213
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#define ALU_OP3_MULADD_IEEE_D2 214
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#define LDS_OP2_LDS_ADD 215
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#define LDS_OP2_LDS_SUB 216
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#define LDS_OP2_LDS_RSUB 217
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#define LDS_OP2_LDS_INC 218
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#define LDS_OP2_LDS_DEC 219
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#define LDS_OP2_LDS_MIN_INT 220
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#define LDS_OP2_LDS_MAX_INT 221
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#define LDS_OP2_LDS_MIN_UINT 222
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#define LDS_OP2_LDS_MAX_UINT 223
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#define LDS_OP2_LDS_AND 224
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#define LDS_OP2_LDS_OR 225
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#define LDS_OP2_LDS_XOR 226
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#define LDS_OP3_LDS_MSKOR 227
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#define LDS_OP2_LDS_WRITE 228
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#define LDS_OP3_LDS_WRITE_REL 229
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#define LDS_OP3_LDS_WRITE2 230
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#define LDS_OP3_LDS_CMP_STORE 231
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#define LDS_OP3_LDS_CMP_STORE_SPF 232
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#define LDS_OP2_LDS_BYTE_WRITE 233
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#define LDS_OP2_LDS_SHORT_WRITE 234
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#define LDS_OP2_LDS_ADD_RET 235
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#define LDS_OP2_LDS_SUB_RET 236
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#define LDS_OP2_LDS_RSUB_RET 237
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#define LDS_OP2_LDS_INC_RET 238
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#define LDS_OP2_LDS_DEC_RET 239
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#define LDS_OP2_LDS_MIN_INT_RET 240
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#define LDS_OP2_LDS_MAX_INT_RET 241
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#define LDS_OP2_LDS_MIN_UINT_RET 242
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#define LDS_OP2_LDS_MAX_UINT_RET 243
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#define LDS_OP2_LDS_AND_RET 244
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#define LDS_OP2_LDS_OR_RET 245
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#define LDS_OP2_LDS_XOR_RET 246
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#define LDS_OP3_LDS_MSKOR_RET 247
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#define LDS_OP2_LDS_XCHG_RET 248
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#define LDS_OP3_LDS_XCHG_REL_RET 249
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#define LDS_OP3_LDS_XCHG2_RET 250
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#define LDS_OP3_LDS_CMP_XCHG_RET 251
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#define LDS_OP3_LDS_CMP_XCHG_SPF_RET 252
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#define LDS_OP1_LDS_READ_RET 253
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#define LDS_OP1_LDS_READ_REL_RET 254
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#define LDS_OP2_LDS_READ2_RET 255
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#define LDS_OP3_LDS_READWRITE_RET 256
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#define LDS_OP1_LDS_BYTE_READ_RET 257
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#define LDS_OP1_LDS_UBYTE_READ_RET 258
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#define LDS_OP1_LDS_SHORT_READ_RET 259
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#define LDS_OP1_LDS_USHORT_READ_RET 260
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#define FETCH_OP_VFETCH 0
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#define FETCH_OP_SEMFETCH 1
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#define FETCH_OP_READ_SCRATCH 2
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#define FETCH_OP_READ_REDUCT 3
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#define FETCH_OP_READ_MEM 4
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#define FETCH_OP_DS_LOCAL_WRITE 5
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#define FETCH_OP_DS_LOCAL_READ 6
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#define FETCH_OP_GDS_ADD 7
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#define FETCH_OP_GDS_SUB 8
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#define FETCH_OP_GDS_RSUB 9
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#define FETCH_OP_GDS_INC 10
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#define FETCH_OP_GDS_DEC 11
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#define FETCH_OP_GDS_MIN_INT 12
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#define FETCH_OP_GDS_MAX_INT 13
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#define FETCH_OP_GDS_MIN_UINT 14
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#define FETCH_OP_GDS_MAX_UINT 15
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#define FETCH_OP_GDS_AND 16
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#define FETCH_OP_GDS_OR 17
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#define FETCH_OP_GDS_XOR 18
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#define FETCH_OP_GDS_MSKOR 19
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#define FETCH_OP_GDS_WRITE 20
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#define FETCH_OP_GDS_WRITE_REL 21
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#define FETCH_OP_GDS_WRITE2 22
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#define FETCH_OP_GDS_CMP_STORE 23
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#define FETCH_OP_GDS_CMP_STORE_SPF 24
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#define FETCH_OP_GDS_BYTE_WRITE 25
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#define FETCH_OP_GDS_SHORT_WRITE 26
|
#define FETCH_OP_GDS_ADD_RET 27
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#define FETCH_OP_GDS_SUB_RET 28
|
#define FETCH_OP_GDS_RSUB_RET 29
|
#define FETCH_OP_GDS_INC_RET 30
|
#define FETCH_OP_GDS_DEC_RET 31
|
#define FETCH_OP_GDS_MIN_INT_RET 32
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#define FETCH_OP_GDS_MAX_INT_RET 33
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#define FETCH_OP_GDS_MIN_UINT_RET 34
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#define FETCH_OP_GDS_MAX_UINT_RET 35
|
#define FETCH_OP_GDS_AND_RET 36
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#define FETCH_OP_GDS_OR_RET 37
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#define FETCH_OP_GDS_XOR_RET 38
|
#define FETCH_OP_GDS_MSKOR_RET 39
|
#define FETCH_OP_GDS_XCHG_RET 40
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#define FETCH_OP_GDS_XCHG_REL_RET 41
|
#define FETCH_OP_GDS_XCHG2_RET 42
|
#define FETCH_OP_GDS_CMP_XCHG_RET 43
|
#define FETCH_OP_GDS_CMP_XCHG_SPF_RET 44
|
#define FETCH_OP_GDS_READ_RET 45
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#define FETCH_OP_GDS_READ_REL_RET 46
|
#define FETCH_OP_GDS_READ2_RET 47
|
#define FETCH_OP_GDS_READWRITE_RET 48
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#define FETCH_OP_GDS_BYTE_READ_RET 49
|
#define FETCH_OP_GDS_UBYTE_READ_RET 50
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#define FETCH_OP_GDS_SHORT_READ_RET 51
|
#define FETCH_OP_GDS_USHORT_READ_RET 52
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#define FETCH_OP_GDS_ATOMIC_ORDERED_ALLOC 53
|
#define FETCH_OP_TF_WRITE 54
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#define FETCH_OP_DS_GLOBAL_WRITE 55
|
#define FETCH_OP_DS_GLOBAL_READ 56
|
#define FETCH_OP_LD 57
|
#define FETCH_OP_LDFPTR 58
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#define FETCH_OP_GET_TEXTURE_RESINFO 59
|
#define FETCH_OP_GET_NUMBER_OF_SAMPLES 60
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#define FETCH_OP_GET_LOD 61
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#define FETCH_OP_GET_GRADIENTS_H 62
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#define FETCH_OP_GET_GRADIENTS_V 63
|
#define FETCH_OP_GET_GRADIENTS_H_FINE 64
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#define FETCH_OP_GET_GRADIENTS_V_FINE 65
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#define FETCH_OP_GET_LERP 66
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#define FETCH_OP_SET_TEXTURE_OFFSETS 67
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#define FETCH_OP_KEEP_GRADIENTS 68
|
#define FETCH_OP_SET_GRADIENTS_H 69
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#define FETCH_OP_SET_GRADIENTS_V 70
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#define FETCH_OP_SET_GRADIENTS_H_COARSE 71
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#define FETCH_OP_SET_GRADIENTS_V_COARSE 72
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#define FETCH_OP_SET_GRADIENTS_H_PACKED_FINE 73
|
#define FETCH_OP_SET_GRADIENTS_V_PACKED_FINE 74
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#define FETCH_OP_SET_GRADIENTS_H_PACKED_COARSE 75
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#define FETCH_OP_SET_GRADIENTS_V_PACKED_COARSE 76
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#define FETCH_OP_PASS 77
|
#define FETCH_OP_PASS1 78
|
#define FETCH_OP_PASS2 79
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#define FETCH_OP_PASS3 80
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#define FETCH_OP_SET_CUBEMAP_INDEX 81
|
#define FETCH_OP_GET_BUFFER_RESINFO 82
|
#define FETCH_OP_FETCH4 83
|
#define FETCH_OP_SAMPLE 84
|
#define FETCH_OP_SAMPLE_L 85
|
#define FETCH_OP_SAMPLE_LB 86
|
#define FETCH_OP_SAMPLE_LZ 87
|
#define FETCH_OP_SAMPLE_G 88
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#define FETCH_OP_SAMPLE_G_L 89
|
#define FETCH_OP_GATHER4 90
|
#define FETCH_OP_SAMPLE_G_LB 91
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#define FETCH_OP_SAMPLE_G_LZ 92
|
#define FETCH_OP_GATHER4_O 93
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#define FETCH_OP_SAMPLE_C 94
|
#define FETCH_OP_SAMPLE_C_L 95
|
#define FETCH_OP_SAMPLE_C_LB 96
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#define FETCH_OP_SAMPLE_C_LZ 97
|
#define FETCH_OP_SAMPLE_C_G 98
|
#define FETCH_OP_SAMPLE_C_G_L 99
|
#define FETCH_OP_GATHER4_C 100
|
#define FETCH_OP_SAMPLE_C_G_LB 101
|
#define FETCH_OP_SAMPLE_C_G_LZ 102
|
#define FETCH_OP_GATHER4_C_O 103
|
|
#define CF_OP_NOP 0
|
#define CF_OP_TEX 1
|
#define CF_OP_VTX 2
|
#define CF_OP_VTX_TC 3
|
#define CF_OP_GDS 4
|
#define CF_OP_LOOP_START 5
|
#define CF_OP_LOOP_END 6
|
#define CF_OP_LOOP_START_DX10 7
|
#define CF_OP_LOOP_START_NO_AL 8
|
#define CF_OP_LOOP_CONTINUE 9
|
#define CF_OP_LOOP_BREAK 10
|
#define CF_OP_JUMP 11
|
#define CF_OP_PUSH 12
|
#define CF_OP_PUSH_ELSE 13
|
#define CF_OP_ELSE 14
|
#define CF_OP_POP 15
|
#define CF_OP_POP_JUMP 16
|
#define CF_OP_POP_PUSH 17
|
#define CF_OP_POP_PUSH_ELSE 18
|
#define CF_OP_CALL 19
|
#define CF_OP_CALL_FS 20
|
#define CF_OP_RET 21
|
#define CF_OP_EMIT_VERTEX 22
|
#define CF_OP_EMIT_CUT_VERTEX 23
|
#define CF_OP_CUT_VERTEX 24
|
#define CF_OP_KILL 25
|
#define CF_OP_END_PROGRAM 26
|
#define CF_OP_WAIT_ACK 27
|
#define CF_OP_TEX_ACK 28
|
#define CF_OP_VTX_ACK 29
|
#define CF_OP_VTX_TC_ACK 30
|
#define CF_OP_JUMPTABLE 31
|
#define CF_OP_WAVE_SYNC 32
|
#define CF_OP_HALT 33
|
#define CF_OP_CF_END 34
|
#define CF_OP_LDS_DEALLOC 35
|
#define CF_OP_PUSH_WQM 36
|
#define CF_OP_POP_WQM 37
|
#define CF_OP_ELSE_WQM 38
|
#define CF_OP_JUMP_ANY 39
|
#define CF_OP_REACTIVATE 40
|
#define CF_OP_REACTIVATE_WQM 41
|
#define CF_OP_INTERRUPT 42
|
#define CF_OP_INTERRUPT_AND_SLEEP 43
|
#define CF_OP_SET_PRIORITY 44
|
#define CF_OP_MEM_STREAM0_BUF0 45
|
#define CF_OP_MEM_STREAM0_BUF1 46
|
#define CF_OP_MEM_STREAM0_BUF2 47
|
#define CF_OP_MEM_STREAM0_BUF3 48
|
#define CF_OP_MEM_STREAM1_BUF0 49
|
#define CF_OP_MEM_STREAM1_BUF1 50
|
#define CF_OP_MEM_STREAM1_BUF2 51
|
#define CF_OP_MEM_STREAM1_BUF3 52
|
#define CF_OP_MEM_STREAM2_BUF0 53
|
#define CF_OP_MEM_STREAM2_BUF1 54
|
#define CF_OP_MEM_STREAM2_BUF2 55
|
#define CF_OP_MEM_STREAM2_BUF3 56
|
#define CF_OP_MEM_STREAM3_BUF0 57
|
#define CF_OP_MEM_STREAM3_BUF1 58
|
#define CF_OP_MEM_STREAM3_BUF2 59
|
#define CF_OP_MEM_STREAM3_BUF3 60
|
#define CF_OP_MEM_STREAM0 61
|
#define CF_OP_MEM_STREAM1 62
|
#define CF_OP_MEM_STREAM2 63
|
#define CF_OP_MEM_STREAM3 64
|
#define CF_OP_MEM_SCRATCH 65
|
#define CF_OP_MEM_REDUCT 66
|
#define CF_OP_MEM_RING 67
|
#define CF_OP_EXPORT 68
|
#define CF_OP_EXPORT_DONE 69
|
#define CF_OP_MEM_EXPORT 70
|
#define CF_OP_MEM_RAT 71
|
#define CF_OP_MEM_RAT_NOCACHE 72
|
#define CF_OP_MEM_RING1 73
|
#define CF_OP_MEM_RING2 74
|
#define CF_OP_MEM_RING3 75
|
#define CF_OP_MEM_MEM_COMBINED 76
|
#define CF_OP_MEM_RAT_COMBINED_NOCACHE 77
|
#define CF_OP_MEM_RAT_COMBINED 78
|
#define CF_OP_EXPORT_DONE_END 79
|
#define CF_OP_ALU 80
|
#define CF_OP_ALU_PUSH_BEFORE 81
|
#define CF_OP_ALU_POP_AFTER 82
|
#define CF_OP_ALU_POP2_AFTER 83
|
#define CF_OP_ALU_EXT 84
|
#define CF_OP_ALU_CONTINUE 85
|
#define CF_OP_ALU_BREAK 86
|
#define CF_OP_ALU_ELSE_AFTER 87
|
|
/* CF_NATIVE means that r600_bytecode_cf contains pre-encoded native data */
|
#define CF_NATIVE 88
|
|
enum r600_chip_class {
|
ISA_CC_R600,
|
ISA_CC_R700,
|
ISA_CC_EVERGREEN,
|
ISA_CC_CAYMAN
|
};
|
|
struct r600_isa {
|
enum r600_chip_class hw_class;
|
|
/* these arrays provide reverse mapping - opcode => table_index,
|
* typically we don't need such lookup, unless we are decoding the native
|
* bytecode (e.g. when reading the bytestream from llvm backend) */
|
unsigned *alu_op2_map;
|
unsigned *alu_op3_map;
|
unsigned *fetch_map;
|
unsigned *cf_map;
|
};
|
|
struct r600_context;
|
|
int r600_isa_init(struct r600_context *ctx, struct r600_isa *isa);
|
int r600_isa_destroy(struct r600_isa *isa);
|
|
extern const struct alu_op_info r600_alu_op_table[];
|
|
unsigned
|
r600_alu_op_table_size(void);
|
|
const struct alu_op_info *
|
r600_isa_alu(unsigned op);
|
|
const struct fetch_op_info *
|
r600_isa_fetch(unsigned op);
|
|
const struct cf_op_info *
|
r600_isa_cf(unsigned op);
|
|
static inline unsigned
|
r600_isa_alu_opcode(enum r600_chip_class chip_class, unsigned op) {
|
int opc = r600_isa_alu(op)->opcode[chip_class >> 1];
|
assert(opc != -1);
|
return opc;
|
}
|
|
static inline unsigned
|
r600_isa_alu_slots(enum r600_chip_class chip_class, unsigned op) {
|
unsigned slots = r600_isa_alu(op)->slots[chip_class];
|
assert(slots != 0);
|
return slots;
|
}
|
|
static inline unsigned
|
r600_isa_fetch_opcode(enum r600_chip_class chip_class, unsigned op) {
|
int opc = r600_isa_fetch(op)->opcode[chip_class];
|
assert(opc != -1);
|
return opc;
|
}
|
|
static inline unsigned
|
r600_isa_cf_opcode(enum r600_chip_class chip_class, unsigned op) {
|
int opc = r600_isa_cf(op)->opcode[chip_class];
|
assert(opc != -1);
|
return opc;
|
}
|
|
static inline unsigned
|
r600_isa_alu_by_opcode(struct r600_isa* isa, unsigned opcode, unsigned is_op3) {
|
unsigned op;
|
if (is_op3) {
|
assert(isa->alu_op3_map);
|
op = isa->alu_op3_map[opcode];
|
} else {
|
assert(isa->alu_op2_map);
|
op = isa->alu_op2_map[opcode];
|
}
|
assert(op);
|
return op - 1;
|
}
|
|
static inline unsigned
|
r600_isa_fetch_by_opcode(struct r600_isa* isa, unsigned opcode) {
|
unsigned op;
|
assert(isa->fetch_map);
|
op = isa->fetch_map[opcode];
|
assert(op);
|
return op - 1;
|
}
|
|
static inline unsigned
|
r600_isa_cf_by_opcode(struct r600_isa* isa, unsigned opcode, unsigned is_alu) {
|
unsigned op;
|
assert(isa->cf_map);
|
/* using offset for CF_ALU_xxx opcodes because they overlap with other
|
* CF opcodes (they use different encoding in hw) */
|
op = isa->cf_map[is_alu ? opcode + 0x80 : opcode];
|
assert(op);
|
return op - 1;
|
}
|
|
#ifdef __cplusplus
|
} /* extern "C" */
|
#endif
|
|
#endif /* R600_ISA_H_ */
|
