/* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
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/*
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* Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Authors:
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* Rob Clark <robclark@freedesktop.org>
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*/
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#ifndef FREEDRENO_UTIL_H_
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#define FREEDRENO_UTIL_H_
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#include <freedreno_drmif.h>
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#include <freedreno_ringbuffer.h>
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#include "pipe/p_format.h"
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#include "pipe/p_state.h"
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#include "util/u_debug.h"
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#include "util/u_math.h"
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#include "util/u_half.h"
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#include "util/u_dynarray.h"
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#include "util/u_pack_color.h"
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#include "disasm.h"
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#include "adreno_common.xml.h"
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#include "adreno_pm4.xml.h"
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enum adreno_rb_depth_format fd_pipe2depth(enum pipe_format format);
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enum pc_di_index_size fd_pipe2index(enum pipe_format format);
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enum pipe_format fd_gmem_restore_format(enum pipe_format format);
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enum adreno_rb_blend_factor fd_blend_factor(unsigned factor);
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enum adreno_pa_su_sc_draw fd_polygon_mode(unsigned mode);
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enum adreno_stencil_op fd_stencil_op(unsigned op);
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#define A3XX_MAX_MIP_LEVELS 14
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/* TBD if it is same on a2xx, but for now: */
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#define MAX_MIP_LEVELS A3XX_MAX_MIP_LEVELS
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#define A2XX_MAX_RENDER_TARGETS 1
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#define A3XX_MAX_RENDER_TARGETS 4
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#define A4XX_MAX_RENDER_TARGETS 8
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#define A5XX_MAX_RENDER_TARGETS 8
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#define MAX_RENDER_TARGETS A5XX_MAX_RENDER_TARGETS
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#define FD_DBG_MSGS 0x0001
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#define FD_DBG_DISASM 0x0002
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#define FD_DBG_DCLEAR 0x0004
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#define FD_DBG_DDRAW 0x0008
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#define FD_DBG_NOSCIS 0x0010
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#define FD_DBG_DIRECT 0x0020
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#define FD_DBG_NOBYPASS 0x0040
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#define FD_DBG_FRAGHALF 0x0080
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#define FD_DBG_NOBIN 0x0100
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#define FD_DBG_OPTMSGS 0x0200
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#define FD_DBG_GLSL120 0x0400
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#define FD_DBG_SHADERDB 0x0800
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#define FD_DBG_FLUSH 0x1000
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#define FD_DBG_DEQP 0x2000
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#define FD_DBG_INORDER 0x4000
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#define FD_DBG_BSTAT 0x8000
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#define FD_DBG_NOGROW 0x10000
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#define FD_DBG_LRZ 0x20000
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#define FD_DBG_NOINDR 0x40000
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#define FD_DBG_NOBLIT 0x80000
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#define FD_DBG_HIPRIO 0x100000
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#define FD_DBG_TTILE 0x200000
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extern int fd_mesa_debug;
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extern bool fd_binning_enabled;
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#define DBG(fmt, ...) \
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do { if (fd_mesa_debug & FD_DBG_MSGS) \
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debug_printf("%s:%d: "fmt "\n", \
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__FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
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/* for conditionally setting boolean flag(s): */
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#define COND(bool, val) ((bool) ? (val) : 0)
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#define CP_REG(reg) ((0x4 << 16) | ((unsigned int)((reg) - (0x2000))))
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static inline uint32_t DRAW(enum pc_di_primtype prim_type,
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enum pc_di_src_sel source_select, enum pc_di_index_size index_size,
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enum pc_di_vis_cull_mode vis_cull_mode,
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uint8_t instances)
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{
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return (prim_type << 0) |
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(source_select << 6) |
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((index_size & 1) << 11) |
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((index_size >> 1) << 13) |
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(vis_cull_mode << 9) |
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(1 << 14) |
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(instances << 24);
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}
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/* for tracking cmdstream positions that need to be patched: */
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struct fd_cs_patch {
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uint32_t *cs;
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uint32_t val;
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};
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#define fd_patch_num_elements(buf) ((buf)->size / sizeof(struct fd_cs_patch))
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#define fd_patch_element(buf, i) util_dynarray_element(buf, struct fd_cs_patch, i)
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static inline enum pipe_format
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pipe_surface_format(struct pipe_surface *psurf)
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{
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if (!psurf)
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return PIPE_FORMAT_NONE;
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return psurf->format;
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}
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static inline bool
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fd_surface_half_precision(const struct pipe_surface *psurf)
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{
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enum pipe_format format;
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if (!psurf)
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return true;
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format = psurf->format;
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/* colors are provided in consts, which go through cov.f32f16, which will
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* break these values
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*/
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if (util_format_is_pure_integer(format))
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return false;
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/* avoid losing precision on 32-bit float formats */
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if (util_format_is_float(format) &&
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util_format_get_component_bits(format, UTIL_FORMAT_COLORSPACE_RGB, 0) == 32)
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return false;
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return true;
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}
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static inline unsigned
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fd_sampler_first_level(const struct pipe_sampler_view *view)
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{
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if (view->target == PIPE_BUFFER)
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return 0;
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return view->u.tex.first_level;
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}
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static inline unsigned
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fd_sampler_last_level(const struct pipe_sampler_view *view)
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{
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if (view->target == PIPE_BUFFER)
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return 0;
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return view->u.tex.last_level;
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}
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static inline bool
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fd_half_precision(struct pipe_framebuffer_state *pfb)
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{
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unsigned i;
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for (i = 0; i < pfb->nr_cbufs; i++)
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if (!fd_surface_half_precision(pfb->cbufs[i]))
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return false;
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return true;
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}
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#define LOG_DWORDS 0
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static inline void emit_marker(struct fd_ringbuffer *ring, int scratch_idx);
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static inline void emit_marker5(struct fd_ringbuffer *ring, int scratch_idx);
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static inline void
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OUT_RING(struct fd_ringbuffer *ring, uint32_t data)
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{
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if (LOG_DWORDS) {
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DBG("ring[%p]: OUT_RING %04x: %08x", ring,
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(uint32_t)(ring->cur - ring->last_start), data);
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}
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fd_ringbuffer_emit(ring, data);
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}
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/* like OUT_RING() but appends a cmdstream patch point to 'buf' */
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static inline void
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OUT_RINGP(struct fd_ringbuffer *ring, uint32_t data,
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struct util_dynarray *buf)
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{
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if (LOG_DWORDS) {
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DBG("ring[%p]: OUT_RINGP %04x: %08x", ring,
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(uint32_t)(ring->cur - ring->last_start), data);
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}
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util_dynarray_append(buf, struct fd_cs_patch, ((struct fd_cs_patch){
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.cs = ring->cur++,
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.val = data,
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}));
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}
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/*
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* NOTE: OUT_RELOC*() is 2 dwords (64b) on a5xx+
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*/
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static inline void
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OUT_RELOC(struct fd_ringbuffer *ring, struct fd_bo *bo,
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uint32_t offset, uint64_t or, int32_t shift)
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{
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if (LOG_DWORDS) {
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DBG("ring[%p]: OUT_RELOC %04x: %p+%u << %d", ring,
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(uint32_t)(ring->cur - ring->last_start), bo, offset, shift);
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}
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debug_assert(offset < fd_bo_size(bo));
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fd_ringbuffer_reloc2(ring, &(struct fd_reloc){
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.bo = bo,
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.flags = FD_RELOC_READ,
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.offset = offset,
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.or = or,
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.shift = shift,
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.orhi = or >> 32,
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});
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}
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static inline void
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OUT_RELOCW(struct fd_ringbuffer *ring, struct fd_bo *bo,
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uint32_t offset, uint64_t or, int32_t shift)
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{
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if (LOG_DWORDS) {
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DBG("ring[%p]: OUT_RELOCW %04x: %p+%u << %d", ring,
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(uint32_t)(ring->cur - ring->last_start), bo, offset, shift);
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}
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debug_assert(offset < fd_bo_size(bo));
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fd_ringbuffer_reloc2(ring, &(struct fd_reloc){
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.bo = bo,
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.flags = FD_RELOC_READ | FD_RELOC_WRITE,
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.offset = offset,
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.or = or,
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.shift = shift,
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.orhi = or >> 32,
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});
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}
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static inline void BEGIN_RING(struct fd_ringbuffer *ring, uint32_t ndwords)
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{
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if (ring->cur + ndwords >= ring->end)
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fd_ringbuffer_grow(ring, ndwords);
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}
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static inline uint32_t
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__gpu_id(struct fd_ringbuffer *ring)
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{
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uint64_t val;
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fd_pipe_get_param(ring->pipe, FD_GPU_ID, &val);
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return val;
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}
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static inline void
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OUT_PKT0(struct fd_ringbuffer *ring, uint16_t regindx, uint16_t cnt)
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{
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debug_assert(__gpu_id(ring) < 500);
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BEGIN_RING(ring, cnt+1);
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OUT_RING(ring, CP_TYPE0_PKT | ((cnt-1) << 16) | (regindx & 0x7FFF));
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}
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static inline void
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OUT_PKT2(struct fd_ringbuffer *ring)
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{
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debug_assert(__gpu_id(ring) < 500);
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BEGIN_RING(ring, 1);
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OUT_RING(ring, CP_TYPE2_PKT);
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}
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static inline void
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OUT_PKT3(struct fd_ringbuffer *ring, uint8_t opcode, uint16_t cnt)
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{
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debug_assert(__gpu_id(ring) < 500);
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BEGIN_RING(ring, cnt+1);
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OUT_RING(ring, CP_TYPE3_PKT | ((cnt-1) << 16) | ((opcode & 0xFF) << 8));
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}
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/*
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* Starting with a5xx, pkt4/pkt7 are used instead of pkt0/pkt3
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*/
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static inline unsigned
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_odd_parity_bit(unsigned val)
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{
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/* See: http://graphics.stanford.edu/~seander/bithacks.html#ParityParallel
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* note that we want odd parity so 0x6996 is inverted.
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*/
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val ^= val >> 16;
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val ^= val >> 8;
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val ^= val >> 4;
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val &= 0xf;
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return (~0x6996 >> val) & 1;
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}
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static inline void
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OUT_PKT4(struct fd_ringbuffer *ring, uint16_t regindx, uint16_t cnt)
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{
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BEGIN_RING(ring, cnt+1);
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OUT_RING(ring, CP_TYPE4_PKT | cnt |
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(_odd_parity_bit(cnt) << 7) |
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((regindx & 0x3ffff) << 8) |
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((_odd_parity_bit(regindx) << 27)));
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}
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static inline void
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OUT_PKT7(struct fd_ringbuffer *ring, uint8_t opcode, uint16_t cnt)
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{
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BEGIN_RING(ring, cnt+1);
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OUT_RING(ring, CP_TYPE7_PKT | cnt |
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(_odd_parity_bit(cnt) << 15) |
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((opcode & 0x7f) << 16) |
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((_odd_parity_bit(opcode) << 23)));
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}
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static inline void
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OUT_WFI(struct fd_ringbuffer *ring)
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{
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OUT_PKT3(ring, CP_WAIT_FOR_IDLE, 1);
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OUT_RING(ring, 0x00000000);
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}
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static inline void
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OUT_WFI5(struct fd_ringbuffer *ring)
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{
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OUT_PKT7(ring, CP_WAIT_FOR_IDLE, 0);
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}
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static inline void
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__OUT_IB(struct fd_ringbuffer *ring, bool prefetch, struct fd_ringbuffer *target)
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{
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unsigned count = fd_ringbuffer_cmd_count(target);
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debug_assert(__gpu_id(ring) < 500);
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/* for debug after a lock up, write a unique counter value
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* to scratch6 for each IB, to make it easier to match up
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* register dumps to cmdstream. The combination of IB and
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* DRAW (scratch7) is enough to "triangulate" the particular
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* draw that caused lockup.
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*/
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emit_marker(ring, 6);
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for (unsigned i = 0; i < count; i++) {
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uint32_t dwords;
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OUT_PKT3(ring, prefetch ? CP_INDIRECT_BUFFER_PFE : CP_INDIRECT_BUFFER_PFD, 2);
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dwords = fd_ringbuffer_emit_reloc_ring_full(ring, target, i) / 4;
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assert(dwords > 0);
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OUT_RING(ring, dwords);
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OUT_PKT2(ring);
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}
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emit_marker(ring, 6);
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}
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static inline void
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__OUT_IB5(struct fd_ringbuffer *ring, struct fd_ringbuffer *target)
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{
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unsigned count = fd_ringbuffer_cmd_count(target);
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/* for debug after a lock up, write a unique counter value
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* to scratch6 for each IB, to make it easier to match up
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* register dumps to cmdstream. The combination of IB and
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* DRAW (scratch7) is enough to "triangulate" the particular
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* draw that caused lockup.
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*/
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emit_marker5(ring, 6);
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for (unsigned i = 0; i < count; i++) {
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uint32_t dwords;
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OUT_PKT7(ring, CP_INDIRECT_BUFFER, 3);
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dwords = fd_ringbuffer_emit_reloc_ring_full(ring, target, i) / 4;
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assert(dwords > 0);
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OUT_RING(ring, dwords);
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}
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emit_marker5(ring, 6);
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}
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/* CP_SCRATCH_REG4 is used to hold base address for query results: */
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// XXX annoyingly scratch regs move on a5xx.. and additionally different
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// packet types.. so freedreno_query_hw is going to need a bit of
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// rework..
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#define HW_QUERY_BASE_REG REG_AXXX_CP_SCRATCH_REG4
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static inline void
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emit_marker(struct fd_ringbuffer *ring, int scratch_idx)
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{
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extern unsigned marker_cnt;
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unsigned reg = REG_AXXX_CP_SCRATCH_REG0 + scratch_idx;
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assert(reg != HW_QUERY_BASE_REG);
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if (reg == HW_QUERY_BASE_REG)
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return;
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OUT_PKT0(ring, reg, 1);
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OUT_RING(ring, ++marker_cnt);
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}
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static inline void
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emit_marker5(struct fd_ringbuffer *ring, int scratch_idx)
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{
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extern unsigned marker_cnt;
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//XXX unsigned reg = REG_A5XX_CP_SCRATCH_REG(scratch_idx);
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unsigned reg = 0x00000b78 + scratch_idx;
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OUT_PKT4(ring, reg, 1);
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OUT_RING(ring, ++marker_cnt);
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}
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/* helper to get numeric value from environment variable.. mostly
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* just leaving this here because it is helpful to brute-force figure
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* out unknown formats, etc, which blob driver does not support:
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*/
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static inline uint32_t env2u(const char *envvar)
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{
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char *str = getenv(envvar);
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if (str)
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return strtoul(str, NULL, 0);
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return 0;
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}
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static inline uint32_t
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pack_rgba(enum pipe_format format, const float *rgba)
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{
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union util_color uc;
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util_pack_color(rgba, format, &uc);
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return uc.ui[0];
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}
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/*
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* swap - swap value of @a and @b
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*/
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#define swap(a, b) \
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do { __typeof(a) __tmp = (a); (a) = (b); (b) = __tmp; } while (0)
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#define foreach_bit(b, mask) \
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for (uint32_t _m = (mask); _m && ({(b) = u_bit_scan(&_m); 1;});)
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#define BIT(bit) (1u << bit)
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/*
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* a4xx+ helpers:
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*/
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static inline enum a4xx_state_block
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fd4_stage2shadersb(enum shader_t type)
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{
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switch (type) {
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case SHADER_VERTEX:
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return SB4_VS_SHADER;
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case SHADER_FRAGMENT:
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return SB4_FS_SHADER;
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case SHADER_COMPUTE:
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return SB4_CS_SHADER;
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default:
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unreachable("bad shader type");
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return ~0;
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}
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}
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#endif /* FREEDRENO_UTIL_H_ */
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