/* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
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/*
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* Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Authors:
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* Rob Clark <robclark@freedesktop.org>
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*/
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#include "pipe/p_defines.h"
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#include "pipe/p_screen.h"
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#include "pipe/p_state.h"
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#include "util/u_memory.h"
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#include "util/u_inlines.h"
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#include "util/u_format.h"
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#include "util/u_format_s3tc.h"
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#include "util/u_string.h"
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#include "util/u_debug.h"
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#include "util/os_time.h"
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#include <stdio.h>
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#include <errno.h>
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#include <stdlib.h>
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#include "freedreno_screen.h"
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#include "freedreno_resource.h"
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#include "freedreno_fence.h"
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#include "freedreno_query.h"
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#include "freedreno_util.h"
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#include "a2xx/fd2_screen.h"
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#include "a3xx/fd3_screen.h"
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#include "a4xx/fd4_screen.h"
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#include "a5xx/fd5_screen.h"
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#include "ir3/ir3_nir.h"
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/* XXX this should go away */
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#include "state_tracker/drm_driver.h"
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static const struct debug_named_value debug_options[] = {
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{"msgs", FD_DBG_MSGS, "Print debug messages"},
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{"disasm", FD_DBG_DISASM, "Dump TGSI and adreno shader disassembly"},
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{"dclear", FD_DBG_DCLEAR, "Mark all state dirty after clear"},
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{"ddraw", FD_DBG_DDRAW, "Mark all state dirty after draw"},
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{"noscis", FD_DBG_NOSCIS, "Disable scissor optimization"},
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{"direct", FD_DBG_DIRECT, "Force inline (SS_DIRECT) state loads"},
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{"nobypass", FD_DBG_NOBYPASS, "Disable GMEM bypass"},
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{"fraghalf", FD_DBG_FRAGHALF, "Use half-precision in fragment shader"},
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{"nobin", FD_DBG_NOBIN, "Disable hw binning"},
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{"optmsgs", FD_DBG_OPTMSGS,"Enable optimizer debug messages"},
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{"glsl120", FD_DBG_GLSL120,"Temporary flag to force GLSL 1.20 (rather than 1.30) on a3xx+"},
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{"shaderdb", FD_DBG_SHADERDB, "Enable shaderdb output"},
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{"flush", FD_DBG_FLUSH, "Force flush after every draw"},
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{"deqp", FD_DBG_DEQP, "Enable dEQP hacks"},
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{"inorder", FD_DBG_INORDER,"Disable reordering for draws/blits"},
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{"bstat", FD_DBG_BSTAT, "Print batch stats at context destroy"},
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{"nogrow", FD_DBG_NOGROW, "Disable \"growable\" cmdstream buffers, even if kernel supports it"},
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{"lrz", FD_DBG_LRZ, "Enable experimental LRZ support (a5xx+)"},
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{"noindirect",FD_DBG_NOINDR, "Disable hw indirect draws (emulate on CPU)"},
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{"noblit", FD_DBG_NOBLIT, "Disable blitter (fallback to generic blit path)"},
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{"hiprio", FD_DBG_HIPRIO, "Force high-priority context"},
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{"ttile", FD_DBG_TTILE, "Enable texture tiling (a5xx)"},
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DEBUG_NAMED_VALUE_END
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};
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DEBUG_GET_ONCE_FLAGS_OPTION(fd_mesa_debug, "FD_MESA_DEBUG", debug_options, 0)
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int fd_mesa_debug = 0;
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bool fd_binning_enabled = true;
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static bool glsl120 = false;
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static const char *
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fd_screen_get_name(struct pipe_screen *pscreen)
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{
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static char buffer[128];
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util_snprintf(buffer, sizeof(buffer), "FD%03d",
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fd_screen(pscreen)->device_id);
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return buffer;
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}
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static const char *
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fd_screen_get_vendor(struct pipe_screen *pscreen)
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{
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return "freedreno";
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}
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static const char *
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fd_screen_get_device_vendor(struct pipe_screen *pscreen)
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{
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return "Qualcomm";
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}
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static uint64_t
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fd_screen_get_timestamp(struct pipe_screen *pscreen)
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{
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struct fd_screen *screen = fd_screen(pscreen);
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if (screen->has_timestamp) {
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uint64_t n;
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fd_pipe_get_param(screen->pipe, FD_TIMESTAMP, &n);
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debug_assert(screen->max_freq > 0);
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return n * 1000000000 / screen->max_freq;
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} else {
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int64_t cpu_time = os_time_get() * 1000;
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return cpu_time + screen->cpu_gpu_time_delta;
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}
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}
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static void
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fd_screen_destroy(struct pipe_screen *pscreen)
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{
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struct fd_screen *screen = fd_screen(pscreen);
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if (screen->pipe)
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fd_pipe_del(screen->pipe);
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if (screen->dev)
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fd_device_del(screen->dev);
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fd_bc_fini(&screen->batch_cache);
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slab_destroy_parent(&screen->transfer_pool);
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mtx_destroy(&screen->lock);
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ralloc_free(screen->compiler);
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free(screen);
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}
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/*
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TODO either move caps to a2xx/a3xx specific code, or maybe have some
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tables for things that differ if the delta is not too much..
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*/
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static int
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fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
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{
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struct fd_screen *screen = fd_screen(pscreen);
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/* this is probably not totally correct.. but it's a start: */
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switch (param) {
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/* Supported features (boolean caps). */
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case PIPE_CAP_NPOT_TEXTURES:
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case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
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case PIPE_CAP_ANISOTROPIC_FILTER:
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case PIPE_CAP_POINT_SPRITE:
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case PIPE_CAP_BLEND_EQUATION_SEPARATE:
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case PIPE_CAP_TEXTURE_SWIZZLE:
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case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
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case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
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case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
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case PIPE_CAP_SEAMLESS_CUBE_MAP:
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case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
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case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
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case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
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case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
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case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
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case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
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case PIPE_CAP_STRING_MARKER:
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case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
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case PIPE_CAP_TEXTURE_BARRIER:
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case PIPE_CAP_INVALIDATE_BUFFER:
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return 1;
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case PIPE_CAP_VERTEXID_NOBASE:
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return is_a3xx(screen) || is_a4xx(screen);
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case PIPE_CAP_COMPUTE:
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return has_compute(screen);
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case PIPE_CAP_SHADER_STENCIL_EXPORT:
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case PIPE_CAP_TGSI_TEXCOORD:
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case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
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case PIPE_CAP_TEXTURE_MULTISAMPLE:
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case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
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case PIPE_CAP_QUERY_MEMORY_INFO:
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case PIPE_CAP_PCI_GROUP:
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case PIPE_CAP_PCI_BUS:
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case PIPE_CAP_PCI_DEVICE:
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case PIPE_CAP_PCI_FUNCTION:
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return 0;
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case PIPE_CAP_SM3:
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case PIPE_CAP_PRIMITIVE_RESTART:
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case PIPE_CAP_TGSI_INSTANCEID:
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case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
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case PIPE_CAP_INDEP_BLEND_ENABLE:
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case PIPE_CAP_INDEP_BLEND_FUNC:
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case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
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case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
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case PIPE_CAP_CONDITIONAL_RENDER:
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case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
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case PIPE_CAP_FAKE_SW_MSAA:
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case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
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case PIPE_CAP_CLIP_HALFZ:
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return is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen);
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case PIPE_CAP_DEPTH_CLIP_DISABLE:
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return is_a3xx(screen) || is_a4xx(screen);
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case PIPE_CAP_POLYGON_OFFSET_CLAMP:
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return is_a5xx(screen);
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case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
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return 0;
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case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
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if (is_a3xx(screen)) return 16;
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if (is_a4xx(screen)) return 32;
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if (is_a5xx(screen)) return 32;
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return 0;
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case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
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/* We could possibly emulate more by pretending 2d/rect textures and
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* splitting high bits of index into 2nd dimension..
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*/
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if (is_a3xx(screen)) return 8192;
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if (is_a4xx(screen)) return 16384;
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if (is_a5xx(screen)) return 16384;
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return 0;
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case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
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case PIPE_CAP_CUBE_MAP_ARRAY:
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case PIPE_CAP_SAMPLER_VIEW_TARGET:
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case PIPE_CAP_TEXTURE_QUERY_LOD:
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return is_a4xx(screen) || is_a5xx(screen);
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case PIPE_CAP_START_INSTANCE:
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/* Note that a5xx can do this, it just can't (at least with
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* current firmware) do draw_indirect with base_instance.
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* Since draw_indirect is needed sooner (gles31 and gl40 vs
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* gl42), hide base_instance on a5xx. :-/
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*/
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return is_a4xx(screen);
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case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
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return 64;
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case PIPE_CAP_GLSL_FEATURE_LEVEL:
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if (glsl120)
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return 120;
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return is_ir3(screen) ? 140 : 120;
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case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
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if (is_a5xx(screen))
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return 4;
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return 0;
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case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
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if (is_a4xx(screen) || is_a5xx(screen))
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return 4;
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return 0;
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/* Unsupported features. */
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case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
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case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
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case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
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case PIPE_CAP_USER_VERTEX_BUFFERS:
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case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
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case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
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case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
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case PIPE_CAP_TEXTURE_GATHER_SM5:
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case PIPE_CAP_SAMPLE_SHADING:
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case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
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case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
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case PIPE_CAP_MULTI_DRAW_INDIRECT:
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case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
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case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
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case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
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case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
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case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
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case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
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case PIPE_CAP_DEPTH_BOUNDS_TEST:
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case PIPE_CAP_TGSI_TXQS:
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/* TODO if we need this, do it in nir/ir3 backend to avoid breaking precompile: */
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case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
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case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
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case PIPE_CAP_CLEAR_TEXTURE:
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case PIPE_CAP_DRAW_PARAMETERS:
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case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
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case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
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case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
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case PIPE_CAP_GENERATE_MIPMAP:
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case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
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case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
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case PIPE_CAP_CULL_DISTANCE:
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case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
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case PIPE_CAP_TGSI_VOTE:
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case PIPE_CAP_MAX_WINDOW_RECTANGLES:
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case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
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case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
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case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
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case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
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case PIPE_CAP_TGSI_FS_FBFETCH:
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case PIPE_CAP_TGSI_MUL_ZERO_WINS:
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case PIPE_CAP_DOUBLES:
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case PIPE_CAP_INT64:
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case PIPE_CAP_INT64_DIVMOD:
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case PIPE_CAP_TGSI_TEX_TXF_LZ:
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case PIPE_CAP_TGSI_CLOCK:
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case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
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case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
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case PIPE_CAP_TGSI_BALLOT:
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case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
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case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
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case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
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case PIPE_CAP_POST_DEPTH_COVERAGE:
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case PIPE_CAP_BINDLESS_TEXTURE:
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case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
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case PIPE_CAP_QUERY_SO_OVERFLOW:
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case PIPE_CAP_MEMOBJ:
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case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
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case PIPE_CAP_TILE_RASTER_ORDER:
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case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
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case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
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return 0;
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case PIPE_CAP_CONTEXT_PRIORITY_MASK:
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return screen->priority_mask;
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case PIPE_CAP_DRAW_INDIRECT:
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if (is_a4xx(screen) || is_a5xx(screen))
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return 1;
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return 0;
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case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
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if (is_a4xx(screen) || is_a5xx(screen))
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return 1;
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return 0;
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case PIPE_CAP_LOAD_CONSTBUF:
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/* name is confusing, but this turns on std430 packing */
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if (is_ir3(screen))
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return 1;
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return 0;
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case PIPE_CAP_MAX_VIEWPORTS:
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return 1;
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case PIPE_CAP_SHAREABLE_SHADERS:
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case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
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/* manage the variants for these ourself, to avoid breaking precompile: */
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case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
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case PIPE_CAP_VERTEX_COLOR_CLAMPED:
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if (is_ir3(screen))
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return 1;
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return 0;
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/* Stream output. */
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case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
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if (is_ir3(screen))
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return PIPE_MAX_SO_BUFFERS;
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return 0;
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case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
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case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
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if (is_ir3(screen))
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return 1;
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return 0;
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case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
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case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
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if (is_ir3(screen))
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return 16 * 4; /* should only be shader out limit? */
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return 0;
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/* Geometry shader output, unsupported. */
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case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
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case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
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case PIPE_CAP_MAX_VERTEX_STREAMS:
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return 0;
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case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
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return 2048;
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/* Texturing. */
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case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
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case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
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return MAX_MIP_LEVELS;
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case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
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return 11;
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case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
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return (is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen)) ? 256 : 0;
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/* Render targets. */
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case PIPE_CAP_MAX_RENDER_TARGETS:
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return screen->max_rts;
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case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
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return is_a3xx(screen) ? 1 : 0;
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/* Queries. */
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case PIPE_CAP_QUERY_BUFFER_OBJECT:
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return 0;
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case PIPE_CAP_OCCLUSION_QUERY:
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return is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen);
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case PIPE_CAP_QUERY_TIMESTAMP:
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case PIPE_CAP_QUERY_TIME_ELAPSED:
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/* only a4xx, requires new enough kernel so we know max_freq: */
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return (screen->max_freq > 0) && (is_a4xx(screen) || is_a5xx(screen));
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case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
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case PIPE_CAP_MIN_TEXEL_OFFSET:
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return -8;
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case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
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case PIPE_CAP_MAX_TEXEL_OFFSET:
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return 7;
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case PIPE_CAP_ENDIANNESS:
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return PIPE_ENDIAN_LITTLE;
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case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
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return 64;
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case PIPE_CAP_VENDOR_ID:
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return 0x5143;
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case PIPE_CAP_DEVICE_ID:
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return 0xFFFFFFFF;
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case PIPE_CAP_ACCELERATED:
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return 1;
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case PIPE_CAP_VIDEO_MEMORY:
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DBG("FINISHME: The value returned is incorrect\n");
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return 10;
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case PIPE_CAP_UMA:
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return 1;
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case PIPE_CAP_NATIVE_FENCE_FD:
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return fd_device_version(screen->dev) >= FD_VERSION_FENCE_FD;
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}
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debug_printf("unknown param %d\n", param);
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return 0;
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}
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static float
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fd_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
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{
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switch (param) {
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case PIPE_CAPF_MAX_LINE_WIDTH:
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case PIPE_CAPF_MAX_LINE_WIDTH_AA:
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/* NOTE: actual value is 127.0f, but this is working around a deqp
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* bug.. dEQP-GLES3.functional.rasterization.primitives.lines_wide
|
* uses too small of a render target size, and gets confused when
|
* the lines start going offscreen.
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*
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* See: https://code.google.com/p/android/issues/detail?id=206513
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*/
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if (fd_mesa_debug & FD_DBG_DEQP)
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return 48.0f;
|
return 127.0f;
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case PIPE_CAPF_MAX_POINT_WIDTH:
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case PIPE_CAPF_MAX_POINT_WIDTH_AA:
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return 4092.0f;
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case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
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return 16.0f;
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case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
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return 15.0f;
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case PIPE_CAPF_GUARD_BAND_LEFT:
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case PIPE_CAPF_GUARD_BAND_TOP:
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case PIPE_CAPF_GUARD_BAND_RIGHT:
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case PIPE_CAPF_GUARD_BAND_BOTTOM:
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return 0.0f;
|
}
|
debug_printf("unknown paramf %d\n", param);
|
return 0;
|
}
|
|
static int
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fd_screen_get_shader_param(struct pipe_screen *pscreen,
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enum pipe_shader_type shader,
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enum pipe_shader_cap param)
|
{
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struct fd_screen *screen = fd_screen(pscreen);
|
|
switch(shader)
|
{
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case PIPE_SHADER_FRAGMENT:
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case PIPE_SHADER_VERTEX:
|
break;
|
case PIPE_SHADER_COMPUTE:
|
if (has_compute(screen))
|
break;
|
return 0;
|
case PIPE_SHADER_GEOMETRY:
|
/* maye we could emulate.. */
|
return 0;
|
default:
|
DBG("unknown shader type %d", shader);
|
return 0;
|
}
|
|
/* this is probably not totally correct.. but it's a start: */
|
switch (param) {
|
case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
|
case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
|
case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
|
case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
|
return 16384;
|
case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
|
return 8; /* XXX */
|
case PIPE_SHADER_CAP_MAX_INPUTS:
|
case PIPE_SHADER_CAP_MAX_OUTPUTS:
|
return 16;
|
case PIPE_SHADER_CAP_MAX_TEMPS:
|
return 64; /* Max native temporaries. */
|
case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
|
/* NOTE: seems to be limit for a3xx is actually 512 but
|
* split between VS and FS. Use lower limit of 256 to
|
* avoid getting into impossible situations:
|
*/
|
return ((is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen)) ? 4096 : 64) * sizeof(float[4]);
|
case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
|
return is_ir3(screen) ? 16 : 1;
|
case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
|
return 1;
|
case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
|
case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
|
/* Technically this should be the same as for TEMP/CONST, since
|
* everything is just normal registers. This is just temporary
|
* hack until load_input/store_output handle arrays in a similar
|
* way as load_var/store_var..
|
*/
|
return 0;
|
case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
|
case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
|
/* a2xx compiler doesn't handle indirect: */
|
return is_ir3(screen) ? 1 : 0;
|
case PIPE_SHADER_CAP_SUBROUTINES:
|
case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
|
case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
|
case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
|
case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
|
case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
|
return 0;
|
case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
|
return 1;
|
case PIPE_SHADER_CAP_INTEGERS:
|
if (glsl120)
|
return 0;
|
return is_ir3(screen) ? 1 : 0;
|
case PIPE_SHADER_CAP_INT64_ATOMICS:
|
return 0;
|
case PIPE_SHADER_CAP_FP16:
|
return 0;
|
case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
|
case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
|
return 16;
|
case PIPE_SHADER_CAP_PREFERRED_IR:
|
if (is_ir3(screen))
|
return PIPE_SHADER_IR_NIR;
|
return PIPE_SHADER_IR_TGSI;
|
case PIPE_SHADER_CAP_SUPPORTED_IRS:
|
if (is_ir3(screen)) {
|
return (1 << PIPE_SHADER_IR_NIR) | (1 << PIPE_SHADER_IR_TGSI);
|
} else {
|
return (1 << PIPE_SHADER_IR_TGSI);
|
}
|
return 0;
|
case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
|
return 32;
|
case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
|
case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
|
case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
|
case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
|
return 0;
|
case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
|
case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
|
if (is_a5xx(screen)) {
|
/* a5xx (and a4xx for that matter) has one state-block
|
* for compute-shader SSBO's and another that is shared
|
* by VS/HS/DS/GS/FS.. so to simplify things for now
|
* just advertise SSBOs for FS and CS. We could possibly
|
* do what blob does, and partition the space for
|
* VS/HS/DS/GS/FS. The blob advertises:
|
*
|
* GL_MAX_VERTEX_SHADER_STORAGE_BLOCKS: 4
|
* GL_MAX_GEOMETRY_SHADER_STORAGE_BLOCKS: 4
|
* GL_MAX_TESS_CONTROL_SHADER_STORAGE_BLOCKS: 4
|
* GL_MAX_TESS_EVALUATION_SHADER_STORAGE_BLOCKS: 4
|
* GL_MAX_FRAGMENT_SHADER_STORAGE_BLOCKS: 4
|
* GL_MAX_COMPUTE_SHADER_STORAGE_BLOCKS: 24
|
* GL_MAX_COMBINED_SHADER_STORAGE_BLOCKS: 24
|
*
|
* I think that way we could avoid having to patch shaders
|
* for actual SSBO indexes by using a static partitioning.
|
*
|
* Note same state block is used for images and buffers,
|
* but images also need texture state for read access
|
* (isam/isam.3d)
|
*/
|
switch(shader)
|
{
|
case PIPE_SHADER_FRAGMENT:
|
case PIPE_SHADER_COMPUTE:
|
return 24;
|
default:
|
return 0;
|
}
|
}
|
return 0;
|
}
|
debug_printf("unknown shader param %d\n", param);
|
return 0;
|
}
|
|
/* TODO depending on how much the limits differ for a3xx/a4xx, maybe move this
|
* into per-generation backend?
|
*/
|
static int
|
fd_get_compute_param(struct pipe_screen *pscreen, enum pipe_shader_ir ir_type,
|
enum pipe_compute_cap param, void *ret)
|
{
|
struct fd_screen *screen = fd_screen(pscreen);
|
const char * const ir = "ir3";
|
|
if (!has_compute(screen))
|
return 0;
|
|
switch (param) {
|
case PIPE_COMPUTE_CAP_ADDRESS_BITS:
|
if (ret) {
|
uint32_t *address_bits = ret;
|
address_bits[0] = 32;
|
|
if (is_a5xx(screen))
|
address_bits[0] = 64;
|
}
|
return 1 * sizeof(uint32_t);
|
|
case PIPE_COMPUTE_CAP_IR_TARGET:
|
if (ret)
|
sprintf(ret, ir);
|
return strlen(ir) * sizeof(char);
|
|
case PIPE_COMPUTE_CAP_GRID_DIMENSION:
|
if (ret) {
|
uint64_t *grid_dimension = ret;
|
grid_dimension[0] = 3;
|
}
|
return 1 * sizeof(uint64_t);
|
|
case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
|
if (ret) {
|
uint64_t *grid_size = ret;
|
grid_size[0] = 65535;
|
grid_size[1] = 65535;
|
grid_size[2] = 65535;
|
}
|
return 3 * sizeof(uint64_t) ;
|
|
case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
|
if (ret) {
|
uint64_t *block_size = ret;
|
block_size[0] = 1024;
|
block_size[1] = 1024;
|
block_size[2] = 64;
|
}
|
return 3 * sizeof(uint64_t) ;
|
|
case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
|
if (ret) {
|
uint64_t *max_threads_per_block = ret;
|
*max_threads_per_block = 1024;
|
}
|
return sizeof(uint64_t);
|
|
case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
|
case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
|
if (ret) {
|
uint64_t *local_size = ret;
|
*local_size = 32768;
|
}
|
return sizeof(uint64_t);
|
case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
|
case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
|
break;
|
case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
|
if (ret) {
|
uint64_t *max = ret;
|
*max = 32768;
|
}
|
return sizeof(uint64_t);
|
case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
|
case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
|
case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
|
case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
|
case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
|
break;
|
}
|
|
return 0;
|
}
|
|
static const void *
|
fd_get_compiler_options(struct pipe_screen *pscreen,
|
enum pipe_shader_ir ir, unsigned shader)
|
{
|
struct fd_screen *screen = fd_screen(pscreen);
|
|
if (is_ir3(screen))
|
return ir3_get_compiler_options(screen->compiler);
|
|
return NULL;
|
}
|
|
boolean
|
fd_screen_bo_get_handle(struct pipe_screen *pscreen,
|
struct fd_bo *bo,
|
unsigned stride,
|
struct winsys_handle *whandle)
|
{
|
whandle->stride = stride;
|
|
if (whandle->type == DRM_API_HANDLE_TYPE_SHARED) {
|
return fd_bo_get_name(bo, &whandle->handle) == 0;
|
} else if (whandle->type == DRM_API_HANDLE_TYPE_KMS) {
|
whandle->handle = fd_bo_handle(bo);
|
return TRUE;
|
} else if (whandle->type == DRM_API_HANDLE_TYPE_FD) {
|
whandle->handle = fd_bo_dmabuf(bo);
|
return TRUE;
|
} else {
|
return FALSE;
|
}
|
}
|
|
struct fd_bo *
|
fd_screen_bo_from_handle(struct pipe_screen *pscreen,
|
struct winsys_handle *whandle)
|
{
|
struct fd_screen *screen = fd_screen(pscreen);
|
struct fd_bo *bo;
|
|
if (whandle->type == DRM_API_HANDLE_TYPE_SHARED) {
|
bo = fd_bo_from_name(screen->dev, whandle->handle);
|
} else if (whandle->type == DRM_API_HANDLE_TYPE_KMS) {
|
bo = fd_bo_from_handle(screen->dev, whandle->handle, 0);
|
} else if (whandle->type == DRM_API_HANDLE_TYPE_FD) {
|
bo = fd_bo_from_dmabuf(screen->dev, whandle->handle);
|
} else {
|
DBG("Attempt to import unsupported handle type %d", whandle->type);
|
return NULL;
|
}
|
|
if (!bo) {
|
DBG("ref name 0x%08x failed", whandle->handle);
|
return NULL;
|
}
|
|
return bo;
|
}
|
|
struct pipe_screen *
|
fd_screen_create(struct fd_device *dev)
|
{
|
struct fd_screen *screen = CALLOC_STRUCT(fd_screen);
|
struct pipe_screen *pscreen;
|
uint64_t val;
|
|
fd_mesa_debug = debug_get_option_fd_mesa_debug();
|
|
if (fd_mesa_debug & FD_DBG_NOBIN)
|
fd_binning_enabled = false;
|
|
glsl120 = !!(fd_mesa_debug & FD_DBG_GLSL120);
|
|
if (!screen)
|
return NULL;
|
|
pscreen = &screen->base;
|
|
screen->dev = dev;
|
screen->refcnt = 1;
|
|
// maybe this should be in context?
|
screen->pipe = fd_pipe_new(screen->dev, FD_PIPE_3D);
|
if (!screen->pipe) {
|
DBG("could not create 3d pipe");
|
goto fail;
|
}
|
|
if (fd_pipe_get_param(screen->pipe, FD_GMEM_SIZE, &val)) {
|
DBG("could not get GMEM size");
|
goto fail;
|
}
|
screen->gmemsize_bytes = val;
|
|
if (fd_pipe_get_param(screen->pipe, FD_DEVICE_ID, &val)) {
|
DBG("could not get device-id");
|
goto fail;
|
}
|
screen->device_id = val;
|
|
if (fd_pipe_get_param(screen->pipe, FD_MAX_FREQ, &val)) {
|
DBG("could not get gpu freq");
|
/* this limits what performance related queries are
|
* supported but is not fatal
|
*/
|
screen->max_freq = 0;
|
} else {
|
screen->max_freq = val;
|
if (fd_pipe_get_param(screen->pipe, FD_TIMESTAMP, &val) == 0)
|
screen->has_timestamp = true;
|
}
|
|
if (fd_pipe_get_param(screen->pipe, FD_GPU_ID, &val)) {
|
DBG("could not get gpu-id");
|
goto fail;
|
}
|
screen->gpu_id = val;
|
|
if (fd_pipe_get_param(screen->pipe, FD_CHIP_ID, &val)) {
|
DBG("could not get chip-id");
|
/* older kernels may not have this property: */
|
unsigned core = screen->gpu_id / 100;
|
unsigned major = (screen->gpu_id % 100) / 10;
|
unsigned minor = screen->gpu_id % 10;
|
unsigned patch = 0; /* assume the worst */
|
val = (patch & 0xff) | ((minor & 0xff) << 8) |
|
((major & 0xff) << 16) | ((core & 0xff) << 24);
|
}
|
screen->chip_id = val;
|
|
if (fd_pipe_get_param(screen->pipe, FD_NR_RINGS, &val)) {
|
DBG("could not get # of rings");
|
screen->priority_mask = 0;
|
} else {
|
/* # of rings equates to number of unique priority values: */
|
screen->priority_mask = (1 << val) - 1;
|
}
|
|
DBG("Pipe Info:");
|
DBG(" GPU-id: %d", screen->gpu_id);
|
DBG(" Chip-id: 0x%08x", screen->chip_id);
|
DBG(" GMEM size: 0x%08x", screen->gmemsize_bytes);
|
|
/* explicitly checking for GPU revisions that are known to work. This
|
* may be overly conservative for a3xx, where spoofing the gpu_id with
|
* the blob driver seems to generate identical cmdstream dumps. But
|
* on a2xx, there seem to be small differences between the GPU revs
|
* so it is probably better to actually test first on real hardware
|
* before enabling:
|
*
|
* If you have a different adreno version, feel free to add it to one
|
* of the cases below and see what happens. And if it works, please
|
* send a patch ;-)
|
*/
|
switch (screen->gpu_id) {
|
case 220:
|
fd2_screen_init(pscreen);
|
break;
|
case 305:
|
case 307:
|
case 320:
|
case 330:
|
fd3_screen_init(pscreen);
|
break;
|
case 420:
|
case 430:
|
fd4_screen_init(pscreen);
|
break;
|
case 530:
|
fd5_screen_init(pscreen);
|
break;
|
default:
|
debug_printf("unsupported GPU: a%03d\n", screen->gpu_id);
|
goto fail;
|
}
|
|
if (screen->gpu_id >= 500) {
|
screen->gmem_alignw = 64;
|
screen->gmem_alignh = 32;
|
screen->num_vsc_pipes = 16;
|
} else {
|
screen->gmem_alignw = 32;
|
screen->gmem_alignh = 32;
|
screen->num_vsc_pipes = 8;
|
}
|
|
/* NOTE: don't enable reordering on a2xx, since completely untested.
|
* Also, don't enable if we have too old of a kernel to support
|
* growable cmdstream buffers, since memory requirement for cmdstream
|
* buffers would be too much otherwise.
|
*/
|
if ((screen->gpu_id >= 300) && (fd_device_version(dev) >= FD_VERSION_UNLIMITED_CMDS))
|
screen->reorder = !(fd_mesa_debug & FD_DBG_INORDER);
|
|
fd_bc_init(&screen->batch_cache);
|
|
(void) mtx_init(&screen->lock, mtx_plain);
|
|
pscreen->destroy = fd_screen_destroy;
|
pscreen->get_param = fd_screen_get_param;
|
pscreen->get_paramf = fd_screen_get_paramf;
|
pscreen->get_shader_param = fd_screen_get_shader_param;
|
pscreen->get_compute_param = fd_get_compute_param;
|
pscreen->get_compiler_options = fd_get_compiler_options;
|
|
fd_resource_screen_init(pscreen);
|
fd_query_screen_init(pscreen);
|
|
pscreen->get_name = fd_screen_get_name;
|
pscreen->get_vendor = fd_screen_get_vendor;
|
pscreen->get_device_vendor = fd_screen_get_device_vendor;
|
|
pscreen->get_timestamp = fd_screen_get_timestamp;
|
|
pscreen->fence_reference = fd_fence_ref;
|
pscreen->fence_finish = fd_fence_finish;
|
pscreen->fence_get_fd = fd_fence_get_fd;
|
|
slab_create_parent(&screen->transfer_pool, sizeof(struct fd_transfer), 16);
|
|
return pscreen;
|
|
fail:
|
fd_screen_destroy(pscreen);
|
return NULL;
|
}
|
