/*
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* arch/blackfin/lib/ins.S - ins{bwl} using hardware loops
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*
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* Copyright 2004-2008 Analog Devices Inc.
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* Copyright (C) 2005 Bas Vermeulen, BuyWays BV <bas@buyways.nl>
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* Licensed under the GPL-2 or later.
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*/
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#include <linux/linkage.h>
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#include <asm/blackfin.h>
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.align 2
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#ifdef CONFIG_IPIPE
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# define DO_CLI \
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[--sp] = rets; \
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[--sp] = (P5:0); \
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sp += -12; \
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call ___ipipe_disable_root_irqs_hw; \
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sp += 12; \
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(P5:0) = [sp++];
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# define CLI_INNER_NOP
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#else
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# define DO_CLI cli R3;
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# define CLI_INNER_NOP nop; nop; nop;
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#endif
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#ifdef CONFIG_IPIPE
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# define DO_STI \
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sp += -12; \
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call ___ipipe_enable_root_irqs_hw; \
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sp += 12; \
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2: rets = [sp++];
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#else
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# define DO_STI 2: sti R3;
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#endif
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#ifdef CONFIG_BFIN_INS_LOWOVERHEAD
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# define CLI_OUTER DO_CLI;
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# define STI_OUTER DO_STI;
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# define CLI_INNER 1:
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# if ANOMALY_05000416
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# define STI_INNER nop; 2: nop;
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# else
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# define STI_INNER 2:
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# endif
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#else
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# define CLI_OUTER
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# define STI_OUTER
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# define CLI_INNER 1: DO_CLI; CLI_INNER_NOP;
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# define STI_INNER DO_STI;
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#endif
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/*
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* Reads on the Blackfin are speculative. In Blackfin terms, this means they
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* can be interrupted at any time (even after they have been issued on to the
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* external bus), and re-issued after the interrupt occurs.
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*
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* If a FIFO is sitting on the end of the read, it will see two reads,
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* when the core only sees one. The FIFO receives the read which is cancelled,
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* and not delivered to the core.
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*
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* To solve this, interrupts are turned off before reads occur to I/O space.
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* There are 3 versions of all these functions
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* - turns interrupts off every read (higher overhead, but lower latency)
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* - turns interrupts off every loop (low overhead, but longer latency)
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* - DMA version, which do not suffer from this issue. DMA versions have
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* different name (prefixed by dma_ ), and are located in
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* ../kernel/bfin_dma.c
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* Using the dma related functions are recommended for transferring large
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* buffers in/out of FIFOs.
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*/
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#define COMMON_INS(func, ops) \
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ENTRY(_ins##func) \
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P0 = R0; /* P0 = port */ \
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CLI_OUTER; /* 3 instructions before first read access */ \
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P1 = R1; /* P1 = address */ \
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P2 = R2; /* P2 = count */ \
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SSYNC; \
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\
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LSETUP(1f, 2f) LC0 = P2; \
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CLI_INNER; \
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ops; \
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STI_INNER; \
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\
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STI_OUTER; \
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RTS; \
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ENDPROC(_ins##func)
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COMMON_INS(l, \
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R0 = [P0]; \
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[P1++] = R0; \
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)
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COMMON_INS(w, \
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R0 = W[P0]; \
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W[P1++] = R0; \
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)
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COMMON_INS(w_8, \
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R0 = W[P0]; \
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B[P1++] = R0; \
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R0 = R0 >> 8; \
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B[P1++] = R0; \
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)
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COMMON_INS(b, \
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R0 = B[P0]; \
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B[P1++] = R0; \
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)
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COMMON_INS(l_16, \
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R0 = [P0]; \
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W[P1++] = R0; \
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R0 = R0 >> 16; \
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W[P1++] = R0; \
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)
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