/*
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* Copyright 2005-2010 Analog Devices Inc.
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*
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* Licensed under the GPL-2 or later.
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*/
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#ifndef _MACH_COMMON_PLL_H
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#define _MACH_COMMON_PLL_H
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#ifndef __ASSEMBLY__
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#include <asm/blackfin.h>
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#include <asm/irqflags.h>
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#ifndef bfin_iwr_restore
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static inline void
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bfin_iwr_restore(unsigned long iwr0, unsigned long iwr1, unsigned long iwr2)
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{
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#ifdef SIC_IWR
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bfin_write_SIC_IWR(iwr0);
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#else
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bfin_write_SIC_IWR0(iwr0);
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# ifdef SIC_IWR1
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bfin_write_SIC_IWR1(iwr1);
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# endif
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# ifdef SIC_IWR2
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bfin_write_SIC_IWR2(iwr2);
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# endif
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#endif
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}
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#endif
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#ifndef bfin_iwr_save
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static inline void
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bfin_iwr_save(unsigned long niwr0, unsigned long niwr1, unsigned long niwr2,
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unsigned long *iwr0, unsigned long *iwr1, unsigned long *iwr2)
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{
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#ifdef SIC_IWR
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*iwr0 = bfin_read_SIC_IWR();
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#else
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*iwr0 = bfin_read_SIC_IWR0();
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# ifdef SIC_IWR1
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*iwr1 = bfin_read_SIC_IWR1();
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# endif
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# ifdef SIC_IWR2
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*iwr2 = bfin_read_SIC_IWR2();
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# endif
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#endif
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bfin_iwr_restore(niwr0, niwr1, niwr2);
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}
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#endif
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static inline void _bfin_write_pll_relock(u32 addr, unsigned int val)
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{
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unsigned long flags, iwr0, iwr1, iwr2;
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if (val == bfin_read_PLL_CTL())
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return;
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flags = hard_local_irq_save();
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/* Enable the PLL Wakeup bit in SIC IWR */
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bfin_iwr_save(IWR_ENABLE(0), 0, 0, &iwr0, &iwr1, &iwr2);
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bfin_write16(addr, val);
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SSYNC();
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asm("IDLE;");
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bfin_iwr_restore(iwr0, iwr1, iwr2);
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hard_local_irq_restore(flags);
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}
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/* Writing to PLL_CTL initiates a PLL relock sequence */
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static inline void bfin_write_PLL_CTL(unsigned int val)
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{
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_bfin_write_pll_relock(PLL_CTL, val);
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}
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/* Writing to VR_CTL initiates a PLL relock sequence */
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static inline void bfin_write_VR_CTL(unsigned int val)
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{
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_bfin_write_pll_relock(VR_CTL, val);
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}
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#endif
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#endif
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