/*
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* Common Blackfin IRQ definitions (i.e. the CEC)
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*
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* Copyright 2005-2011 Analog Devices Inc.
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*
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* Licensed under the GPL-2 or later
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*/
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#ifndef _MACH_COMMON_IRQ_H_
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#define _MACH_COMMON_IRQ_H_
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/*
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* Core events interrupt source definitions
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*
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* Event Source Event Name
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* Emulation EMU 0 (highest priority)
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* Reset RST 1
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* NMI NMI 2
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* Exception EVX 3
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* Reserved -- 4
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* Hardware Error IVHW 5
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* Core Timer IVTMR 6
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* Peripherals IVG7 7
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* Peripherals IVG8 8
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* Peripherals IVG9 9
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* Peripherals IVG10 10
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* Peripherals IVG11 11
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* Peripherals IVG12 12
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* Peripherals IVG13 13
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* Softirq IVG14 14
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* System Call IVG15 15 (lowest priority)
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*/
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/* The ABSTRACT IRQ definitions */
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#define IRQ_EMU 0 /* Emulation */
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#define IRQ_RST 1 /* reset */
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#define IRQ_NMI 2 /* Non Maskable */
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#define IRQ_EVX 3 /* Exception */
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#define IRQ_UNUSED 4 /* - unused interrupt */
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#define IRQ_HWERR 5 /* Hardware Error */
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#define IRQ_CORETMR 6 /* Core timer */
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#define IVG7 7
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#define IVG8 8
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#define IVG9 9
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#define IVG10 10
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#define IVG11 11
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#define IVG12 12
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#define IVG13 13
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#define IVG14 14
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#define IVG15 15
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#define BFIN_IRQ(x) ((x) + IVG7)
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#define BFIN_SYSIRQ(x) ((x) - IVG7)
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#define NR_IRQS (NR_MACH_IRQS + NR_SPARE_IRQS)
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#endif
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