/*
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* Allwinner SoCs display driver.
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*
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* Copyright (C) 2016 Allwinner.
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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/**
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* All Winner Tech, All Right Reserved. 2014-2015 Copyright (c)
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*
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* File name : de_smbl_type.h
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*
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* Description : display engine 2.0 smbl struct declaration
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*
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* History : 2014/05/13 vito cheng v0.1 Initial version
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*
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*/
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#ifndef __DE_SMBL_TYPE_H__
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#define __DE_SMBL_TYPE_H__
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#include "de_rtmx.h"
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#define SMBL_FRAME_MASK 0x00000002
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/* 0x0: do SMBL in even frame;
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* 0x1, do SMBL in odd frame;
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* 0x2, do SMBL in all frames
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*/
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#define IEP_LH_INTERVAL_NUM 8
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#define IEP_LH_PWRSV_NUM 24
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union __imgehc_gnectl_reg_t {
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u32 dwval;
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struct {
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u32 en:1;
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u32 incsc_en:1;
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u32 r0:2;
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u32 coef_switch_en:1;
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u32 r1:3;
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u32 mod:2;
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u32 r2:21;
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u32 bist_en:1;
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} bits;
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};
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union __imgehc_drcsize_reg_t {
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u32 dwval;
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struct {
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u32 disp_w:13;
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u32 r0:3;
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u32 disp_h:13;
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u32 r1:3;
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} bits;
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};
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union __imgehc_drcctl_reg_t {
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u32 dwval;
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struct {
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u32 db_en:1;
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u32 r0:7;
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u32 win_en:1;
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u32 hsv_en:1;
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u32 r1:22;
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} bits;
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};
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union __imgehc_drc_set_reg_t {
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u32 dwval;
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struct {
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u32 lgc_abslumshf:1;
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u32 adjust_en:1;
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u32 r0:6;
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u32 lgc_abslumperval:8;
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u32 r1:16;
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} bits;
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};
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union __imgehc_drc_wp_reg0_t {
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u32 dwval;
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struct {
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u32 win_left:12;
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u32 r0:4;
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u32 win_top:12;
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u32 r1:4;
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} bits;
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};
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union __imgehc_drc_wp_reg1_t {
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u32 dwval;
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struct {
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u32 win_right:12;
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u32 r0:4;
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u32 win_bottom:12;
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u32 r1:4;
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} bits;
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};
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union __imgehc_lhctl_reg_t {
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u32 dwval;
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struct {
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u32 lh_rec_clr:1;
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u32 lh_mod:1;
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u32 r0:30;
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} bits;
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};
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union __imgehc_lhthr_reg0_t {
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u32 dwval;
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struct {
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u32 lh_thres_val1:8;
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u32 lh_thres_val2:8;
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u32 lh_thres_val3:8;
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u32 lh_thres_val4:8;
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} bits;
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};
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union __imgehc_lhthr_reg1_t {
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u32 dwval;
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struct {
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u32 lh_thres_val5:8;
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u32 lh_thres_val6:8;
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u32 lh_thres_val7:8;
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u32 r0:8;
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} bits;
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};
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union __imgehc_lhslum_reg_t {
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u32 dwval;
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struct {
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u32 lh_lum_data:32;
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} bits;
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};
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union __imgehc_lhscnt_reg_t {
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u32 dwval;
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struct {
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u32 lh_cnt_data:32;
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} bits;
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};
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union __imgehc_cscygcoff_reg_t {
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u32 dwval;
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struct {
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u32 csc_yg_coff:13;
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u32 r0:19;
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} bits;
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};
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union __imgehc_cscygcon_reg_t {
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u32 dwval;
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struct {
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u32 csc_yg_con:14;
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u32 r0:18;
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} bits;
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};
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union __imgehc_cscurcoff_reg_t {
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u32 dwval;
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struct {
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u32 csc_ur_coff:13;
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u32 r0:19;
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} bits;
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};
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union __imgehc_cscurcon_reg_t {
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u32 dwval;
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struct {
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u32 csc_ur_con:14;
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u32 r0:18;
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} bits;
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};
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union __imgehc_cscvbcoff_reg_t {
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u32 dwval;
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struct {
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u32 csc_vb_coff:13;
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u32 r0:19;
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} bits;
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};
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union __imgehc_cscvbcon_reg_t {
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u32 dwval;
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struct {
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u32 csc_vb_con:14;
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u32 r0:18;
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} bits;
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};
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union __imgehc_drcspacoff_reg_t {
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u32 dwval;
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struct {
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u32 spa_coff0:8;
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u32 spa_coff1:8;
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u32 spa_coff2:8;
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u32 r0:8;
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} bits;
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};
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union __imgehc_drcintcoff_reg_t {
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u32 dwval;
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struct {
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u32 inten_coff0:8;
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u32 inten_coff1:8;
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u32 inten_coff2:8;
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u32 inten_coff3:8;
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} bits;
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};
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union __imgehc_drclgcoff_reg_t {
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u32 dwval;
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struct {
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u32 lumagain_coff0:16;
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u32 lumagain_coff1:16;
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} bits;
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};
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struct __smbl_reg_t {
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union __imgehc_gnectl_reg_t gnectl; /* 0x00 */
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union __imgehc_drcsize_reg_t drcsize; /* 0x04 */
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u32 r0[2]; /* 0x08~0x0c */
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union __imgehc_drcctl_reg_t drcctl; /* 0x10 */
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u32 r1; /* 0x14 */
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union __imgehc_drc_set_reg_t drc_set; /* 0x18 */
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union __imgehc_drc_wp_reg0_t drc_wp0; /* 0x1c */
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union __imgehc_drc_wp_reg1_t drc_wp1; /* 0x20 */
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u32 r5[3]; /* 0x24~0x2c */
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union __imgehc_lhctl_reg_t lhctl; /* 0x30 */
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union __imgehc_lhthr_reg0_t lhthr0; /* 0x34 */
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union __imgehc_lhthr_reg1_t lhthr1; /* 0x38 */
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u32 r2; /* 0x3c */
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union __imgehc_lhslum_reg_t lhslum[8]; /* 0x40~0x5c */
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union __imgehc_lhscnt_reg_t lhscnt[8]; /* 0x0060 ~ 0x007c */
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union __imgehc_cscygcoff_reg_t incscycoff[3]; /* 0x80~0x88 */
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union __imgehc_cscygcon_reg_t incscycon; /* 0x8c */
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union __imgehc_cscurcoff_reg_t incscucoff[3]; /* 0x90~0x98 */
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union __imgehc_cscurcon_reg_t incscucon; /* 0x9c */
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union __imgehc_cscvbcoff_reg_t incscvcoff[3]; /* 0xa0~0xa8 */
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union __imgehc_cscvbcon_reg_t incscvcon; /* 0xac */
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u32 r6[4]; /* 0xb0~0xbc */
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union __imgehc_cscygcoff_reg_t cscrcoff[3]; /* 0xc0~0xc8 */
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union __imgehc_cscygcon_reg_t cscrcon; /* 0xcc */
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union __imgehc_cscurcoff_reg_t cscgcoff[3]; /* 0xd0~0xd8 */
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union __imgehc_cscurcon_reg_t cscgcon; /* 0xdc */
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union __imgehc_cscvbcoff_reg_t cscbcoff[3]; /* 0xe0~0xe8 */
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union __imgehc_cscvbcon_reg_t cscbcon; /* 0xec */
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union __imgehc_drcspacoff_reg_t drcspacoff[3]; /* 0xf0~0xf8 */
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u32 r4; /* 0xfc */
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union __imgehc_drcintcoff_reg_t drcintcoff[64]; /* 0x0100 ~ 0x01fc */
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union __imgehc_drclgcoff_reg_t drclgcoff[128]; /* 0x0200 ~ 0x03fc */
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};
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struct __smbl_status_t {
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unsigned int isenable;
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unsigned int runtime;
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unsigned int backlight;
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unsigned int dimming;
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unsigned char min_adj_index_hist[IEP_LH_PWRSV_NUM];
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unsigned int size; /* size = width*height/100 */
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};
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#endif
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