/*
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* Allwinner SoCs display driver.
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*
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* Copyright (C) 2016 Allwinner.
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#ifndef __DE_RTMX_TYPE_H__
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#define __DE_RTMX_TYPE_H__
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/* for global control */
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union __glb_ctl_reg_t {
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unsigned int dwval;
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struct {
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unsigned int rt_en:1;
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unsigned int r0:3;
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unsigned int finish_irq_en:1;
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unsigned int error_irq_en:1;
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unsigned int r1:2;
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unsigned int sync_rev:1;
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unsigned int flied_rev:1;
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unsigned int r2:2;
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unsigned int rtwb_port:2;
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unsigned int r3:18;
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} bits;
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};
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/* 0x0 */
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union __glb_status_reg_t {
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unsigned int dwval;
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struct {
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unsigned int finish_irq:1;
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unsigned int error_irq:1;
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unsigned int r0:2;
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unsigned int busy_status:1;
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unsigned int error_status:1;
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unsigned int r1:2;
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unsigned int even_odd_flag:1;
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unsigned int r2:23;
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} bits;
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};
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/* 0x4 */
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union __glb_dbuff_reg_t {
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unsigned int dwval;
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struct {
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unsigned int dbuff_rdy:1;
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unsigned int r0:31;
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} bits;
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};
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/* 0x8 */
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union __glb_size_reg_t {
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unsigned int dwval;
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struct {
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unsigned int width:13;
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unsigned int r0:3;
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unsigned int height:13;
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unsigned int r1:3;
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} bits;
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};
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/* 0xc */
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struct __glb_reg_t {
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union __glb_ctl_reg_t glb_ctl;
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union __glb_status_reg_t glb_status;
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union __glb_dbuff_reg_t glb_dbuff;
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union __glb_size_reg_t glb_size;
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};
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/* for video overlay */
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union __vi_lay_attr_reg_t {
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unsigned int dwval;
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struct {
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unsigned int lay_en:1;
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unsigned int alpmode:2;
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unsigned int r0:1;
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unsigned int lay_fcolor_en:1;
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unsigned int r1:3;
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unsigned int lay_fmt:5;
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unsigned int r2:2;
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unsigned int ui_sel:1;
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unsigned int alpctl:2;
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unsigned int r3:2;
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unsigned int brust:3;
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unsigned int lay_top_down:1;
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unsigned int alpha:8;
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} bits;
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};
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/* 0x0+N*0x30(N=0,1,2,3) */
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union __vi_lay_size_reg_t {
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unsigned int dwval;
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struct {
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unsigned int lay_width:13;
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unsigned int r0:3;
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unsigned int lay_height:13;
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unsigned int r1:3;
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} bits;
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};
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/* 0x4+N*0x30(N=0,1,2,3) */
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union __vi_lay_coor_reg_t {
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unsigned int dwval;
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struct {
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unsigned int lay_coorx:16;
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unsigned int lay_coory:16;
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} bits;
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};
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/* 0x8+N*0x30(N=0,1,2,3) */
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union __vi_lay_pitch_reg_t {
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unsigned int dwval;
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struct {
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unsigned int lay_pitch:32;
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} bits;
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};
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/* 0xc/0x010/0x014+N*0x30(N=0,1,2,3) */
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union __vi_lay_top_laddr_reg_t {
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unsigned int dwval;
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struct {
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unsigned int lay_top_laddr:32;
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} bits;
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};
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/* 0x018/0x01c/0x020+N*0x30(N=0,1,2,3) */
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union __vi_lay_bot_laddr_reg_t {
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unsigned int dwval;
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struct {
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unsigned int lay_bot_laddr:32;
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} bits;
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};
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/* 0x024/0x028/0x02c+N*0x30(N=0,1,2,3) */
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union __vi_lay_fcolor_reg_t {
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unsigned int dwval;
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struct {
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unsigned int lay_vb:8;
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unsigned int lay_ug:8;
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unsigned int lay_yr:8;
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unsigned int r0:8;
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} bits;
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};
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/* 0x0c0+N*0x4(N=0,1,2,3) */
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union __vi_lay_top_haddr_reg_t {
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unsigned int dwval;
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struct {
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unsigned int lay0_top_haddr:8;
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unsigned int lay1_top_haddr:8;
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unsigned int lay2_top_haddr:8;
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unsigned int lay3_top_haddr:8;
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} bits;
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};
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/* 0xd0~0x0xd8 */
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union __vi_lay_bot_haddr_reg_t {
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unsigned int dwval;
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struct {
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unsigned int lay0_bot_haddr:8;
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unsigned int lay1_bot_haddr:8;
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unsigned int lay2_bot_haddr:8;
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unsigned int lay3_bot_haddr:8;
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} bits;
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};
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/* 0xdc~0xe4 */
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union __vi_ovl_size_reg_t {
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unsigned int dwval;
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struct {
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unsigned int ovl_width:13;
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unsigned int r0:3;
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unsigned int ovl_height:13;
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unsigned int r1:3;
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} bits;
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};
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/* 0xe8~0xec */
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union __vi_hori_ds_reg_t {
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unsigned int dwval;
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struct {
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unsigned int m:14;
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unsigned int r0:2;
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unsigned int n:14;
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unsigned int r1:2;
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} bits;
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};
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/* 0xf0~0xf4 */
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union __vi_vert_ds_reg_t {
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unsigned int dwval;
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struct {
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unsigned int m:14;
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unsigned int r0:2;
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unsigned int n:14;
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unsigned int r1:2;
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} bits;
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};
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/* 0xf8~0xfc */
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struct __vi_lay_reg_t {
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union __vi_lay_attr_reg_t lay_attr;
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union __vi_lay_size_reg_t lay_size;
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union __vi_lay_coor_reg_t lay_coor;
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union __vi_lay_pitch_reg_t lay_pitch[3];
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union __vi_lay_top_laddr_reg_t lay_top_laddr[3];
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union __vi_lay_bot_laddr_reg_t lay_bot_laddr[3];
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};
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struct __vi_ovl_reg_t {
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struct __vi_lay_reg_t vi_lay_cfg[4];
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union __vi_lay_fcolor_reg_t vi_lay_fcolor[4];
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union __vi_lay_top_haddr_reg_t vi_lay_top_haddr[3];
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union __vi_lay_bot_haddr_reg_t vi_lay_bot_haddr[3];
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union __vi_ovl_size_reg_t vi_ovl_size[2];
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union __vi_hori_ds_reg_t vi_hori_ds[2];
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union __vi_vert_ds_reg_t vi_vert_ds[2];
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};
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/* for ui overlay */
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union __ui_lay_attr_reg_t {
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unsigned int dwval;
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struct {
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unsigned int lay_en:1;
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unsigned int lay_alpmod:2;
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unsigned int r0:1;
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unsigned int lay_fcolor_en:1;
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unsigned int r1:3;
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unsigned int lay_fmt:5;
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unsigned int r2:3;
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unsigned int lay_alpctl:2;
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unsigned int r3:5;
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unsigned int lay_top_down:1;
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unsigned int lay_alpha:8;
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} bits;
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};
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/* 0x0+N*0x20(N=0,1,2,3) */
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union __ui_lay_size_reg_t {
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unsigned int dwval;
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struct {
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unsigned int lay_width:13;
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unsigned int r0:3;
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unsigned int lay_height:13;
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unsigned int r1:3;
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} bits;
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};
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/* 0x4+N*0x20(N=0,1,2,3) */
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union __ui_lay_coor_reg_t {
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unsigned int dwval;
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struct {
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unsigned int lay_coorx:16;
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unsigned int lay_coory:16;
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} bits;
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};
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/* 0x8+N*0x20(N=0,1,2,3) */
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union __ui_lay_pitch_reg_t {
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unsigned int dwval;
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struct {
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unsigned int lay_pitch:32;
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} bits;
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};
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/* 0xc+N*0x20(N=0,1,2,3) */
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union __ui_lay_top_laddr_reg_t {
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unsigned int dwval;
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struct {
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unsigned int lay_top_laddr:32;
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} bits;
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};
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/* 0x10+N*0x20(N=0,1,2,3) */
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union __ui_lay_bot_laddr_reg_t {
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unsigned int dwval;
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struct {
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unsigned int lay_bot_laddr:32;
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} bits;
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};
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/* 0x14+N*0x20(N=0,1,2,3) */
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union __ui_lay_fcolor_reg_t {
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unsigned int dwval;
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struct {
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unsigned int lay_blue:8;
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unsigned int lay_green:8;
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unsigned int lay_red:8;
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unsigned int lay_alpha:8;
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} bits;
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};
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/* 0x18+N*0x20(N=0,1,2,3) */
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union __ui_lay_top_haddr_reg_t {
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unsigned int dwval;
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struct {
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unsigned int lay0_top_haddr:8;
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unsigned int lay1_top_haddr:8;
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unsigned int lay2_top_haddr:8;
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unsigned int lay3_top_haddr:8;
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} bits;
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};
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/* 0x80 */
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union __ui_lay_bot_haddr_reg_t {
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unsigned int dwval;
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struct {
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unsigned int lay0_bot_haddr:8;
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unsigned int lay1_bot_haddr:8;
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unsigned int lay2_bot_haddr:8;
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unsigned int lay3_bot_haddr:8;
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} bits;
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};
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/* 0x84 */
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union __ui_ovl_size_reg_t {
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unsigned int dwval;
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struct {
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unsigned int ovl_width:13;
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unsigned int r0:3;
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unsigned int ovl_height:13;
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unsigned int r1:3;
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} bits;
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};
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/* 0x88 */
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struct __ui_lay_reg_t {
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union __ui_lay_attr_reg_t lay_attr;
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union __ui_lay_size_reg_t lay_size;
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union __ui_lay_coor_reg_t lay_coor;
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union __ui_lay_pitch_reg_t lay_pitch;
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union __ui_lay_top_laddr_reg_t lay_top_laddr;
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union __ui_lay_bot_laddr_reg_t lay_bot_laddr;
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union __ui_lay_fcolor_reg_t lay_fcolor;
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unsigned int r0;
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};
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struct __ui_ovl_reg_t {
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struct __ui_lay_reg_t ui_lay_cfg[4];
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union __ui_lay_top_haddr_reg_t ui_lay_top_haddr;
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union __ui_lay_bot_haddr_reg_t ui_lay_bot_haddr;
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union __ui_ovl_size_reg_t ui_ovl_size;
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};
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/* for alpha blending */
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union __bld_fcolor_ctl_reg_t {
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unsigned int dwval;
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struct {
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unsigned int p0_fcolor_en:1;
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unsigned int p1_fcolor_en:1;
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unsigned int p2_fcolor_en:1;
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unsigned int p3_fcolor_en:1;
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unsigned int p4_fcolor_en:1;
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unsigned int r0:3;
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unsigned int p0_en:1;
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unsigned int p1_en:1;
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unsigned int p2_en:1;
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unsigned int p3_en:1;
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unsigned int p4_en:1;
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unsigned int r1:19;
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} bits;
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};
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/* 0x0 */
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union __bld_fcolor_reg_t {
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unsigned int dwval;
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struct {
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unsigned int blue:8;
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unsigned int green:8;
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unsigned int red:8;
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unsigned int alpha:8;
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} bits;
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};
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/* 0x4+N*0x10(N=0,1,2,3,4) */
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union __bld_isize_reg_t {
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unsigned int dwval;
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struct {
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unsigned int width:13;
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unsigned int r0:3;
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unsigned int height:13;
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unsigned int r1:3;
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} bits;
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};
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/* 0x8+N*0x10(N=0,1,2,3,4) */
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union __bld_offset_reg_t {
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unsigned int dwval;
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struct {
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unsigned int coorx:16;
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unsigned int coory:13;
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} bits;
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};
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/* 0xc+N*0x10(N=0,1,2,3,4) */
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union __bld_route_ctl_reg_t {
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unsigned int dwval;
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struct {
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unsigned int ch0_routr_ctl:4;
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unsigned int ch1_routr_ctl:4;
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unsigned int ch2_routr_ctl:4;
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unsigned int ch3_routr_ctl:4;
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unsigned int ch4_routr_ctl:4;
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unsigned int r0:12;
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} bits;
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};
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union __bld_premultiply_ctl_reg_t {
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unsigned int dwval;
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struct {
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unsigned int p0_alpha_mode:1;
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unsigned int p1_alpha_mode:1;
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unsigned int p2_alpha_mode:1;
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unsigned int p3_alpha_mode:1;
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unsigned int p4_alpha_mode:1;
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unsigned int r0:27;
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} bits;
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};
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union __bld_bkcolor_reg_t {
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unsigned int dwval;
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struct {
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unsigned int blue:8;
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unsigned int green:8;
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unsigned int red:8;
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unsigned int alpha:8;
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} bits;
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};
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union __bld_output_size_reg_t {
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unsigned int dwval;
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struct {
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unsigned int width:13;
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unsigned int r0:3;
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unsigned int height:13;
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unsigned int r1:3;
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} bits;
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};
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union __bld_ctl_reg_t {
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unsigned int dwval;
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struct {
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unsigned int pixel_fs:4;
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unsigned int r0:4;
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unsigned int pixel_fd:4;
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unsigned int r1:4;
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unsigned int alpha_fs:4;
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unsigned int r2:4;
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unsigned int alpha_fd:4;
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unsigned int r3:4;
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} bits;
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};
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union __bld_colorkey_ctl_reg_t {
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unsigned int dwval;
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struct {
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unsigned int key0_en:1;
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unsigned int key0_dir:2;
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unsigned int r0:1;
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unsigned int key1_en:1;
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unsigned int key1_dir:2;
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unsigned int r1:1;
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unsigned int key2_en:1;
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unsigned int key2_dir:2;
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unsigned int r2:1;
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unsigned int key3_en:1;
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unsigned int key3_dir:2;
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unsigned int r3:17;
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} bits;
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};
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union __bld_colorkey_cfg_reg_t {
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unsigned int dwval;
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struct {
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unsigned int key0_blue:1;
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unsigned int key0_green:1;
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unsigned int key0_red:1;
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unsigned int r0:5;
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unsigned int key1_blue:1;
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unsigned int key1_green:1;
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unsigned int key1_red:1;
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unsigned int r1:5;
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unsigned int key2_blue:1;
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unsigned int key2_green:1;
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unsigned int key2_red:1;
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unsigned int r2:5;
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unsigned int key3_blue:1;
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unsigned int key3_green:1;
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unsigned int key3_red:1;
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unsigned int r3:5;
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} bits;
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};
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union __bld_colorkey_max_reg_t {
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unsigned int dwval;
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struct {
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unsigned int max_blue:8;
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unsigned int max_green:8;
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unsigned int max_red:8;
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unsigned int r0:8;
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} bits;
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};
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union __bld_colorkey_min_reg_t {
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unsigned int dwval;
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struct {
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unsigned int min_blue:8;
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unsigned int min_green:8;
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unsigned int min_red:8;
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unsigned int r0:8;
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} bits;
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};
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union __bld_out_color_ctl_reg_t {
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unsigned int dwval;
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struct {
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unsigned int premultiply_en:1;
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unsigned int interlace_en:1;
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unsigned int r0:30;
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} bits;
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};
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struct __bld_pipe_reg_t {
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union __bld_fcolor_reg_t fcolor;
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union __bld_isize_reg_t insize;
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union __bld_offset_reg_t offset;
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unsigned int r0;
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};
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struct __bld_reg_t {
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union __bld_fcolor_ctl_reg_t bld_fcolor_ctl;
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struct __bld_pipe_reg_t bld_pipe_attr[5];
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unsigned int r0[11];
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union __bld_route_ctl_reg_t bld_route_ctl;
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union __bld_premultiply_ctl_reg_t bld_premultiply_ctl;
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union __bld_bkcolor_reg_t bld_bkcolor;
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union __bld_output_size_reg_t bld_output_size;
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union __bld_ctl_reg_t bld_mode[4];
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unsigned int r1[4];
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union __bld_colorkey_ctl_reg_t bld_ck_ctl;
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union __bld_colorkey_cfg_reg_t bld_ck_cfg;
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unsigned int r2[2];
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union __bld_colorkey_max_reg_t bld_ck_max[4];
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unsigned int r3[4];
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union __bld_colorkey_min_reg_t bld_ck_min[4];
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unsigned int r4[3];
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union __bld_out_color_ctl_reg_t bld_out_ctl;
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};
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struct __rtmx_reg_t {
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struct __glb_reg_t *glb_ctl;
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struct __bld_reg_t *bld_ctl;
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struct __vi_ovl_reg_t *vi_ovl[VI_CHN_NUM];
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struct __ui_ovl_reg_t *ui_ovl[UI_CHN_NUM];
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};
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#endif
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