/*
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* drivers/video/sunxi/disp2/disp/de/lowlevel_v2x/de_lcd.h
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*
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* Copyright (c) 2007-2019 Allwinnertech Co., Ltd.
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* Author: zhengxiaobin <zhengxiaobin@allwinnertech.com>
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef __DE_LCD_H_
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#define __DE_LCD_H_
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#include "../include.h"
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#include "de_feat.h"
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enum __lcd_irq_id_t {
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LCD_IRQ_TCON0_VBLK = 15,
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LCD_IRQ_TCON1_VBLK = 14,
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LCD_IRQ_TCON0_LINE = 13,
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LCD_IRQ_TCON1_LINE = 12,
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LCD_IRQ_TCON0_TRIF = 11,
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LCD_IRQ_TCON0_CNTR = 10,
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LCD_IRQ_FSYNC_INT = 9,
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LCD_IRQ_DATA_EN_INT = 8,
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};
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enum __dsi_irq_id_t {
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DSI_IRQ_VIDEO_LINE = 3,
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DSI_IRQ_VIDEO_VBLK = 2,
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DSI_IRQ_INSTR_STEP = 1,
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DSI_IRQ_INSTR_END = 0,
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};
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enum __edp_irq_id_t {
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EDP_IRQ_VBLK = 0,
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EDP_IRQ_LINE1 = 1,
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};
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enum __lcd_src_t {
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LCD_SRC_DE = 0,
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LCD_SRC_COLOR_BAR = 1,
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LCD_SRC_GRAYSCALE = 2,
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LCD_SRC_BLACK_BY_WHITE = 3,
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LCD_SRC_BLACK = 4,
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LCD_SRC_WHITE = 5,
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LCD_SRC_GRID = 7,
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LCD_SRC_BLUE = 8
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};
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enum __tv_set_t {
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TV_TO_GPIO = 1,
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LCD_TO_GPIO = 0,
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TV_CLK_F_CCU = 0,
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TV_CLK_F_TVE = 1
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};
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enum __de_perh_t {
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LCD0 = 0,
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LCD1 = 1,
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TV0 = 2,
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TV1 = 3
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};
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s32 tcon0_out_to_gpio(u32 sel);
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s32 tcon1_out_to_gpio(u32 sel);
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s32 tcon1_tv_clk_enable(u32 sel, u32 en);
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s32 tcon1_hdmi_clk_enable(u32 sel, u32 en);
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s32 tcon0_dsi_clk_enable(u32 sel, u32 en);
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s32 tcon_de_attach(u32 tcon_index, u32 de_index);
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s32 tcon_get_attach_by_de_index(u32 de_index);
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s32 tcon_top_set_reg_base(u32 sel, uintptr_t base);
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uintptr_t tcon_top_get_reg_base(u32 sel);
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s32 lvds_open(u32 sel, disp_panel_para *panel);
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s32 lvds_close(u32 sel);
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u32 tcon_get_cur_field(u32 sel, u32 tcon_index);
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s32 tcon_irq_enable(u32 sel, enum __lcd_irq_id_t id);
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s32 tcon_irq_disable(u32 sel, enum __lcd_irq_id_t id);
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s32 tcon_set_reg_base(u32 sel, uintptr_t address);
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uintptr_t tcon_get_reg_base(u32 sel);
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s32 tcon_init(u32 sel);
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s32 tcon_exit(u32 sel);
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s32 tcon_get_timing(u32 sel, u32 index, struct disp_video_timings *tt);
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u32 tcon_irq_query(u32 sel, enum __lcd_irq_id_t id);
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u32 tcon_get_start_delay(u32 sel, u32 tcon_index);
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u32 tcon_get_cur_line(u32 sel, u32 tcon_index);
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s32 tcon_gamma(u32 sel, u32 en, u32 *gamma_tbl);
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s32 tcon_get_status(u32 sel, u32 tcon_index);
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s32 tcon0_cfg(u32 sel, disp_panel_para *panel);
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s32 tcon0_cfg_ext(u32 sel, panel_extend_para *extend_panel);
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s32 tcon0_src_select(u32 sel, enum __lcd_src_t src, u32 de_no);
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s32 tcon0_src_get(u32 sel);
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s32 tcon0_open(u32 sel, disp_panel_para *panel);
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s32 tcon0_close(u32 sel);
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s32 tcon0_set_dclk_div(u32 sel, u8 div);
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u32 tcon0_get_dclk_div(u32 sel);
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s32 tcon0_tri_busy(u32 sel);
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s32 tcon0_cpu_set_auto_mode(u32 sel);
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s32 tcon0_tri_start(u32 sel);
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u32 tcon0_cpu_16b_to_24b(u32 value);
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u32 tcon0_cpu_24b_to_16b(u32 value);
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u32 tcon0_cpu_busy(u32 sel);
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s32 tcon0_cpu_wr_24b(u32 sel, u32 index, u32 data);
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s32 tcon0_cpu_wr_24b_index(u32 sel, u32 index);
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s32 tcon0_cpu_wr_24b_data(u32 sel, u32 data);
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s32 tcon0_cpu_rd_24b(u32 sel, u32 index, u32 *data);
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s32 tcon0_cpu_rd_24b_data(u32 sel, u32 index, u32 *data, u32 size);
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s32 tcon0_cpu_wr_16b(u32 sel, u32 index, u32 data);
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s32 tcon0_cpu_wr_16b_index(u32 sel, u32 index);
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s32 tcon0_cpu_wr_16b_data(u32 sel, u32 data);
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s32 tcon0_cpu_rd_16b(u32 sel, u32 index, u32 *data);
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s32 tcon1_open(u32 sel);
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s32 tcon1_close(u32 sel);
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#ifdef TCON_POL_CORRECT
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u32 tcom1_cfg_correct(u32 sel, struct disp_video_timings *timing);
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#endif
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s32 tcon1_src_select(u32 sel, enum __lcd_src_t src, enum __de_perh_t de_no);
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s32 tcon1_src_get(u32 sel);
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s32 tcon1_cfg_ex(u32 sel, disp_panel_para *panel);
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s32 tcon1_set_timming(u32 sel, struct disp_video_timings *timming);
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s32 tcon1_cfg(u32 sel, struct disp_video_timings *timing);
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s32 tcon1_set_tv_mode(u32 sel, enum disp_output_type mode);
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s32 hmdi_src_sel(u32 sel);
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s32 tcon1_hdmi_color_remap(u32 sel, u32 onoff, u32 is_yuv);
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s32 tcon1_yuv_range(u32 sel, u32 onoff);
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u32 tcon0_get_cpu_tri2_start_delay(u32 sel);
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s32 rgb_src_sel(u32 src);
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s32 dsi_src_sel(u32 sel, u32 src);
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s32 tcon_set_sync_pol(u32 sel, u32 ver_pol, u32 hor_pol);
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/**
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* @name :tcon_fsync_set_pol
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* @brief :set fsync's polarity
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* @param[IN] :sel:tcon index
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* @param[IN] :pol:polarity. 1:positive;0:negetive
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* positive:
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* +---------+
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* ---------+ +-----------
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*
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* negative:
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* ---------+ +------------
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* +---------+
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*
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* @return :always 0
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*/
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s32 tcon_set_fsync_pol(u32 sel, u32 pol);
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/**
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* @name :tcon_set_fsync_active_time
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* @brief :set tcon fsync's active time
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* @param[IN] :sel:tcon index
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* @param[IN] :pixel_num:number of pixel time(Tpixel) to set
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*
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* Tpixel = 1/fps*1e9/vt/ht, unit:ns
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*
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* @return :0 if success
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*/
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s32 tcon_set_fsync_active_time(u32 sel, u32 pixel_num);
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#if defined(SUPPORT_DSI)
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extern __u32 dsi_pixel_bits[4];
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extern __u32 tcon_div;
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#endif
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extern s32 disp_delay_us(u32 us);
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extern s32 disp_delay_ms(u32 ms);
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extern int de_get_clk_rate(void);
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void tcon_show_builtin_patten(u32 sel, u32 patten);
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#endif
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