// SPDX-License-Identifier: GPL-2.0+
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/*
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* Meson GXL USB3 PHY driver
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*
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* Copyright (C) 2018 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
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* Copyright (C) 2018 BayLibre, SAS
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* Author: Neil Armstrong <narmstron@baylibre.com>
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <bitfield.h>
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#include <dm.h>
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#include <errno.h>
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#include <generic-phy.h>
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#include <regmap.h>
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#include <clk.h>
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#include <linux/bitops.h>
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#include <linux/compat.h>
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#include <linux/bitfield.h>
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#define USB_R0 0x00
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#define USB_R0_P30_FSEL_MASK GENMASK(5, 0)
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#define USB_R0_P30_PHY_RESET BIT(6)
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#define USB_R0_P30_TEST_POWERDOWN_HSP BIT(7)
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#define USB_R0_P30_TEST_POWERDOWN_SSP BIT(8)
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#define USB_R0_P30_ACJT_LEVEL_MASK GENMASK(13, 9)
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#define USB_R0_P30_TX_BOOST_LEVEL_MASK GENMASK(16, 14)
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#define USB_R0_P30_LANE0_TX2RX_LOOPBACK BIT(17)
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#define USB_R0_P30_LANE0_EXT_PCLK_REQ BIT(18)
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#define USB_R0_P30_PCS_RX_LOS_MASK_VAL_MASK GENMASK(28, 19)
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#define USB_R0_U2D_SS_SCALEDOWN_MODE_MASK GENMASK(30, 29)
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#define USB_R0_U2D_ACT BIT(31)
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#define USB_R1 0x04
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#define USB_R1_U3H_BIGENDIAN_GS BIT(0)
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#define USB_R1_U3H_PME_ENABLE BIT(1)
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#define USB_R1_U3H_HUB_PORT_OVERCURRENT_MASK GENMASK(6, 2)
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#define USB_R1_U3H_HUB_PORT_PERM_ATTACH_MASK GENMASK(11, 7)
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#define USB_R1_U3H_HOST_U2_PORT_DISABLE_MASK GENMASK(15, 12)
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#define USB_R1_U3H_HOST_U3_PORT_DISABLE BIT(16)
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#define USB_R1_U3H_HOST_PORT_POWER_CONTROL_PRESENT BIT(17)
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#define USB_R1_U3H_HOST_MSI_ENABLE BIT(18)
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#define USB_R1_U3H_FLADJ_30MHZ_REG_MASK GENMASK(24, 19)
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#define USB_R1_P30_PCS_TX_SWING_FULL_MASK GENMASK(31, 25)
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#define USB_R2 0x08
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#define USB_R2_P30_CR_DATA_IN_MASK GENMASK(15, 0)
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#define USB_R2_P30_CR_READ BIT(16)
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#define USB_R2_P30_CR_WRITE BIT(17)
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#define USB_R2_P30_CR_CAP_ADDR BIT(18)
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#define USB_R2_P30_CR_CAP_DATA BIT(19)
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#define USB_R2_P30_PCS_TX_DEEMPH_3P5DB_MASK GENMASK(25, 20)
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#define USB_R2_P30_PCS_TX_DEEMPH_6DB_MASK GENMASK(31, 26)
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#define USB_R3 0x0c
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#define USB_R3_P30_SSC_ENABLE BIT(0)
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#define USB_R3_P30_SSC_RANGE_MASK GENMASK(3, 1)
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#define USB_R3_P30_SSC_REF_CLK_SEL_MASK GENMASK(12, 4)
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#define USB_R3_P30_REF_SSP_EN BIT(13)
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#define USB_R3_P30_LOS_BIAS_MASK GENMASK(18, 16)
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#define USB_R3_P30_LOS_LEVEL_MASK GENMASK(23, 19)
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#define USB_R3_P30_MPLL_MULTIPLIER_MASK GENMASK(30, 24)
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#define USB_R4 0x10
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#define USB_R4_P21_PORT_RESET_0 BIT(0)
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#define USB_R4_P21_SLEEP_M0 BIT(1)
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#define USB_R4_MEM_PD_MASK GENMASK(3, 2)
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#define USB_R4_P21_ONLY BIT(4)
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#define USB_R5 0x14
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#define USB_R5_ID_DIG_SYNC BIT(0)
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#define USB_R5_ID_DIG_REG BIT(1)
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#define USB_R5_ID_DIG_CFG_MASK GENMASK(3, 2)
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#define USB_R5_ID_DIG_EN_0 BIT(4)
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#define USB_R5_ID_DIG_EN_1 BIT(5)
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#define USB_R5_ID_DIG_CURR BIT(6)
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#define USB_R5_ID_DIG_IRQ BIT(7)
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#define USB_R5_ID_DIG_TH_MASK GENMASK(15, 8)
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#define USB_R5_ID_DIG_CNT_MASK GENMASK(23, 16)
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/* read-only register */
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#define USB_R6 0x18
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#define USB_R6_P30_CR_DATA_OUT_MASK GENMASK(15, 0)
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#define USB_R6_P30_CR_ACK BIT(16)
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struct phy_meson_gxl_usb3_priv {
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struct regmap *regmap;
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#if CONFIG_IS_ENABLED(CLK)
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struct clk clk;
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#endif
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};
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static int
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phy_meson_gxl_usb3_set_host_mode(struct phy_meson_gxl_usb3_priv *priv)
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{
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uint val;
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regmap_read(priv->regmap, USB_R0, &val);
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val &= ~USB_R0_U2D_ACT;
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regmap_write(priv->regmap, USB_R0, val);
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regmap_read(priv->regmap, USB_R4, &val);
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val &= ~USB_R4_P21_SLEEP_M0;
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regmap_write(priv->regmap, USB_R4, val);
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return 0;
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}
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static int phy_meson_gxl_usb3_power_on(struct phy *phy)
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{
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struct udevice *dev = phy->dev;
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struct phy_meson_gxl_usb3_priv *priv = dev_get_priv(dev);
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uint val;
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regmap_read(priv->regmap, USB_R5, &val);
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val |= USB_R5_ID_DIG_EN_0;
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val |= USB_R5_ID_DIG_EN_1;
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val &= ~USB_R5_ID_DIG_TH_MASK;
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val |= FIELD_PREP(USB_R5_ID_DIG_TH_MASK, 0xff);
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regmap_write(priv->regmap, USB_R5, val);
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return phy_meson_gxl_usb3_set_host_mode(priv);
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}
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static int phy_meson_gxl_usb3_power_off(struct phy *phy)
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{
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struct udevice *dev = phy->dev;
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struct phy_meson_gxl_usb3_priv *priv = dev_get_priv(dev);
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uint val;
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regmap_read(priv->regmap, USB_R5, &val);
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val &= ~USB_R5_ID_DIG_EN_0;
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val &= ~USB_R5_ID_DIG_EN_1;
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regmap_write(priv->regmap, USB_R5, val);
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return 0;
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}
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static int phy_meson_gxl_usb3_init(struct phy *phy)
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{
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struct udevice *dev = phy->dev;
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struct phy_meson_gxl_usb3_priv *priv = dev_get_priv(dev);
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uint val;
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regmap_read(priv->regmap, USB_R1, &val);
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val &= ~USB_R1_U3H_FLADJ_30MHZ_REG_MASK;
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val |= FIELD_PREP(USB_R1_U3H_FLADJ_30MHZ_REG_MASK, 0x20);
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regmap_write(priv->regmap, USB_R1, val);
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return 0;
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}
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struct phy_ops meson_gxl_usb3_phy_ops = {
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.init = phy_meson_gxl_usb3_init,
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.power_on = phy_meson_gxl_usb3_power_on,
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.power_off = phy_meson_gxl_usb3_power_off,
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};
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int meson_gxl_usb3_phy_probe(struct udevice *dev)
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{
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struct phy_meson_gxl_usb3_priv *priv = dev_get_priv(dev);
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int ret;
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ret = regmap_init_mem(dev, &priv->regmap);
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if (ret)
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return ret;
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#if CONFIG_IS_ENABLED(CLK)
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ret = clk_get_by_index(dev, 0, &priv->clk);
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if (ret < 0)
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return ret;
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ret = clk_enable(&priv->clk);
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if (ret && ret != -ENOSYS && ret != -ENOTSUPP) {
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pr_err("failed to enable PHY clock\n");
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clk_free(&priv->clk);
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return ret;
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}
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#endif
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return 0;
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}
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static const struct udevice_id meson_gxl_usb3_phy_ids[] = {
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{ .compatible = "amlogic,meson-gxl-usb3-phy" },
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{ }
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};
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U_BOOT_DRIVER(meson_gxl_usb3_phy) = {
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.name = "meson_gxl_usb3_phy",
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.id = UCLASS_PHY,
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.of_match = meson_gxl_usb3_phy_ids,
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.probe = meson_gxl_usb3_phy_probe,
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.ops = &meson_gxl_usb3_phy_ops,
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.priv_auto_alloc_size = sizeof(struct phy_meson_gxl_usb3_priv),
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};
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