/*
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* (C) Copyright 2007-2013
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* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
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* Jerry Wang <wangflord@allwinnertech.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <malloc.h>
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#include <asm/arch/dma.h>
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#include <asm/arch/gic.h>
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#include <asm/arch/clock.h>
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#include <asm/io.h>
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#ifdef CONFIG_MACH_SUN8IW18
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#define SUNXI_DMA_MAX 10
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#else
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#define SUNXI_DMA_MAX 4
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#endif
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static int dma_int_cnt = 0;
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static int dma_init = -1;
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static sunxi_dma_source dma_channal_source[SUNXI_DMA_MAX];
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static void sunxi_dma_reg_func(void *p)
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{
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int i;
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uint pending;
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sunxi_dma_reg *dma_reg = (sunxi_dma_reg *)SUNXI_DMA_BASE;
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for (i = 0; i < 8 && i < SUNXI_DMA_MAX; i++) {
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pending = (DMA_PKG_END_INT << (i * 4));
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if (readl(&dma_reg->irq_pending0) & pending) {
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writel(pending, &dma_reg->irq_pending0);
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if (dma_channal_source[i].dma_func.m_func != NULL)
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dma_channal_source[i].dma_func.m_func(dma_channal_source[i].dma_func.m_data);
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}
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}
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for (i = 8; i < SUNXI_DMA_MAX; i++) {
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pending = (DMA_PKG_END_INT << ((i - 8) * 4));
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if (readl(&dma_reg->irq_pending1) & pending) {
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writel(pending, &dma_reg->irq_pending1);
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if (dma_channal_source[i].dma_func.m_func != NULL)
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dma_channal_source[i].dma_func.m_func(dma_channal_source[i].dma_func.m_data);
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}
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}
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}
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void sunxi_dma_init(void)
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{
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int i;
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sunxi_dma_reg *const dma_reg = (sunxi_dma_reg *)SUNXI_DMA_BASE;
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struct sunxi_ccm_reg *const ccm =
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(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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if (dma_init > 0)
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return ;
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#if defined(CONFIG_SUNXI_VERSION1)
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setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_DMA);
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setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_GATE_OFFSET_DMA);
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#else
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/* dma : mbus clock gating */
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setbits_le32(&ccm->mbus_gate, 1 << 0);
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/* dma reset */
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setbits_le32(&ccm->dma_gate_reset, 1 << DMA_RST_OFS);
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/* dma gating */
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setbits_le32(&ccm->dma_gate_reset, 1 << DMA_GATING_OFS);
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#endif
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writel(0, &dma_reg->irq_en0);
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writel(0, &dma_reg->irq_en0);
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writel(0xffffffff, &dma_reg->irq_pending0);
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writel(0xffffffff, &dma_reg->irq_pending1);
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/*auto MCLK gating disable*/
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clrsetbits_le32(&dma_reg->auto_gate, 0x7 << 0, 0x7 << 0);
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memset((void *)dma_channal_source, 0, SUNXI_DMA_MAX * sizeof(struct sunxi_dma_source_t));
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for (i = 0; i < SUNXI_DMA_MAX; i++) {
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dma_channal_source[i].used = 0;
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dma_channal_source[i].channal = &(dma_reg->channal[i]);
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dma_channal_source[i].desc =
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(sunxi_dma_desc *)malloc_align(sizeof(sunxi_dma_desc), CONFIG_SYS_CACHELINE_SIZE);
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}
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irq_install_handler(AW_IRQ_DMA, sunxi_dma_reg_func, 0);
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dma_int_cnt = 0;
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dma_init = 1;
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return ;
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}
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void sunxi_dma_exit(void)
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{
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int i;
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ulong hdma;
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sunxi_dma_reg *dma_reg = (sunxi_dma_reg *)SUNXI_DMA_BASE;
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struct sunxi_ccm_reg *const ccm =
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(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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/* free dma channal if other module not free it */
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for (i = 0; i < SUNXI_DMA_MAX; i++) {
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if (dma_channal_source[i].used == 1) {
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hdma = (ulong)&dma_channal_source[i];
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sunxi_dma_disable_int(hdma);
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sunxi_dma_free_int(hdma);
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writel(0, &dma_channal_source[i].channal->enable);
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dma_channal_source[i].used = 0;
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}
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}
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/* irq disable */
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writel(0, &dma_reg->irq_en0);
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writel(0, &dma_reg->irq_en0);
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writel(0xffffffff, &dma_reg->irq_pending0);
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writel(0xffffffff, &dma_reg->irq_pending1);
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irq_free_handler(AW_IRQ_DMA);
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#if defined(CONFIG_SUNXI_VERSION1)
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clrbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_DMA);
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#else
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/* close dma clock when dma exit */
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clrbits_le32(&ccm->dma_gate_reset, 1 << DMA_GATING_OFS);
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#endif
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dma_init--;
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}
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ulong sunxi_dma_request_from_last(uint dmatype)
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{
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int i;
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for (i = SUNXI_DMA_MAX - 1; i >= 0; i--) {
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if (dma_channal_source[i].used == 0) {
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dma_channal_source[i].used = 1;
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dma_channal_source[i].channal_count = i;
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return (ulong)&dma_channal_source[i];
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}
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}
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return 0;
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}
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ulong sunxi_dma_request(uint dmatype)
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{
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int i;
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for (i = 0; i < SUNXI_DMA_MAX; i++) {
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if (dma_channal_source[i].used == 0) {
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dma_channal_source[i].used = 1;
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dma_channal_source[i].channal_count = i;
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return (ulong)&dma_channal_source[i];
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}
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}
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return 0;
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}
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int sunxi_dma_release(ulong hdma)
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{
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struct sunxi_dma_source_t *dma_source = (struct sunxi_dma_source_t *)hdma;
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if (!dma_source->used)
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return -1;
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sunxi_dma_disable_int(hdma);
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sunxi_dma_free_int(hdma);
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dma_source->used = 0;
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return 0;
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}
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int sunxi_dma_setting(ulong hdma, sunxi_dma_set *cfg)
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{
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uint commit_para;
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sunxi_dma_set *dma_set = cfg;
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sunxi_dma_source *dma_source = (sunxi_dma_source *)hdma;
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sunxi_dma_desc *desc = dma_source->desc;
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uint channal_addr = (uint)(&(dma_set->channal_cfg));
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if (!dma_source->used)
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return -1;
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if (dma_set->loop_mode)
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desc->link = (uint)(&dma_source->desc);
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else
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desc->link = SUNXI_DMA_LINK_NULL;
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commit_para = (dma_set->wait_cyc & 0xff);
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commit_para |= (dma_set->data_block_size & 0xff) << 8;
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writel(commit_para, &desc->commit_para);
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writel(readl(channal_addr), &desc->config);
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return 0;
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}
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int sunxi_dma_start(ulong hdma, uint saddr, uint daddr, uint bytes)
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{
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sunxi_dma_source *dma_source = (sunxi_dma_source *)hdma;
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sunxi_dma_channal_reg *channal = dma_source->channal;
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sunxi_dma_desc *desc = dma_source->desc;
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if (!dma_source->used)
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return -1;
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/*config desc */
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writel(saddr, &desc->source_addr);
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writel(daddr, &desc->dest_addr);
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writel(bytes, &desc->byte_count);
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flush_cache((ulong)desc,
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ALIGN(sizeof(sunxi_dma_desc), CONFIG_SYS_CACHELINE_SIZE));
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/* start dma */
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writel((uint)(desc), &channal->desc_addr);
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writel(1, &channal->enable);
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return 0;
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}
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int sunxi_dma_stop(ulong hdma)
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{
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sunxi_dma_source *dma_source = (sunxi_dma_source *)hdma;
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sunxi_dma_channal_reg *channal = dma_source->channal;
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if (!dma_source->used)
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return -1;
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writel(0, &channal->enable);
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return 0;
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}
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int sunxi_dma_querystatus(ulong hdma)
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{
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uint channal_count;
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sunxi_dma_source *dma_source = (sunxi_dma_source *)hdma;
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sunxi_dma_reg *dma_reg = (sunxi_dma_reg *)SUNXI_DMA_BASE;
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if (!dma_source->used)
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return -1;
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channal_count = dma_source->channal_count;
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return (readl(&dma_reg->status) >> channal_count) & 0x01;
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}
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int sunxi_dma_install_int(ulong hdma, interrupt_handler_t dma_reg_func, void *p)
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{
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sunxi_dma_source *dma_channal = (sunxi_dma_source *)hdma;
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sunxi_dma_reg *dma_reg = (sunxi_dma_reg *)SUNXI_DMA_BASE;
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uint channal_count;
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if (!dma_channal->used)
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return -1;
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channal_count = dma_channal->channal_count;
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if (channal_count < 8)
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writel((7 << channal_count * 4), &dma_reg->irq_pending0);
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else
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writel((7 << (channal_count - 8) * 4), &dma_reg->irq_pending1);
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if (!dma_channal->dma_func.m_func) {
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dma_channal->dma_func.m_func = dma_reg_func;
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dma_channal->dma_func.m_data = p;
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} else {
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printf("dma 0x%lx int is used already, you have to free it first\n", hdma);
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}
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return 0;
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}
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int sunxi_dma_enable_int(ulong hdma)
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{
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sunxi_dma_source *dma_channal = (sunxi_dma_source *)hdma;
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sunxi_dma_reg *dma_status = (sunxi_dma_reg *)SUNXI_DMA_BASE;
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uint channal_count;
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if (!dma_channal->used)
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return -1;
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channal_count = dma_channal->channal_count;
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if (channal_count < 8) {
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if (readl(&dma_status->irq_en0) & (DMA_PKG_END_INT << channal_count * 4)) {
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printf("dma 0x%lx int is avaible already\n", hdma);
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return 0;
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}
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setbits_le32(&dma_status->irq_en0, (DMA_PKG_END_INT << channal_count * 4));
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} else {
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if (readl(&dma_status->irq_en1) & (DMA_PKG_END_INT << (channal_count - 8) * 4)) {
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printf("dma 0x%lx int is avaible already\n", hdma);
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return 0;
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}
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setbits_le32(&dma_status->irq_en1, (DMA_PKG_END_INT << (channal_count - 8) * 4));
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}
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if (!dma_int_cnt)
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irq_enable(AW_IRQ_DMA);
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dma_int_cnt ++;
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return 0;
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}
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int sunxi_dma_disable_int(ulong hdma)
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{
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sunxi_dma_source *dma_channal = (sunxi_dma_source *)hdma;
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sunxi_dma_reg *dma_reg = (sunxi_dma_reg *)SUNXI_DMA_BASE;
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uint channal_count;
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if (!dma_channal->used)
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return -1;
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channal_count = dma_channal->channal_count;
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if (channal_count < 8) {
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if (!(readl(&dma_reg->irq_en0) & (DMA_PKG_END_INT << channal_count * 4))) {
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debug("dma 0x%lx int is not used yet\n", hdma);
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return 0;
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}
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clrbits_le32(&dma_reg->irq_en0, (DMA_PKG_END_INT << channal_count * 4));
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} else {
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if (!(readl(dma_reg->irq_en1) & (DMA_PKG_END_INT << (channal_count - 8) * 4))) {
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debug("dma 0x%lx int is not used yet\n", hdma);
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return 0;
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}
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clrbits_le32(&dma_reg->irq_en1, (DMA_PKG_END_INT << (channal_count - 8) * 4));
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}
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//disable golbal int
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if (dma_int_cnt > 0)
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dma_int_cnt --;
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if (!dma_int_cnt)
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irq_disable(AW_IRQ_DMA);
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return 0;
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}
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int sunxi_dma_free_int(ulong hdma)
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{
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sunxi_dma_source *dma_channal = (sunxi_dma_source *)hdma;
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sunxi_dma_reg *dma_status = (sunxi_dma_reg *)SUNXI_DMA_BASE;
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uint channal_count;
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if (!dma_channal->used)
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return -1;
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channal_count = dma_channal->channal_count;
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if (channal_count < 8)
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writel((7 << channal_count), &dma_status->irq_pending0);
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else
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writel((7 << (channal_count - 8)), &dma_status->irq_pending1);
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if (dma_channal->dma_func.m_func) {
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dma_channal->dma_func.m_func = NULL;
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dma_channal->dma_func.m_data = NULL;
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} else {
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debug("dma 0x%lx int is free, you do not need to free it again\n", hdma);
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return -1;
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}
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return 0;
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}
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