/*
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* arch/arm/mach-sun6i/arisc/arisc_i.h
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*
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* Copyright (c) 2012 Allwinner.
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* 2012-05-01 Written by sunny (sunny@allwinnertech.com).
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* 2012-10-01 Written by superm (superm@allwinnertech.com).
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program;
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*/
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#ifndef __ARISC_I_H__
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#define __ARISC_I_H__
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#include <common.h>
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#include <fdt_support.h>
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#include <fdtdec.h>
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#include <linux/libfdt.h>
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#include <private_uboot.h>
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#include <linux/types.h>
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#include <linux/err.h>
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#include <asm/io.h>
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#include <linux/errno.h>
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#define ARISC_DVFS_VF_TABLE_MAX (16)
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#define IR_NUM_KEY_SUP 16
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/*
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* debug level define,
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* level 0 : dump debug information--none;
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* level 1 : dump debug information--error;
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* level 2 : dump debug information--error+warning;
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* level 3 : dump debug information--error+warning+information;
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* extern void printk(const char *, ...);
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*/
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#define ARISC_DEBUG_ON
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#ifdef ARISC_DEBUG_ON
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/* debug levels */
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#define DEBUG_LEVEL_INF ((u32)1 << 0)
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#define DEBUG_LEVEL_LOG ((u32)1 << 1)
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#define DEBUG_LEVEL_WRN ((u32)1 << 2)
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#define DEBUG_LEVEL_ERR ((u32)1 << 3)
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#define ARISC_INF(format, args...) \
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if (DEBUG_LEVEL_INF & (0xf0 >> (arisc_debug_level +1))) \
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pr_msg("[ARISC] :"format, ##args);
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#define ARISC_LOG(format, args...) \
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if (DEBUG_LEVEL_LOG & (0xf0 >> (arisc_debug_level +1))) \
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pr_msg("[ARISC] :"format, ##args);
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#define ARISC_WRN(format, args...) \
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if (DEBUG_LEVEL_WRN & (0xf0 >> (arisc_debug_level +1))) \
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pr_warning("[ARISC WARING] :"format, ##args);
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#define ARISC_ERR(format, args...) \
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if (DEBUG_LEVEL_ERR & (0xf0 >> (arisc_debug_level +1))) \
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pr_error("[ARISC ERROR] :"format, ##args);
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#else /* ARISC_DEBUG_ON */
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#define ARISC_INF(...)
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#define ARISC_WRN(...)
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#define ARISC_ERR(...)
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#define ARISC_LOG(...)
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#endif /* ARISC_DEBUG_ON */
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typedef struct mem_cfg {
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phys_addr_t base;
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size_t size;
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} mem_cfg_t;
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typedef struct mem_cfg_64 {
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u64 base;
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u64 size;
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} mem_cfg_64_t;
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typedef struct dev_cfg {
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phys_addr_t base;
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size_t size;
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u32 irq;
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int status;
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} dev_cfg_t;
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typedef struct dev_cfg_64 {
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u64 base;
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u64 size;
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u32 irq;
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int status;
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} dev_cfg_64_t;
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typedef struct ir_code {
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uint32_t key_code;
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uint32_t addr_code;
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} ir_code_t;
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typedef struct ir_key {
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uint32_t num;
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ir_code_t ir_code[IR_NUM_KEY_SUP];
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} ir_key_t;
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typedef struct cir_cfg {
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phys_addr_t base;
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size_t size;
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u32 irq;
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ir_key_t ir_key;
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int status;
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} cir_cfg_t;
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typedef struct cir_cfg_64 {
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u64 base;
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u64 size;
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u32 irq;
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ir_key_t ir_key;
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int status;
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} cir_cfg_64_t;
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typedef struct pmu_cfg {
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u32 pmu_bat_shutdown_ltf;
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u32 pmu_bat_shutdown_htf;
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u32 pmu_pwroff_vol;
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u32 power_start;
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} pmu_cfg_t;
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typedef struct box_start_os_cfg {
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u32 used;
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u32 start_type;
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u32 irkey_used;
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u32 pmukey_used;
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u32 pmukey_num;
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u32 led_power;
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u32 led_state;
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} box_start_os_cfg_t;
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typedef struct power_cfg {
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u32 powchk_used;
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u32 power_reg;
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u32 system_power;
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} power_cfg_t;
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typedef struct image_cfg {
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phys_addr_t base;
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size_t size;
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} image_cfg_t;
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typedef struct image_cfg_64 {
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u64 base;
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u64 size;
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} image_cfg_64_t;
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typedef struct space_cfg {
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phys_addr_t sram_dst;
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phys_addr_t sram_offset;
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size_t sram_size;
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phys_addr_t dram_dst;
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phys_addr_t dram_offset;
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size_t dram_size;
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phys_addr_t para_dst;
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phys_addr_t para_offset;
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size_t para_size;
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phys_addr_t msgpool_dst;
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phys_addr_t msgpool_offset;
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size_t msgpool_size;
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phys_addr_t standby_dst;
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phys_addr_t standby_offset;
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size_t standby_size;
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} space_cfg_t;
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typedef struct space_cfg_64 {
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u64 sram_dst;
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u64 sram_offset;
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u64 sram_size;
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u64 dram_dst;
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u64 dram_offset;
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u64 dram_size;
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u64 para_dst;
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u64 para_offset;
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u64 para_size;
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u64 msgpool_dst;
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u64 msgpool_offset;
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u64 msgpool_size;
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u64 standby_dst;
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u64 standby_offset;
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u64 standby_size;
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} space_cfg_64_t;
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typedef struct dram_para {
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//normal configuration
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u32 dram_clk;
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u32 dram_type; //dram_type DDR2: 2 DDR3: 3 LPDDR2: 6 DDR3L: 31
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u32 dram_zq;
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u32 dram_odt_en;
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//control configuration
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u32 dram_para1;
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u32 dram_para2;
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//timing configuration
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u32 dram_mr0;
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u32 dram_mr1;
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u32 dram_mr2;
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u32 dram_mr3;
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u32 dram_tpr0;
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u32 dram_tpr1;
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u32 dram_tpr2;
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u32 dram_tpr3;
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u32 dram_tpr4;
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u32 dram_tpr5;
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u32 dram_tpr6;
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//reserved for future use
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u32 dram_tpr7;
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u32 dram_tpr8;
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u32 dram_tpr9;
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u32 dram_tpr10;
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u32 dram_tpr11;
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u32 dram_tpr12;
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u32 dram_tpr13;
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} dram_para_t;
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typedef struct arisc_freq_voltage {
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u32 freq; //cpu frequency
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u32 voltage; //voltage for the frequency
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u32 axi_div; //the divide ratio of axi bus
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} arisc_freq_voltage_t;
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typedef struct dts_cfg {
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struct dram_para dram_para;
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struct arisc_freq_voltage vf[ARISC_DVFS_VF_TABLE_MAX];
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struct space_cfg space;
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struct image_cfg image;
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struct mem_cfg prcm;
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struct mem_cfg cpuscfg;
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struct dev_cfg msgbox;
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struct dev_cfg hwspinlock;
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struct dev_cfg s_uart;
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#if defined CONFIG_ARCH_SUN50IW2P1
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struct dev_cfg s_twi;
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#else
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struct dev_cfg s_rsb;
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#endif
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struct dev_cfg s_jtag;
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struct cir_cfg s_cir;
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struct pmu_cfg pmu;
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struct box_start_os_cfg start_os;
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struct power_cfg power;
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} dts_cfg_t;
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typedef struct dts_cfg_64 {
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struct dram_para dram_para;
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struct arisc_freq_voltage vf[ARISC_DVFS_VF_TABLE_MAX];
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struct space_cfg_64 space;
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struct image_cfg_64 image;
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struct mem_cfg_64 prcm;
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struct mem_cfg_64 cpuscfg;
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struct dev_cfg_64 msgbox;
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struct dev_cfg_64 hwspinlock;
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struct dev_cfg_64 s_uart;
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#if defined CONFIG_ARCH_SUN50IW2P1
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struct dev_cfg_64 s_twi;
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#else
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struct dev_cfg_64 s_rsb;
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#endif
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struct dev_cfg_64 s_jtag;
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struct cir_cfg_64 s_cir;
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struct pmu_cfg pmu;
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struct box_start_os_cfg start_os;
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struct power_cfg power;
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} dts_cfg_64_t;
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#endif //__ARISC_I_H__
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