/*
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* sound\soc\sunxi\sunxi_ahub.h
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* (C) Copyright 2015-2017
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* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
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* Wolfgang huang <huangjinhui@allwinnertechtech.com>
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*
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* some simple description for this code
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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*/
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#ifndef _SUNXI_AHUB_H_
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#define _SUNXI_AHUB_H_
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#include <linux/of_device.h>
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#include <linux/regmap.h>
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#include <linux/module.h>
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/* select pll_audiox4 as clock source */
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#if defined(CONFIG_ARCH_SUN50IW9)
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#define AHUB_PLL_AUDIO_X4
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#else
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#undef AHUB_PLL_AUDIO_X4
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#endif
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/* ahub loopback func for sun50iw9 */
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#if defined(CONFIG_ARCH_SUN50IW9)
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//#define LOOPBACK_FOR_DAUDIO
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//#else
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#undef LOOPBACK_FOR_DAUDIO
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#endif
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/* SUNXI Audio Hub registers list */
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#define SUNXI_AHUB_CTL 0x00
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#define SUNXI_AHUB_VER 0x04
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#define SUNXI_AHUB_RST 0x08
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#define SUNXI_AHUB_GAT 0x0c
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/* Left blank */
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#define SUNXI_AHUB_APBIF_TX_CTL(n) (0x10 + ((n) * 0x30))
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#define SUNXI_AHUB_APBIF_TX_IRQ_CTL(n) (0x14 + ((n) * 0x30))
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#define SUNXI_AHUB_APBIF_TX_IRQ_STA(n) (0x18 + ((n) * 0x30))
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/* Left Blank */
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#define SUNXI_AHUB_APBIF_TXFIFO_CTL(n) (0x20 + ((n) * 0x30))
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#define SUNXI_AHUB_APBIF_TXFIFO_STA(n) (0x24 + ((n) * 0x30))
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/* Left Blank */
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#define SUNXI_AHUB_APBIF_TXFIFO(n) (0x30 + ((n) * 0x30))
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#define SUNXI_AHUB_APBIF_TXFIFO_CNT(n) (0x34 + ((n) * 0x30))
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/* Left Blank */
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#define SUNXI_AHUB_APBIF_RX_CTL(n) (0x100 + ((n) * 0x30))
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#define SUNXI_AHUB_APBIF_RX_IRQ_CTL(n) (0x104 + ((n) * 0x30))
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#define SUNXI_AHUB_APBIF_RX_IRQ_STA(n) (0x108 + ((n) * 0x30))
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/* Left Blank */
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#define SUNXI_AHUB_APBIF_RXFIFO_CTL(n) (0x110 + ((n) * 0x30))
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#define SUNXI_AHUB_APBIF_RXFIFO_STA(n) (0x114 + ((n) * 0x30))
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#define SUNXI_AHUB_APBIF_RXFIFO_CONT(n) (0x118 + ((n) * 0x30))
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/* Left Blank */
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#define SUNXI_AHUB_APBIF_RXFIFO(n) (0x120 + ((n) * 0x30))
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#define SUNXI_AHUB_APBIF_RXFIFO_CNT(n) (0x124 + ((n) * 0x30))
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#define SUNXI_AHUB_I2S_CTL(n) (0x200 + ((n) << 8))
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#define SUNXI_AHUB_I2S_FMT0(n) (0x204 + ((n) << 8))
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#define SUNXI_AHUB_I2S_FMT1(n) (0x208 + ((n) << 8))
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#define SUNXI_AHUB_I2S_CLKD(n) (0x20c + ((n) << 8))
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/* Left Blank */
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#define SUNXI_AHUB_I2S_RXCONT(n) (0x220 + ((n) << 8))
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#define SUNXI_AHUB_I2S_CHCFG(n) (0x224 + ((n) << 8))
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#define SUNXI_AHUB_I2S_IRQ_CTL(n) (0x228 + ((n) << 8))
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#define SUNXI_AHUB_I2S_IRQ_STA(n) (0x22C + ((n) << 8))
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#define SUNXI_AHUB_I2S_OUT_SLOT0(n) (0x230 + ((n) << 8) + (0 << 4))
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#define SUNXI_AHUB_I2S_OUT_SLOT1(n) (0x230 + ((n) << 8) + (1 << 4))
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#define SUNXI_AHUB_I2S_OUT_SLOT2(n) (0x230 + ((n) << 8) + (2 << 4))
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#define SUNXI_AHUB_I2S_OUT_SLOT3(n) (0x230 + ((n) << 8) + (3 << 4))
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#define SUNXI_AHUB_I2S_OUT_CH0MAP0(n) (0x234 + ((n) << 8) + (0 << 4))
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#define SUNXI_AHUB_I2S_OUT_CH1MAP0(n) (0x234 + ((n) << 8) + (1 << 4))
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#define SUNXI_AHUB_I2S_OUT_CH2MAP0(n) (0x234 + ((n) << 8) + (2 << 4))
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#define SUNXI_AHUB_I2S_OUT_CH3MAP0(n) (0x234 + ((n) << 8) + (3 << 4))
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#define SUNXI_AHUB_I2S_OUT_CH0MAP1(n) (0x238 + ((n) << 8) + (0 << 4))
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#define SUNXI_AHUB_I2S_OUT_CH1MAP1(n) (0x238 + ((n) << 8) + (1 << 4))
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#define SUNXI_AHUB_I2S_OUT_CH2MAP1(n) (0x238 + ((n) << 8) + (2 << 4))
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#define SUNXI_AHUB_I2S_OUT_CH3MAP1(n) (0x238 + ((n) << 8) + (3 << 4))
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/* Left Blank */
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#define SUNXI_AHUB_I2S_IN_SLOT(n) (0x270 + ((n) << 8))
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#define SUNXI_AHUB_I2S_IN_CHMAP0(n) (0x274 + ((n) << 8))
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#define SUNXI_AHUB_I2S_IN_CHMAP1(n) (0x278 + ((n) << 8))
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/* Left Blank */
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#define SUNXI_AHUB_DAM_CTL(n) (0xA00 + ((n) << 7))
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/* Left Blank */
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#define SUNXI_AHUB_DAM_RX0_SRC(n) (0xA10 + ((n) << 7))
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#define SUNXI_AHUB_DAM_RX1_SRC(n) (0xA14 + ((n) << 7))
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#define SUNXI_AHUB_DAM_RX2_SRC(n) (0xA18 + ((n) << 7))
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/* Left Blank */
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#define SUNXI_AHUB_DAM_MIX_CTL0(n) (0xA30 + ((n) << 7))
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#define SUNXI_AHUB_DAM_MIX_CTL1(n) (0xA34 + ((n) << 7))
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#define SUNXI_AHUB_DAM_MIX_CTL2(n) (0xA38 + ((n) << 7))
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#define SUNXI_AHUB_DAM_MIX_CTL3(n) (0xA3C + ((n) << 7))
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#define SUNXI_AHUB_DAM_MIX_CTL4(n) (0xA40 + ((n) << 7))
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#define SUNXI_AHUB_DAM_MIX_CTL5(n) (0xA44 + ((n) << 7))
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#define SUNXI_AHUB_DAM_MIX_CTL6(n) (0xA48 + ((n) << 7))
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#define SUNXI_AHUB_DAM_MIX_CTL7(n) (0xA4C + ((n) << 7))
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#define SUNXI_AHUB_DAM_GAIN_CTL0(n) (0xA50 + ((n) << 7))
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#define SUNXI_AHUB_DAM_GAIN_CTL1(n) (0xA54 + ((n) << 7))
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#define SUNXI_AHUB_DAM_GAIN_CTL2(n) (0xA58 + ((n) << 7))
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#define SUNXI_AHUB_DAM_GAIN_CTL3(n) (0xA5C + ((n) << 7))
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#define SUNXI_AHUB_DAM_GAIN_CTL4(n) (0xA60 + ((n) << 7))
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#define SUNXI_AHUB_DAM_GAIN_CTL5(n) (0xA64 + ((n) << 7))
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#define SUNXI_AHUB_DAM_GAIN_CTL6(n) (0xA68 + ((n) << 7))
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#define SUNXI_AHUB_DAM_GAIN_CTL7(n) (0xA6C + ((n) << 7))
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/* SUNXI_AHUB_CTL */
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#define HDMI_SRC_SEL 0x04
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/* SUNXI_AHUB_RST */
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#define APBIF_TXDIF0_RST 31
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#define APBIF_TXDIF1_RST 30
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#define APBIF_TXDIF2_RST 29
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#define APBIF_RXDIF0_RST 27
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#define APBIF_RXDIF1_RST 26
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#define APBIF_RXDIF2_RST 25
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#define I2S0_RST 23
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#define I2S1_RST 22
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#define I2S2_RST 21
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#define I2S3_RST 20
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#define DAM0_RST 15
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#define DAM1_RST 14
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/* SUNXI_AHUB_GAT */
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#define APBIF_TXDIF0_GAT 31
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#define APBIF_TXDIF1_GAT 30
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#define APBIF_TXDIF2_GAT 29
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#define APBIF_RXDIF0_GAT 27
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#define APBIF_RXDIF1_GAT 26
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#define APBIF_RXDIF2_GAT 25
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#define I2S0_GAT 23
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#define I2S1_GAT 22
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#define I2S2_GAT 21
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#define I2S3_GAT 20
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#define DAM0_GAT 15
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#define DAM1_GAT 14
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/* SUNXI_AHUB_APBIF_TX_CTL */
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#define APBIF_TX_WS 16
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#define APBIF_TX_CHAN_NUM 8
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#define APBIF_TX_START 4
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/* SUNXI_AHUB_APBIF_TX_IRQ_CTL */
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#define APBIF_TX_DRQ 3
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#define APBIF_TX_OVEN 1
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#define APBIF_TX_EMEN 0
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/* SUNXI_AHUB_APBIF_TX_IRQ_STA */
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#define APBIF_TX_OV_PEND 1
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#define APBIF_TX_EM_PEND 0
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/* SUNXI_AHUB_APBIF_TXFIFO_CTL */
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#define APBIF_TX_FTX 12
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#define APBIF_TX_LEVEL 4
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#define APBIF_TX_TXIM 0
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/* SUNXI_AHUB_APBIF_TXFIFO_STA */
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#define APBIF_TX_EMPTY 8
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#define APBIF_TX_EMCNT 0
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/* SUNXI_AHUB_APBIF_RX_CTL */
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#define APBIF_RX_WS 16
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#define APBIF_RX_CHAN_NUM 8
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#define APBIF_RX_START 4
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/* SUNXI_AHUB_APBIF_RX_IRQ_CTL */
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#define APBIF_RX_DRQ 3
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#define APBIF_RX_UVEN 2
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#define APBIF_RX_AVEN 0
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/* SUNXI_AHUB_APBIF_RX_IRQ_STA */
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#define APBIF_RX_UV_PEND 1
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#define APBIF_RX_AV_PEND 0
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/* SUNXI_AHUB_APBIF_RXFIFO_CTL */
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#define APBIF_RX_FRX 12
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#define APBIF_RX_LEVEL 4
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#define APBIF_RX_RXOM 0
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/* SUNXI_AHUB_APBIF_RXFIFO_STA */
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#define APBIF_RX_AVAIL 8
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#define APBIF_RX_AVCNT 0
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/* SUNXI_AHUB_APBIF_RXFIFO_CONT */
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#define APBIF_RX_APBIF_TXDIF0 31
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#define APBIF_RX_APBIF_TXDIF1 30
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#define APBIF_RX_APBIF_TXDIF2 29
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#define APBIF_RX_I2S0_TXDIF 27
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#define APBIF_RX_I2S1_TXDIF 26
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#define APBIF_RX_I2S2_TXDIF 25
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#define APBIF_RX_I2S3_TXDIF 23
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#define APBIF_RX_DAM0_TXDIF 19
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#define APBIF_RX_DAM1_TXDIF 15
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/* SUNXI_AHUB_I2S_CTL */
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//sun50iw9 change loopback bit and SDI_EN
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#ifdef CONFIG_ARCH_SUN50IW9
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#define I2S_CTL_LOOP3 23
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#define I2S_CTL_LOOP2 22
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#define I2S_CTL_LOOP1 21
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#define I2S_CTL_LOOP0 20
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#define I2S_CTL_SDI3_EN 15
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#define I2S_CTL_SDI2_EN 14
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#define I2S_CTL_SDI1_EN 13
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#define I2S_CTL_SDI0_EN 12
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#else
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#define I2S_CTL_LOOP 3
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#endif
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#define I2S_CTL_CLK_OUT 18
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#define I2S_CTL_SDO3_EN 11
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#define I2S_CTL_SDO2_EN 10
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#define I2S_CTL_SDO1_EN 9
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#define I2S_CTL_SDO0_EN 8
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#define I2S_CTL_OUT_MUTE 6
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#define I2S_CTL_MODE 4
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#define I2S_CTL_TXEN 2
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#define I2S_CTL_RXEN 1
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#define I2S_CTL_GEN 0
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/* SUNXI_AHUB_I2S_FMT0 */
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#define I2S_FMT0_LRCK_WIDTH 30
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#define I2S_FMT0_LRCK_POLARITY 19
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#define I2S_FMT0_LRCK_PERIOD 8
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#define I2S_FMT0_BCLK_POLARITY 7
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#define I2S_FMT0_SR 4
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#define I2S_FMT0_EDGE 3
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#define I2S_FMT0_SW 0
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/* SUNXI_AHUB_I2S_FMT1 */
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#define I2S_FMT1_RX_LSB 7
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#define I2S_FMT1_TX_LSB 6
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#define I2S_FMT1_EXT 4
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#define I2S_FMT1_RX_PDM 2
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#define I2S_FMT1_TX_PDM 0
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/* SUNXI_AHUB_I2S_CLKD */
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#define I2S_CLKD_MCLK 8
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#define I2S_CLKD_BCLKDIV 4
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#define I2S_CLKD_MCLKDIV 0
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/* SUNXI_AHUB_I2S_RXCONT */
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#define I2S_RX_APBIF_TXDIF0 31
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#define I2S_RX_APBIF_TXDIF1 30
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#define I2S_RX_APBIF_TXDIF2 29
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#define I2S_RX_I2S0_TXDIF 27
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#define I2S_RX_I2S1_TXDIF 26
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#define I2S_RX_I2S2_TXDIF 25
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#define I2S_RX_I2S3_TXDIF 23
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#define I2S_RX_DAM0_TXDIF 19
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#define I2S_RX_DAM1_TXDIF 15
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/* SUNXI_AHUB_I2S_CHCFG */
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#define I2S_CHCFG_HIZ 9
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#define I2S_CHCFG_TX_STATE 8
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#define I2S_CHCFG_RX_CHANNUM 4
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#define I2S_CHCFG_TX_CHANNUM 0
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/* SUNXI_AHUB_I2S_IRQ_CTL */
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#define I2S_IRQ_RXOV_EN 1
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#define I2S_IRQ_TXUV_EN 0
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/* SUNXI_AHUB_I2S_IRQ_STA */
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#define I2S_IRQ_RXOV_PEND 1
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#define I2S_IRQ_TXUV_PEND 0
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/* SUNXI_AHUB_I2S_OUT_SLOT */
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#define I2S_OUT_OFFSET 20
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#define I2S_OUT_SLOT_NUM 16
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#define I2S_OUT_SLOT_EN 0
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/* SUNXI_AHUB_I2S_IN_SLOT */
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#define I2S_IN_OFFSET 20
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#define I2S_IN_SLOT_NUM 16
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/* SUNXI_AHUB_DAM_CTL */
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#define DAM_CTL_RX2_NUM 24
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#define DAM_CTL_RX1_NUM 20
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#define DAM_CTL_RX0_NUM 16
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#define DAM_CTL_TX_NUM 8
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#define DAM_CTL_RX2EN 6
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#define DAM_CTL_RX1EN 5
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#define DAM_CTL_RX0EN 4
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#define DAM_CTL_TXEN 0
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/* SUNXI_AHUB_DAM_RX##chan##_SRC */
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#define DAM_RX_APBIF_TXDIF0 31
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#define DAM_RX_APBIF_TXDIF1 30
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#define DAM_RX_APBIF_TXDIF2 29
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#define DAM_RX_I2S0_TXDIF 27
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#define DAM_RX_I2S1_TXDIF 26
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#define DAM_RX_I2S2_TXDIF 25
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#define DAM_RX_I2S3_TXDIF 23
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#define DAM_RX_DAM0_TXDIF 19
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#define DAM_RX_DAM1_TXDIF 15
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/* For sun50iw6, if others should redefine */
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#define SUNXI_AHUB_I2S0_ID 0
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#define SUNXI_AHUB_HDMI_ID 1
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#define SUNXI_AHUB_I2S2_ID 2
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#define SUNXI_AHUB_I2S3_ID 3
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extern struct regmap *sunxi_ahub_regmap_init(struct platform_device *pdev);
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extern unsigned int sunxi_ahub_read(unsigned int reg);
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extern int sunxi_ahub_update_bits(unsigned int reg, unsigned int mask,
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unsigned int val);
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extern int sunxi_ahub_cpudai_init(void);
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/* used for sunxi netlink to auto open others card */
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extern void sunxi_netlink_printd(const char *fmt, ...);
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#endif
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