/*
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* sound\soc\sunxi\sun8iw11codec.h
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* (C) Copyright 2014-2016
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* allwinner Technology Co., Ltd. <www.allwinnertech.com>
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* huangxin <huangxin@allwinnertech.com>
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*
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* some simple description for this code
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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*/
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#ifndef _SUN8IW11_CODEC_H
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#define _SUN8IW11_CODEC_H
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#define SUNXI_DAC_DPC 0x00
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#define SUNXI_DAC_FIFO_CTR 0x04
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#define SUNXI_DAC_FIFO_STA 0x08
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/* left blank */
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#define SUNXI_ADC_FIFO_CTR 0x10
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#define SUNXI_ADC_FIFO_STA 0x14
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#define SUNXI_ADC_RXDATA 0x18
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#define SUNXI_DAC_TXDATA 0x20
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/* left blank */
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#define SUNXI_DAC_CNT 0x40
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#define SUNXI_ADC_CNT 0x44
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#define SUNXI_DAC_DG 0x48
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#define SUNXI_ADC_DG 0x4C
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#define SUNXI_HMIC_CTRL 0x50
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#define SUNXI_HMIC_DATA 0x54
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/*left blank */
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#define SUNXI_DAC_DAP_CTR 0x60
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#define SUNXI_ADC_DAP_CTR 0x70
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#define SUNXI_ADC_DRC_HHPFC 0x200
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#define SUNXI_ADC_DRC_LHPFC 0x204
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/* Analog register base - Digital register base */
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#define SUNXI_PR_CFG 0x300
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#define SUNXI_HP_VOLC (SUNXI_PR_CFG + 0x00)
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#define SUNXI_LOMIX_SRC (SUNXI_PR_CFG + 0x01)
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#define SUNXI_ROMIX_SRC (SUNXI_PR_CFG + 0x02)
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#define SUNXI_DAC_PA_SRC (SUNXI_PR_CFG + 0x03)
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#define SUNXI_LINEIN_GCTR (SUNXI_PR_CFG + 0x04)
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#define SUNXI_FM_GCTR (SUNXI_PR_CFG + 0x05)
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#define SUNXI_MICIN_GCTR (SUNXI_PR_CFG + 0x06)
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#define SUNXI_PAEN_HP_CTR (SUNXI_PR_CFG + 0x07)
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#define SUNXI_PHONEOUT_CTR (SUNXI_PR_CFG + 0x08)
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/* left blank */
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#define SUNXI_MIC2G_LINEEN_CTR (SUNXI_PR_CFG + 0x0A)
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#define SUNXI_MIC1G_MICBIAS_CTR (SUNXI_PR_CFG + 0x0B)
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#define SUNXI_LADCMIX_SRC (SUNXI_PR_CFG + 0x0C)
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#define SUNXI_RADCMIX_SRC (SUNXI_PR_CFG + 0x0D)
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#define SUNXI_PA_POP_CTR (SUNXI_PR_CFG + 0x0E)
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#define SUNXI_ADC_AP_EN (SUNXI_PR_CFG + 0x0F)
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#define SUNXI_ADDA_APT0 (SUNXI_PR_CFG + 0x10)
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#define SUNXI_ADDA_APT1 (SUNXI_PR_CFG + 0x11)
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#define SUNXI_ADDA_APT2 (SUNXI_PR_CFG + 0x12)
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#define SUNXI_CHOP_CAL_CTR (SUNXI_PR_CFG + 0x13)
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#define SUNXI_BIAS_DA16_CAL_CTR (SUNXI_PR_CFG + 0x14)
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#define SUNXI_DA16_CALI_DATA (SUNXI_PR_CFG + 0x15)
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/* left blank */
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#define SUNXI_BIAS_CALI_DATA (SUNXI_PR_CFG + 0x17)
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#define SUNXI_BIAS_CALI_SET (SUNXI_PR_CFG + 0x18)
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/* SUNXI_DAC_DPC:0x00 */
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#define EN_DAC 31
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#define MODQU 25
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#define HPF_EN 18
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#define DVOL 12
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#define HUB_EN 0
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/* SUNXI_DAC_FIFO_CTR:0x04 */
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#define DAC_FS 29
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#define FIR_VER 28
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#define SEND_LASAT 26
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#define FIFO_MODE 24
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#define DAC_DRQ_CLR_CNT 21
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#define TX_TRIG_LEVEL 8
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#define ADDA_LOOP_EN 7
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#define DAC_MONO_EN 6
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#define TX_SAMPLE_BITS 5
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#define DAC_DRQ_EN 4
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#define DAC_IRQ_EN 3
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#define FIFO_UNDERRUN_IRQ_EN 2
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#define FIFO_OVERRUN_IRQ_EN 1
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#define FIFO_FLUSH 0
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/* SUNXI_DAC_FIFO_STA:0x08 */
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#define TX_EMPTY 23
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#define TXE_CNT 8
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#define TXE_INT 3
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#define TXU_INT 2
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#define TXO_INT 1
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/* SUNXI_ADC_FIFO_CTR:0x10 */
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#define ADC_FS 29
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#define EN_AD 28
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#define RX_FIFO_MODE 24
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#define ADCFDT 17
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#define ADCDFEN 16
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#define RX_FIFO_TRG_LEVEL 8
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#define ADC_MONO_EN 7
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#define RX_SAMPLE_BITS 6
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#define ADC_DRQ_EN 4
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#define ADC_IRQ_EN 3
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#define ADC_OVERRUN_IRQ_EN 1
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#define ADC_FIFO_FLUSH 0
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/* SUNXI_ADC_FIFO_STA:0x14 */
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#define RXA 23
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#define RXA_CNT 8
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#define RXA_INT 3
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#define RXO_INT 1
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/* SUNXI_HMIC_CTRL:0x50 */
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#define HMIC_M 28
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#define HMIC_N 24
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#define HMIC_DATA_IRQ_MODE 23
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#define HMIC_TH1_HYSTERESIS 21
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#define HMIC_PULLOUT_IRQ 20
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#define HMIC_PLUGIN_IRQ 19
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#define HMIC_KEYUP_IRQ 18
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#define HMIC_KEYDOWN_IRQ 17
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#define HMIC_DATA_IRQ_EN 16
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#define HMIC_SAMPLE_SELECT 14
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#define HMIC_TH2_HYSTERESIS 13
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#define HMIC_TH2 8
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#define HMIC_SF 6
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#define KEYUP_CLEAR 5
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#define HMIC_TH1 0
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/* SUNXI_HMIC_DATA:0x54 */
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#define HMIC_PULLOUT_PEND 20
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#define HMIC_PLUGIN_PEND 19
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#define HMIC_KEYUP_PEND 18
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#define HMIC_KEYDOWN_PEND 17
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#define HMIC_DATA_PEND 16
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#define HMIC_DATA 0
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/* SUNXI_DAC_DAP_CTR:0x60 */
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#define DDAP_EN 31
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#define DDAP_DRC_EN 15
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#define DDAP_HPF_EN 14
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#define RAM_ADDR 0
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/* SUNXI_ADC_DAP_CTR:0x70 */
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#define ENADC_DRC 26
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#define ADC_DRC_EN 25
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#define ADC_DRC_HPF_EN 24
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/*AC_ADC_DRC_HHPFC : 0x200*/
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#define ADC_HHPF_CONF 0
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/*AC_ADC_DRC_LHPFC : 0x204*/
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#define ADC_LHPF_CONF 0
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/* SUNXI_PR_CFG:0x300 */
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#define AC_PR_RST 28
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#define AC_PR_RW 24
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#define AC_PR_ADDR 16
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#define ADDA_PR_WDAT 8
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#define ADDA_PR_RDAT 0
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/* SUNXI_HP_VOLC:0x00 */
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#define PA_CLK_GATING 7
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#define HPVOL 0
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/* SUNXI_LOMIX_SRC:0x01 */
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#define LMIXMUTE 0
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#define LMIX_MIC1_BST 6
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#define LMIX_MIC2_BST 5
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#define LMIX_LINEINLR 4
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#define LMIX_LINEINL 3
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#define LMIX_FML 2
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#define LMIX_LDAC 1
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#define LMIX_RDAC 0
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/* SUNXI_ROMIX_SRC:0x02 */
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#define RMIXMUTE 0
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#define RMIX_MIC1_BST 6
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#define RMIX_MIC2_BST 5
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#define RMIX_LINEINLR 4
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#define RMIX_LINEINR 3
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#define RMIX_FMR 2
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#define RMIX_RDAC 1
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#define RMIX_LDAC 0
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/* SUNXI_DAC_PA_SRC:0x03 */
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#define DACAREN 7
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#define DACALEN 6
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#define RMIXEN 5
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#define LMIXEN 4
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#define RHPPAMUTE 3
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#define LHPPAMUTE 2
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#define RHPIS 1
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#define LHPIS 0
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/* SUNXI_LINEIN_GCTR:0x04 */
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#define LINEINLG 4
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#define LINEINRG 0
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/* SUNXI_FM_GCTR:0x05 */
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#define FMG 4
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#define LINEING 0
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/* SUNXI_MICIN_GCTR:0x06 */
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#define MIC1_GAIN 4
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#define MIC2_GAIN 0
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/* SUNXI_PAEN_HP_CTR:0x07 */
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#define HPPAEN 7
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#define HPCOM_FC 5
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#define HPCOM_PT 4
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#define PA_ANTI_POP_CTRL 2
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#define LTRNMUTE 1
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#define RTLNMUTE 0
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/* SUNXI_PHONEOUT_CTR:0x08 */
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#define PHONEOUTG 5
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#define PHONEOUTEN 4
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#define PHONEOUTS3 3
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#define PHONEOUTS2 2
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#define PHONEOUTS1 1
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#define PHONEOUTS0 0
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/* SUNXI_MIC2G_LINEEN_CTR:0x0A */
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#define MIC2AMPEN 7
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#define MIC2BOOST 4
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/* SUNXI_MIC1G_MICBIAS_CTR:0x0B */
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#define HMICBIASEN 7
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#define MMICBIASEN 6
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#define HMICBIASMODE 5
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#define MIC2_SS 4
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#define MIC1_AMPEN 3
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#define MIC1_BOOST 0
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/* SUNXI_LADCMIX_SRC:0x0C */
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#define LADCMIXMUTE 0
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#define LADC_MIC1_BST 6
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#define LADC_MIC2_BST 5
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#define LADC_LINEINLR 4
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#define LADC_LINEINL 3
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#define LADC_FML 2
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#define LADC_LOUT_MIX 1
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#define LADC_ROUT_MIX 0
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/* SUNXI_RADCMIX_SRC:0x0D */
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#define RADC_MIC1_BST 6
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#define RADC_MIC2_BST 5
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#define RADC_LINEINLR 4
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#define RADC_LINEINR 3
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#define RADC_FMR 2
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#define RADC_ROUT_MIX 1
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#define RADC_LOUT_MIX 0
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/* SUNXI_PA_POP_CTR:0x0E */
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#define PA_POP_CTRL 0
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/* SUNXI_ADC_AP_EN:0x0F */
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#define ADCREN 7
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#define ADCLEN 6
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#define ADCG 0
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/* SUNXI_ADDA_APT0:0x10 */
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#define OPDRV_OPCOM_CUR 6
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#define OPADC1_BIAS_CUR 4
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#define OPADC2_BIAS_CUR 2
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#define OPAAF_BIAS_CUR 0
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/* SUNXI_ADDA_APT1:0x11 */
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#define OPMIC_BIAS_CUR 6
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#define OPVR_BIAS_CUR 4
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#define OPDAC_BIAS_CUR 2
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#define OPMIX_BIAS_CUR 0
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/* SUNXI_ADDA_APT2:0x12 */
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#define ZERO_CROSS_EN 7
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#define ZERO_CROSS_TIMEOUT 6
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#define PTDBS 4
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#define PA_SLOPE_SELECT 3
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#define USB_BIAS_CUR 0
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/* SUNXI_CHOP_CAL_CTR:0x13 */
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#define MMIC_BIASCHOPEN 7
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#define MMIC_BIAS_CHOP_SRC 5
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#define DITHER 4
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#define DITHER_CLK_SEL 2
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#define BIHE_CTRL 0
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/* SUNXI_BIAS_DA16_CAL_CTR:0x14*/
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#define PA_SPEED_SELECT 7
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#define CUR_TEST_SEL 6
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#define BIAS_DA16_CLK_SEL 4
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#define BIAS_CAL_MODE_SEL 3
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#define BIAS_DA16_CAL_CTRL 2
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#define BIAS_CAL_VER 1
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#endif /* __SUN8IW11_CODEC_H */
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