/*
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* sound\soc\sunxi\sun50iw10-codec.h
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* (C) Copyright 2014-2019
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* allwinner Technology Co., Ltd. <www.allwinnertech.com>
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* yumingfeng <yumingfeng@allwinnertech.com>
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* luguofang <luguofang@allwinnertech.com>
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*
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* some simple description for this code
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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*/
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#ifndef _SUN50IW10_CODEC_H
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#define _SUN50IW10_CODEC_H
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#include "sunxi-pcm.h"
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#define SUNXI_DAC_DPC 0x00
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#define SUNXI_DAC_VOL_CTRL 0x04
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#define SUNXI_DAC_FIFOC 0x10
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#define SUNXI_DAC_FIFOS 0x14
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#define SUNXI_DAC_TXDATA 0X20
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#define SUNXI_DAC_CNT 0x24
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#define SUNXI_DAC_DG 0x28
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#define SUNXI_ADC_FIFOC 0x30
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#define SUNXI_ADC_VOL_CTRL 0x34
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#define SUNXI_ADC_FIFOS 0x38
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#define SUNXI_ADC_RXDATA 0x40
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#define SUNXI_ADC_CNT 0x44
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#define SUNXI_ADC_DG 0x4C
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#define SUNXI_DAC_DAP_CTL 0xF0
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#define SUNXI_ADC_DAP_CTL 0xF8
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#define SUNXI_DAC_DRC_HHPFC 0x100
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#define SUNXI_DAC_DRC_LHPFC 0x104
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#define SUNXI_DAC_DRC_CTRL 0x108
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#define SUNXI_DAC_DRC_LPFHAT 0x10C
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#define SUNXI_DAC_DRC_LPFLAT 0x110
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#define SUNXI_DAC_DRC_RPFHAT 0x114
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#define SUNXI_DAC_DRC_RPFLAT 0x118
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#define SUNXI_DAC_DRC_LPFHRT 0x11C
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#define SUNXI_DAC_DRC_LPFLRT 0x120
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#define SUNXI_DAC_DRC_RPFHRT 0x124
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#define SUNXI_DAC_DRC_RPFLRT 0x128
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#define SUNXI_DAC_DRC_LRMSHAT 0x12C
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#define SUNXI_DAC_DRC_LRMSLAT 0x130
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#define SUNXI_DAC_DRC_RRMSHAT 0x134
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#define SUNXI_DAC_DRC_RRMSLAT 0x138
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#define SUNXI_DAC_DRC_HCT 0x13C
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#define SUNXI_DAC_DRC_LCT 0x140
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#define SUNXI_DAC_DRC_HKC 0x144
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#define SUNXI_DAC_DRC_LKC 0x148
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#define SUNXI_DAC_DRC_HOPC 0x14C
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#define SUNXI_DAC_DRC_LOPC 0x150
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#define SUNXI_DAC_DRC_HLT 0x154
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#define SUNXI_DAC_DRC_LLT 0x158
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#define SUNXI_DAC_DRC_HKI 0x15C
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#define SUNXI_DAC_DRC_LKI 0x160
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#define SUNXI_DAC_DRC_HOPL 0x164
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#define SUNXI_DAC_DRC_LOPL 0x168
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#define SUNXI_DAC_DRC_HET 0x16C
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#define SUNXI_DAC_DRC_LET 0x170
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#define SUNXI_DAC_DRC_HKE 0x174
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#define SUNXI_DAC_DRC_LKE 0x178
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#define SUNXI_DAC_DRC_HOPE 0x17C
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#define SUNXI_DAC_DRC_LOPE 0x180
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#define SUNXI_DAC_DRC_HKN 0x184
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#define SUNXI_DAC_DRC_LKN 0x188
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#define SUNXI_DAC_DRC_SFHAT 0x18C
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#define SUNXI_DAC_DRC_SFLAT 0x190
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#define SUNXI_DAC_DRC_SFHRT 0x194
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#define SUNXI_DAC_DRC_SFLRT 0x198
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#define SUNXI_DAC_DRC_MXGHS 0x19C
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#define SUNXI_DAC_DRC_MXGLS 0x1A0
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#define SUNXI_DAC_DRC_MNGHS 0x1A4
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#define SUNXI_DAC_DRC_MNGLS 0x1A8
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#define SUNXI_DAC_DRC_EPSHC 0x1AC
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#define SUNXI_DAC_DRC_EPSLC 0x1B0
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#define SUNXI_DAC_DRC_OPT 0x1B4
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#define SUNXI_DAC_DRC_HPFHGAIN 0x1B8
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#define SUNXI_DAC_DRC_HPFLGAIN 0x1BC
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#define SUNXI_ADC_DRC_HHPFC 0x200
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#define SUNXI_ADC_DRC_LHPFC 0x204
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#define SUNXI_ADC_DRC_CTRL 0x208
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#define SUNXI_ADC_DRC_LPFHAT 0x20C
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#define SUNXI_ADC_DRC_LPFLAT 0x210
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#define SUNXI_ADC_DRC_RPFHAT 0x214
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#define SUNXI_ADC_DRC_RPFLAT 0x218
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#define SUNXI_ADC_DRC_LPFHRT 0x21C
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#define SUNXI_ADC_DRC_LPFLRT 0x220
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#define SUNXI_ADC_DRC_RPFHRT 0x224
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#define SUNXI_ADC_DRC_RPFLRT 0x228
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#define SUNXI_ADC_DRC_LRMSHAT 0x22C
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#define SUNXI_ADC_DRC_LRMSLAT 0x230
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#define SUNXI_ADC_DRC_HCT 0x23C
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#define SUNXI_ADC_DRC_LCT 0x240
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#define SUNXI_ADC_DRC_HKC 0x244
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#define SUNXI_ADC_DRC_LKC 0x248
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#define SUNXI_ADC_DRC_HOPC 0x24C
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#define SUNXI_ADC_DRC_LOPC 0x250
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#define SUNXI_ADC_DRC_HLT 0x254
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#define SUNXI_ADC_DRC_LLT 0x258
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#define SUNXI_ADC_DRC_HKI 0x25C
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#define SUNXI_ADC_DRC_LKI 0x260
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#define SUNXI_ADC_DRC_HOPL 0x264
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#define SUNXI_ADC_DRC_LOPL 0x268
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#define SUNXI_ADC_DRC_HET 0x26C
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#define SUNXI_ADC_DRC_LET 0x270
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#define SUNXI_ADC_DRC_HKE 0x274
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#define SUNXI_ADC_DRC_LKE 0x278
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#define SUNXI_ADC_DRC_HOPE 0x27C
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#define SUNXI_ADC_DRC_LOPE 0x280
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#define SUNXI_ADC_DRC_HKN 0x284
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#define SUNXI_ADC_DRC_LKN 0x288
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#define SUNXI_ADC_DRC_SFHAT 0x28C
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#define SUNXI_ADC_DRC_SFLAT 0x290
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#define SUNXI_ADC_DRC_SFHRT 0x294
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#define SUNXI_ADC_DRC_SFLRT 0x298
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#define SUNXI_ADC_DRC_MXGHS 0x29C
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#define SUNXI_ADC_DRC_MXGLS 0x2A0
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#define SUNXI_ADC_DRC_MNGHS 0x2A4
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#define SUNXI_ADC_DRC_MNGLS 0x2A8
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#define SUNXI_ADC_DRC_EPSHC 0x2AC
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#define SUNXI_ADC_DRC_EPSLC 0x2B0
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#define SUNXI_ADC_DRC_OPT 0x2B4
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#define SUNXI_ADC_DRC_HPFHGAIN 0x2B8
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#define SUNXI_ADC_DRC_HPFLGAIN 0x2BC
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#define SUNXI_AC_VERSION 0x2C0
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/* Analog register */
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#define SUNXI_ADCL_REG 0x300
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#define SUNXI_ADCR_REG 0x304
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#define SUNXI_DAC_REG 0x310
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#define SUNXI_MICBIAS_REG 0x318
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#define SUNXI_BIAS_REG 0x320
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#define SUNXI_HEADPHONE_REG 0x324
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#define SUNXI_HMIC_CTRL 0x328
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#define SUNXI_HMIC_STS 0x32c
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/* SUNXI_DAC_DPC:0x00 */
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#define EN_DAC 31
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#define MODQU 25
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#define DWA_EN 24
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#define HPF_EN 18
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#define DVOL 12
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#define DAC_HUB_EN 0
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/* SUNXI_DAC_VOL_CTRL:0x04 */
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#define DAC_VOL_SEL 16
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#define DAC_VOL_L 8
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#define DAC_VOL_R 0
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/* SUNXI_DAC_FIFOC:0x10 */
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#define DAC_FS 29
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#define FIR_VER 28
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#define SEND_LASAT 26
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#define FIFO_MODE 24
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#define DAC_DRQ_CLR_CNT 21
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#define TX_TRIG_LEVEL 8
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#define DAC_MONO_EN 6
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#define TX_SAMPLE_BITS 5
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#define DAC_DRQ_EN 4
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#define DAC_IRQ_EN 3
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#define FIFO_UNDERRUN_IRQ_EN 2
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#define FIFO_OVERRUN_IRQ_EN 1
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#define FIFO_FLUSH 0
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/* SUNXI_DAC_FIFOS:0x14 */
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#define TX_EMPTY 23
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#define DAC_TXE_CNT 8
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#define DAC_TXE_INT 3
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#define DAC_TXU_INT 2
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#define DAC_TXO_INT 1
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/* SUNXI_DAC_DG:0x28 */
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#define DAC_MODU_SEL 11
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#define DAC_PATTERN_SEL 9
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#define DAC_CODEC_CLK_SEL 8
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#define DAC_SWP 6
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#define ADDA_LOOP_MODE 0
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/* SUNXI_ADC_FIFOC:0x30 */
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#define ADC_FS 29
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#define EN_AD 28
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#define ADCFDT 26
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#define ADCDFEN 25
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#define RX_FIFO_MODE 24
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#define RX_SYNC_EN 21
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#define RX_EN_MUX 20
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#define ADC_VOL_SEL 17
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#define RX_SAMPLE_BITS 16
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#define ADC_CHAN_EN 12
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#define RX_FIFO_TRG_LEVEL 4
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#define ADC_DRQ_EN 3
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#define ADC_IRQ_EN 2
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#define ADC_OVERRUN_IRQ_EN 1
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#define ADC_FIFO_FLUSH 0
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/* SUNXI_ADC_FIFOS:0x34 */
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#define ADC_VOL_L 8
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#define ADC_VOL_R 0
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/* SUNXI_ADC_FIFOS:0x38 */
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#define RXA 23
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#define ADC_RXA_CNT 8
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#define ADC_RXA_INT 3
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#define ADC_RXO_INT 1
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/* SUNXI_ADC_DG:0x4C */
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#define AD_SWP 24
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/* SUNXI_DAC_DAP_CTL:0xf0 */
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#define DDAP_EN 31
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#define DDAP_DRC_EN 29
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#define DDAP_HPF_EN 28
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/* SUNXI_ADC_DAP_CTL:0xf8 */
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#define ADC_DAP0_EN 31
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#define ADC_DRC0_EN 29
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#define ADC_HPF0_EN 28
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/* SUNXI_DAC_DRC_HHPFC : 0x100*/
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#define DAC_HHPF_CONF 0
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/* SUNXI_DAC_DRC_LHPFC : 0x104*/
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#define DAC_LHPF_CONF 0
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/* SUNXI_DAC_DRC_CTRL : 0x108*/
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#define DAC_DRC_DELAY_OUT_STATE 15
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#define DAC_DRC_SIGNAL_DELAY 8
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#define DAC_DRC_DELAY_BUF_EN 7
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#define DAC_DRC_GAIN_MAX_EN 6
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#define DAC_DRC_GAIN_MIN_EN 5
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#define DAC_DRC_NOISE_DET_EN 4
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#define DAC_DRC_SIGNAL_SEL 3
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#define DAC_DRC_DELAY_EN 2
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#define DAC_DRC_LT_EN 1
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#define DAC_DRC_ET_EN 0
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/* SUNXI_ADC_DRC_HHPFC : 0x200*/
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#define ADC_HHPF_CONF 0
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/* SUNXI_ADC_DRC_LHPFC : 0x204*/
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#define ADC_LHPF_CONF 0
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/* SUNXI_ADC_DRC_CTRL : 0x208*/
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#define ADC_DRC_DELAY_OUT_STATE 15
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#define ADC_DRC_SIGNAL_DELAY 8
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#define ADC_DRC_DELAY_BUF_EN 7
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#define ADC_DRC_GAIN_MAX_EN 6
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#define ADC_DRC_GAIN_MIN_EN 5
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#define ADC_DRC_NOISE_DET_EN 4
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#define ADC_DRC_SIGNAL_SEL 3
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#define ADC_DRC_DELAY_EN 2
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#define ADC_DRC_LT_EN 1
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#define ADC_DRC_ET_EN 0
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/* SUNXI_ADCL_REG : 0x300 */
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#define ADCL_EN 31
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#define MIC1AMPEN 30
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#define ADCL_DITHER_RESET 29
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#define ADCL_PGA_CTRL_RCM 18
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#define ADCL_PGA_IN_VCM_CTRL 16
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#define ADCL_PGA_GAIN_CTRL 8
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#define ADCL_IOPAAFL 6
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#define ADCL_IOPSDML1 4
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#define ADCL_IOPSDML2 2
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#define ADCL_IOPMICL 0
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/* SUNXI_ADCR_REG : 0x304 */
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#define ADCR_EN 31
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#define MIC2AMPEN 30
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#define ADCR_DITHER_RESET 29
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#define ADCR_PGA_CTRL_RCM 18
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#define ADCR_PGA_IN_VCM_CTRL 16
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#define ADCR_PGA_GAIN_CTRL 8
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#define ADCR_IOPAAFL 6
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#define ADCR_IOPSDML1 4
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#define ADCR_IOPSDML2 2
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#define ADCR_IOPMICL 0
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/* SUNXI_DAC_REG : 0x310 */
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#define CURRENT_TEST_SELECT 31
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#define HEADPHONE_GAIN 28
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#define CPLDO_EN 27
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#define CPLDO_VOLTAGE 24
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#define OPDRV_CUR 22
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#define VRA2_IOPVRS 20
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#define ILINEOUTAMPS 18
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#define IOPDACS 16
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#define DACLEN 15
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#define DACREN 14
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#define LINEOUTLEN 13
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#define DACLMUTE 12
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#define LINEOUTLDIFFEN 6
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#define LINEOUT_VOL 0
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/* SUNXI_MICBIAS_REG : 0x318 */
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#define SELDETADCFS 28
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#define SELDETADCDB 26
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#define SELDETADCBF 24
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#define JACKDETEN 23
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#define SELDETADCDY 21
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#define MICADCEN 20
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#define POPFREE 19
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#define DETMODE 18
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#define AUTOPLEN 17
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#define MICDETPL 16
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#define HMICBIASEN 15
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#define HBIASSEL 13
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#define HMICBIAS_CHOP_EN 12
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#define HMICBIAS_CHOP_CLK_SEL 10
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#define MMICBIASEN 7
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#define MBIASSEL 5
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#define MMICBIAS_CHOP_EN 4
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#define MMICBIAS_CHOP_CLK_SEL 2
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/* SUNXI_BIAS_REG : 0x320 */
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#define AC_BIASDATA 0
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/* SUNXI_HEADPHONE_REG : 0x324 */
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#define HPRCALIVERIFY 24
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#define HPLCALIVERIFY 16
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#define HPPA_EN 15
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#define HPINPUTEN 11
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#define HPOUTPUTEN 10
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#define HPPA_DEL 8
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#define CP_CLKS 6
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#define HPCALIMODE 5
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#define HPCALIVERIFY 4
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#define HPCALIFIRST 3
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#define HPCALICKS 0
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/* SUNXI_HMIC_CTRL : 0x328 */
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#define HMIC_SAMPLE_SEL 21
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#define MDATA_THRESHOLD 16
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#define HMIC_SF 14
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#define HMIC_M 10
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#define HMIC_N 6
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#define MDATA_THRESHOLD_DB 3
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#define JACK_OUT_IRQ_EN 2
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#define JACK_IN_IRQ_EN 1
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#define MIC_DET_IRQ_EN 0
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/* SUNXI_HMIC_STS : 0x32c */
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#define MDATA_DISCARD 13
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#define HMIC_DATA 8
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#define JACK_DET_OUT_ST 4
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#define JACK_DET_OIRQ 4
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#define JACK_DET_IIN_ST 3
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#define JACK_DET_IIRQ 3
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#define MIC_DET_ST 0
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/*125ms * (HP_DEBOUCE_TIME+1)*/
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#define HP_DEBOUCE_TIME 0x1
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#define REG_LABEL(constant) {#constant, constant, 0}
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#define REG_LABEL_END {NULL, 0, 0}
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/* SUNXI_CODEC_DAP_ENABLE: Whether to use the adc/dac drc/hpf function */
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#define SUNXI_CODEC_DAP_ENABLE
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/* SUNXI_CODEC_HUB_ENABLE: Whether to use the hub mode */
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#define SUNXI_CODEC_HUB_ENABLE
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struct reg_label {
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const char *name;
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const unsigned int address;
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unsigned int value;
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};
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struct codec_hw_config {
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u32 adcdrc_cfg:8;
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u32 dacdrc_cfg:8;
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u32 adchpf_cfg:8;
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u32 dachpf_cfg:8;
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};
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struct codec_spk_config {
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u32 spk_gpio;
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u32 pa_msleep;
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bool used;
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bool pa_level;
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bool pa_power_always_on;
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};
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struct sample_rate {
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unsigned int samplerate;
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unsigned int rate_bit;
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};
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struct voltage_supply {
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struct regulator *avcc;
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struct regulator *cpvin;
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};
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struct codec_dap {
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int drc_enable;
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int hpf_enable;
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};
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struct sunxi_codec_info {
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struct device *dev;
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struct regmap *regmap;
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void __iomem *digital_base;
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struct clk *pllclkx4;
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struct clk *pllcom;
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struct clk *pllcomdiv5;
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struct clk *dacclk;
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struct clk *adcclk;
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/* regulator about */
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struct voltage_supply vol_supply;
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/* for dap function */
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struct codec_dap dac_dap;
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struct codec_dap adc_dap;
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int dac_dap_enable;
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int adc_dap_enable;
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/* self user config params */
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u32 digital_vol;
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u32 lineout_vol;
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u32 mic1gain;
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u32 mic2gain;
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u32 headphonegain;
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u32 rx_sync_en;
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struct sunxi_dma_params playback_dma_param;
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struct sunxi_dma_params capture_dma_param;
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struct codec_spk_config spk_config;
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struct codec_hw_config hw_config;
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};
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#endif /* __SUN50IW10_CODEC_H */
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