#!/usr/bin/python
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#
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# Copyright (C) 2015 The Android Open Source Project
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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#
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def gen_event_type_entry_str(event_type_name, event_type, event_config, description='',
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limited_arch=''):
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"""
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return string as below:
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EVENT_TYPE_TABLE_ENTRY(event_type_name, event_type, event_config, description, limited_arch)
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"""
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return 'EVENT_TYPE_TABLE_ENTRY("%s", %s, %s, "%s", "%s")\n' % (
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event_type_name, event_type, event_config, description, limited_arch)
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def gen_arm_event_type_entry_str(event_type_name, event_type, event_config, description):
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return gen_event_type_entry_str(event_type_name, event_type, event_config, description,
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"arm")
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def gen_hardware_events():
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hardware_configs = ["cpu-cycles",
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"instructions",
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"cache-references",
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"cache-misses",
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"branch-instructions",
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"branch-misses",
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"bus-cycles",
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"stalled-cycles-frontend",
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"stalled-cycles-backend",
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]
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generated_str = ""
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for config in hardware_configs:
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event_type_name = config
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event_config = "PERF_COUNT_HW_" + config.replace('-', '_').upper()
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generated_str += gen_event_type_entry_str(
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event_type_name, "PERF_TYPE_HARDWARE", event_config)
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return generated_str
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def gen_software_events():
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software_configs = ["cpu-clock",
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"task-clock",
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"page-faults",
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"context-switches",
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"cpu-migrations",
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["minor-faults", "PERF_COUNT_SW_PAGE_FAULTS_MIN"],
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["major-faults", "PERF_COUNT_SW_PAGE_FAULTS_MAJ"],
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"alignment-faults",
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"emulation-faults",
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]
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generated_str = ""
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for config in software_configs:
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if isinstance(config, list):
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event_type_name = config[0]
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event_config = config[1]
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else:
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event_type_name = config
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event_config = "PERF_COUNT_SW_" + config.replace('-', '_').upper()
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generated_str += gen_event_type_entry_str(
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event_type_name, "PERF_TYPE_SOFTWARE", event_config)
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return generated_str
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def gen_hw_cache_events():
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hw_cache_types = [["L1-dcache", "PERF_COUNT_HW_CACHE_L1D"],
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["L1-icache", "PERF_COUNT_HW_CACHE_L1I"],
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["LLC", "PERF_COUNT_HW_CACHE_LL"],
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["dTLB", "PERF_COUNT_HW_CACHE_DTLB"],
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["iTLB", "PERF_COUNT_HW_CACHE_ITLB"],
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["branch", "PERF_COUNT_HW_CACHE_BPU"],
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["node", "PERF_COUNT_HW_CACHE_NODE"],
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]
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hw_cache_ops = [["loads", "load", "PERF_COUNT_HW_CACHE_OP_READ"],
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["stores", "store", "PERF_COUNT_HW_CACHE_OP_WRITE"],
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["prefetches", "prefetch",
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"PERF_COUNT_HW_CACHE_OP_PREFETCH"],
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]
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hw_cache_op_results = [["accesses", "PERF_COUNT_HW_CACHE_RESULT_ACCESS"],
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["misses", "PERF_COUNT_HW_CACHE_RESULT_MISS"],
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]
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generated_str = ""
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for (type_name, type_config) in hw_cache_types:
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for (op_name_access, op_name_miss, op_config) in hw_cache_ops:
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for (result_name, result_config) in hw_cache_op_results:
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if result_name == "accesses":
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event_type_name = type_name + '-' + op_name_access
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else:
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event_type_name = type_name + '-' + \
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op_name_miss + '-' + result_name
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event_config = "((%s) | (%s << 8) | (%s << 16))" % (
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type_config, op_config, result_config)
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generated_str += gen_event_type_entry_str(
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event_type_name, "PERF_TYPE_HW_CACHE", event_config)
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return generated_str
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def gen_user_space_events():
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generated_str = gen_event_type_entry_str("inplace-sampler",
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"SIMPLEPERF_TYPE_USER_SPACE_SAMPLERS",
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"SIMPLEPERF_CONFIG_INPLACE_SAMPLER")
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return generated_str
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def gen_arm_raw_events():
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# Refer to "Table D5-7 PMU event numbers" in ARMv8 specification.
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raw_types = [
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[0x00, "sw-incr", "software increment"],
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[0x01, "l1-icache-refill", "level 1 instruction cache refill"],
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[0x02, "l1-itlb-refill", "level 1 instruction TLB refill"],
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[0x03, "l1-dcache-refill", "level 1 data cache refill"],
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[0x04, "l1-dcache", "level 1 data cache access"],
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[0x05, "l1-dtlb-refill", "level 1 data TLB refill"],
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[0x06, "load-retired", "load (instruction architecturally executed)"],
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[0x07, "store-retired", "store (instruction architecturally executed)"],
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[0x08, "instruction-retired", "instructions (instruction architecturally executed)"],
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[0x09, "exception-taken", "exception taken"],
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[0x0a, "exception-return", "exception return (instruction architecturally executed)"],
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[0x0b, "cid-write-retired", "write to CONTEXIDR (instruction architecturally executed)"],
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[0x0c, "pc-write-retired", "software change of the PC (instruction architecturally executed)"],
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[0x0d, "br-immed-retired", "immediate branch (instruction architecturally executed)"],
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[0x0e, "br-return-retired", "procedure return (instruction architecturally executed)"],
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[0x0f, "unaligned-ldst-retired", "unaligned load or store (instruction architecturally executed)"],
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[0x10, "br-mis-pred", "mispredicted or not predicted branch speculatively executed"],
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[0x11, "cpu-cycles", "cpu cycles"],
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[0x12, "br-pred", "predictable branch speculatively executed"],
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[0x13, "mem-access", "data memory access"],
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[0x14, "l1-icache", "level 1 instruction cache access"],
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[0x15, "l1-dcache-wb", "level 1 data cache write-back"],
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[0x16, "l2-dcache", "level 2 data cache access"],
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[0x17, "l2-dcache-refill", "level 2 data cache refill"],
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[0x18, "l2-dcache-wb", "level 2 data cache write-back"],
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[0x19, "bus-access", "bus access"],
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[0x1a, "memory-error", "local memory error"],
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[0x1b, "inst-spec", "operation speculatively executed"],
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[0x1c, "ttbr-write-retired", "write to TTBR (instruction architecturally executed)"],
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[0x1d, "bus-cycles", "bus cycle"],
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# [0x1e, "chain", ""], // Not useful in user space.
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[0x1f, "l1-dcache-allocate", "level 1 data cache allocation without refill"],
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[0x20, "l2-dcache-allocate", "level 2 data cache allocation without refill"],
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[0x21, "br-retired", "branch (instruction architecturally executed)"],
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[0x22, "br-mis-pred-retired", "mispredicted branch (instruction architecturally executed)"],
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[0x23, "stall-frontend", "no operation issued due to the frontend"],
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[0x24, "stall-backend", "no operation issued due to the backend"],
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[0x25, "l1-dtlb", "level 1 data or unified TLB access"],
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[0x26, "l1-itlb", "level 1 instruction TLB access"],
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[0x27, "l2-icache", "level 2 instruction cache access"],
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[0x28, "l2-icache-refill", "level 2 instruction cache refill"],
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[0x29, "l3-dcache-allocate", "level 3 data or unified cache allocation without refill"],
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[0x2a, "l3-dcache-refill", "level 3 data or unified cache refill"],
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[0x2b, "l3-dcache", "level 3 data or unified cache access"],
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[0x2c, "l3-dcache-wb", "level 3 data or unified cache write-back"],
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[0x2d, "l2-dtlb-refill", "level 2 data or unified TLB refill"],
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[0x2e, "l2-itlb-refill", "level 2 instruction TLB refill"],
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[0x2f, "l2-dtlb", "level 2 data or unified TLB access"],
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[0x30, "l2-itlb", "level 2 instruction TLB access"],
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]
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generated_str = ""
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for item in raw_types:
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event_type = 'PERF_TYPE_RAW'
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event_type_name = "raw-" + item[1]
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event_config = '0x%x' % item[0]
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description = item[2]
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generated_str += gen_arm_event_type_entry_str(event_type_name, event_type, event_config,
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description)
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return generated_str
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def gen_events():
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generated_str = "// This file is auto-generated by generate-event_table.py.\n\n"
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generated_str += gen_hardware_events() + '\n'
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generated_str += gen_software_events() + '\n'
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generated_str += gen_hw_cache_events() + '\n'
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generated_str += gen_user_space_events() + '\n'
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generated_str += gen_arm_raw_events() + '\n'
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return generated_str
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generated_str = gen_events()
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fh = open('event_type_table.h', 'w')
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fh.write(generated_str)
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fh.close()
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