/* Capstone Disassembler Engine */
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/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013> */
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// This sample code demonstrates the APIs cs_malloc() & cs_disasm_iter().
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#include <stdio.h>
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#include <stdlib.h>
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#include <platform.h>
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#include <capstone.h>
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struct platform {
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cs_arch arch;
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cs_mode mode;
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unsigned char *code;
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size_t size;
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char *comment;
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cs_opt_type opt_type;
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cs_opt_value opt_value;
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};
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static void print_string_hex(unsigned char *str, size_t len)
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{
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unsigned char *c;
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printf("Code: ");
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for (c = str; c < str + len; c++) {
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printf("0x%02x ", *c & 0xff);
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}
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printf("\n");
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}
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static void test()
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{
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#define X86_CODE16 "\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00"
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#define X86_CODE32 "\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00"
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//#define X86_CODE32 "\x0f\xa7\xc0" // xstorerng
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#define X86_CODE64 "\x55\x48\x8b\x05\xb8\x13\x00\x00"
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//#define ARM_CODE "\x04\xe0\x2d\xe5"
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#define ARM_CODE "\xED\xFF\xFF\xEB\x04\xe0\x2d\xe5\x00\x00\x00\x00\xe0\x83\x22\xe5\xf1\x02\x03\x0e\x00\x00\xa0\xe3\x02\x30\xc1\xe7\x00\x00\x53\xe3"
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#define ARM_CODE2 "\x10\xf1\x10\xe7\x11\xf2\x31\xe7\xdc\xa1\x2e\xf3\xe8\x4e\x62\xf3"
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#define THUMB_CODE "\x70\x47\xeb\x46\x83\xb0\xc9\x68"
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#define THUMB_CODE2 "\x4f\xf0\x00\x01\xbd\xe8\x00\x88\xd1\xe8\x00\xf0"
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#define MIPS_CODE "\x0C\x10\x00\x97\x00\x00\x00\x00\x24\x02\x00\x0c\x8f\xa2\x00\x00\x34\x21\x34\x56\x00\x80\x04\x08"
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//#define MIPS_CODE "\x21\x38\x00\x01"
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//#define MIPS_CODE "\x21\x30\xe6\x70"
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//#define MIPS_CODE "\x1c\x00\x40\x14"
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#define MIPS_CODE2 "\x56\x34\x21\x34\xc2\x17\x01\x00"
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//#define ARM64_CODE "\xe1\x0b\x40\xb9" // ldr w1, [sp, #0x8]
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//#define ARM64_CODE "\x00\x40\x21\x4b" // sub w0, w0, w1, uxtw
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//#define ARM64_CODE "\x21\x7c\x02\x9b" // mul x1, x1, x2
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//#define ARM64_CODE "\x20\x74\x0b\xd5" // dc zva, x0
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//#define ARM64_CODE "\x20\xfc\x02\x9b" // mneg x0, x1, x2
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//#define ARM64_CODE "\x21\x7c\x02\x9b\x21\x7c\x00\x53\x00\x40\x21\x4b\xe1\x0b\x40\xb9\x10\x20\x21\x1e"
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//#define ARM64_CODE "\x21\x7c\x00\x53"
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#define ARM64_CODE "\x09\x00\x38\xd5\xbf\x40\x00\xd5\x0c\x05\x13\xd5\x20\x50\x02\x0e\x20\xe4\x3d\x0f\x00\x18\xa0\x5f\xa2\x00\xae\x9e\x9f\x37\x03\xd5\xbf\x33\x03\xd5\xdf\x3f\x03\xd5\x21\x7c\x02\x9b\x21\x7c\x00\x53\x00\x40\x21\x4b\xe1\x0b\x40\xb9\x20\x04\x81\xda\x20\x08\x02\x8b\x10\x5b\xe8\x3c"
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//#define THUMB_CODE "\x0a\xbf" // itet eq
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//#define X86_CODE32 "\x77\x04" // ja +6
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#define PPC_CODE "\x80\x20\x00\x00\x80\x3f\x00\x00\x10\x43\x23\x0e\xd0\x44\x00\x80\x4c\x43\x22\x02\x2d\x03\x00\x80\x7c\x43\x20\x14\x7c\x43\x20\x93\x4f\x20\x00\x21\x4c\xc8\x00\x21\x40\x82\x00\x14"
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#define SPARC_CODE "\x80\xa0\x40\x02\x85\xc2\x60\x08\x85\xe8\x20\x01\x81\xe8\x00\x00\x90\x10\x20\x01\xd5\xf6\x10\x16\x21\x00\x00\x0a\x86\x00\x40\x02\x01\x00\x00\x00\x12\xbf\xff\xff\x10\xbf\xff\xff\xa0\x02\x00\x09\x0d\xbf\xff\xff\xd4\x20\x60\x00\xd4\x4e\x00\x16\x2a\xc2\x80\x03"
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#define SPARCV9_CODE "\x81\xa8\x0a\x24\x89\xa0\x10\x20\x89\xa0\x1a\x60\x89\xa0\x00\xe0"
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#define SYSZ_CODE "\xed\x00\x00\x00\x00\x1a\x5a\x0f\x1f\xff\xc2\x09\x80\x00\x00\x00\x07\xf7\xeb\x2a\xff\xff\x7f\x57\xe3\x01\xff\xff\x7f\x57\xeb\x00\xf0\x00\x00\x24\xb2\x4f\x00\x78"
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#define XCORE_CODE "\xfe\x0f\xfe\x17\x13\x17\xc6\xfe\xec\x17\x97\xf8\xec\x4f\x1f\xfd\xec\x37\x07\xf2\x45\x5b\xf9\xfa\x02\x06\x1b\x10"
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struct platform platforms[] = {
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{
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CS_ARCH_X86,
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CS_MODE_16,
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(unsigned char *)X86_CODE16,
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sizeof(X86_CODE32) - 1,
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"X86 16bit (Intel syntax)"
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},
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{
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CS_ARCH_X86,
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CS_MODE_32,
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(unsigned char *)X86_CODE32,
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sizeof(X86_CODE32) - 1,
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"X86 32bit (ATT syntax)",
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CS_OPT_SYNTAX,
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CS_OPT_SYNTAX_ATT,
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},
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{
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CS_ARCH_X86,
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CS_MODE_32,
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(unsigned char *)X86_CODE32,
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sizeof(X86_CODE32) - 1,
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"X86 32 (Intel syntax)"
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},
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{
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CS_ARCH_X86,
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CS_MODE_64,
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(unsigned char *)X86_CODE64,
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sizeof(X86_CODE64) - 1,
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"X86 64 (Intel syntax)"
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},
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{
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CS_ARCH_ARM,
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CS_MODE_ARM,
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(unsigned char *)ARM_CODE,
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sizeof(ARM_CODE) - 1,
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"ARM"
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},
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{
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CS_ARCH_ARM,
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CS_MODE_THUMB,
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(unsigned char *)THUMB_CODE2,
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sizeof(THUMB_CODE2) - 1,
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"THUMB-2"
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},
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{
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CS_ARCH_ARM,
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CS_MODE_ARM,
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(unsigned char *)ARM_CODE2,
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sizeof(ARM_CODE2) - 1,
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"ARM: Cortex-A15 + NEON"
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},
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{
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CS_ARCH_ARM,
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CS_MODE_THUMB,
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(unsigned char *)THUMB_CODE,
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sizeof(THUMB_CODE) - 1,
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"THUMB"
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},
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{
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CS_ARCH_MIPS,
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(cs_mode)(CS_MODE_MIPS32 + CS_MODE_BIG_ENDIAN),
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(unsigned char *)MIPS_CODE,
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sizeof(MIPS_CODE) - 1,
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"MIPS-32 (Big-endian)"
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},
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{
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CS_ARCH_MIPS,
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(cs_mode)(CS_MODE_MIPS64 + CS_MODE_LITTLE_ENDIAN),
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(unsigned char *)MIPS_CODE2,
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sizeof(MIPS_CODE2) - 1,
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"MIPS-64-EL (Little-endian)"
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},
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{
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CS_ARCH_ARM64,
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CS_MODE_ARM,
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(unsigned char *)ARM64_CODE,
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sizeof(ARM64_CODE) - 1,
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"ARM-64"
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},
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{
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CS_ARCH_PPC,
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CS_MODE_BIG_ENDIAN,
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(unsigned char*)PPC_CODE,
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sizeof(PPC_CODE) - 1,
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"PPC-64"
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},
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{
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CS_ARCH_SPARC,
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CS_MODE_BIG_ENDIAN,
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(unsigned char*)SPARC_CODE,
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sizeof(SPARC_CODE) - 1,
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"Sparc"
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},
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{
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CS_ARCH_SPARC,
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(cs_mode)(CS_MODE_BIG_ENDIAN + CS_MODE_V9),
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(unsigned char*)SPARCV9_CODE,
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sizeof(SPARCV9_CODE) - 1,
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"SparcV9"
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},
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{
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CS_ARCH_SYSZ,
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(cs_mode)0,
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(unsigned char*)SYSZ_CODE,
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sizeof(SYSZ_CODE) - 1,
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"SystemZ"
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},
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{
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CS_ARCH_XCORE,
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(cs_mode)0,
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(unsigned char*)XCORE_CODE,
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sizeof(XCORE_CODE) - 1,
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"XCore"
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},
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};
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csh handle;
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uint64_t address;
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cs_insn *insn;
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cs_detail *detail;
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int i;
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cs_err err;
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const uint8_t *code;
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size_t size;
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for (i = 0; i < sizeof(platforms)/sizeof(platforms[0]); i++) {
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printf("****************\n");
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printf("Platform: %s\n", platforms[i].comment);
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err = cs_open(platforms[i].arch, platforms[i].mode, &handle);
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if (err) {
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printf("Failed on cs_open() with error returned: %u\n", err);
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continue;
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}
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if (platforms[i].opt_type)
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cs_option(handle, platforms[i].opt_type, platforms[i].opt_value);
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cs_option(handle, CS_OPT_DETAIL, CS_OPT_ON);
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// allocate memory for the cache to be used by cs_disasm_iter()
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insn = cs_malloc(handle);
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print_string_hex(platforms[i].code, platforms[i].size);
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printf("Disasm:\n");
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address = 0x1000;
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code = platforms[i].code;
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size = platforms[i].size;
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while(cs_disasm_iter(handle, &code, &size, &address, insn)) {
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int n;
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printf("0x%" PRIx64 ":\t%s\t\t%s // insn-ID: %u, insn-mnem: %s\n",
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insn->address, insn->mnemonic, insn->op_str,
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insn->id, cs_insn_name(handle, insn->id));
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// print implicit registers used by this instruction
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detail = insn->detail;
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if (detail->regs_read_count > 0) {
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printf("\tImplicit registers read: ");
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for (n = 0; n < detail->regs_read_count; n++) {
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printf("%s ", cs_reg_name(handle, detail->regs_read[n]));
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}
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printf("\n");
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}
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// print implicit registers modified by this instruction
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if (detail->regs_write_count > 0) {
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printf("\tImplicit registers modified: ");
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for (n = 0; n < detail->regs_write_count; n++) {
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printf("%s ", cs_reg_name(handle, detail->regs_write[n]));
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}
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printf("\n");
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}
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// print the groups this instruction belong to
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if (detail->groups_count > 0) {
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printf("\tThis instruction belongs to groups: ");
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for (n = 0; n < detail->groups_count; n++) {
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printf("%s ", cs_group_name(handle, detail->groups[n]));
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}
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printf("\n");
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}
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}
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printf("\n");
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// free memory allocated by cs_malloc()
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cs_free(insn, 1);
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cs_close(&handle);
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}
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}
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int main()
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{
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test();
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return 0;
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}
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