/*
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* drivers/uart/uart.c
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*
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* Copyright (C) 2012-2016 AllWinnertech Ltd.
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* Author: Sunny <Sunny@allwinnertech.com>
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*
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*/
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#include "uart_i.h"
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volatile u32 uart_pin_not_used = 1;
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volatile u32 uart_lock = 1;
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volatile static u32 uart_rate;
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#define IS_TX_FIFO_EMPTY (readl(UART_REG_USR) & (0x1 << 2))
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s32 uart_clkchangecb(u32 command, u32 freq)
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{
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if (uart_pin_not_used)
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return -EACCES;
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switch (command) {
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case CCU_CLK_CLKCHG_REQ:
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{
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/* clock will be change */
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INF("uart source clock change request\n");
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/* wait uart transmit fifo empty */
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while (!IS_TX_FIFO_EMPTY)
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continue;
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/* lock uart */
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uart_lock = 1;
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return OK;
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}
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case CCU_CLK_CLKCHG_DONE:
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{
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/* reconfig uart current baudrate */
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uart_set_baudrate(uart_rate);
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uart_lock = 0;
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INF("uart buadrate change done\n");
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return OK;
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}
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}
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return -ESRCH;
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}
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/*
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* uart_init() - initialize uart.
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*
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* @return: OK if initialize uart succeeded, others if failed.
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* @note: initialize uart.
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*/
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s32 uart_init(void)
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{
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u32 div;
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u32 lcr;
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u32 apb0_clk;
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/* uart_pin_not_used may parse from dts */
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uart_pin_not_used = 0;
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if (uart_pin_not_used)
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return -EACCES;
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uart_rate = UART_BAUDRATE;
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#ifndef CFG_FPGA_PLATFORM
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pin_set_multi_sel(PIN_GRP_PL, 2, 2);
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pin_set_multi_sel(PIN_GRP_PL, 3, 2);
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/* set reset as assert state. */
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ccu_set_mclk_reset(CCU_MOD_CLK_R_UART, CCU_CLK_NRESET),
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/* set uart clock, open apb0 uart gating. */
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ccu_set_mclk_onoff(CCU_MOD_CLK_R_UART, CCU_CLK_ON);
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/* the baud rate divisor */
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apb0_clk = ccu_get_sclk_freq(CCU_SYS_CLK_APBS2);
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div = (apb0_clk + (uart_rate << 3)) / (uart_rate << 4);
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#else
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/* set reset as assert state. */
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ccu_set_mclk_reset(CCU_MOD_CLK_R_UART, CCU_CLK_NRESET),
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/* set uart clock, open apb0 uart gating. */
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ccu_set_mclk_onoff(CCU_MOD_CLK_R_UART, CCU_CLK_ON);
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apb0_clk = 24000000;
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div = (apb0_clk + (uart_rate << 3)) / (uart_rate << 4);
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pin_set_multi_sel(PIN_GRP_PL, 2, 2);
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pin_set_multi_sel(PIN_GRP_PL, 3, 2);
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#endif
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/* initialize uart controller */
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lcr = readl(UART_REG_LCR);
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writel(lcr | 0x80, UART_REG_LCR); /* select the Divsor Latch Low Register and Divsor Latch High Register */
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writel(div & 0xff, UART_REG_DLL);
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writel((div >> 8) & 0xff, UART_REG_DLH);
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#ifdef CFG_SHELL_USED
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writel(lcr & (~0x80), UART_REG_LCR);
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#endif
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writel(0, UART_REG_HALT);
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writel(3, UART_REG_LCR); /* set mode, 8bit charset */
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writel(7, UART_REG_FCR); /* enable and reset transmit/receive fifo */
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#ifdef CFG_SHELL_USED
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writel(1, UART_REG_IER); /* enable receiver interrupt */
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#endif
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/* ensure uart is unlock */
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uart_lock = 0;
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/* uart initialize succeeded */
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return OK;
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}
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/*
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* uart_putc() - exit uart.
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*
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* @return: OK if exit uart succeeded, others if failed.
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* @note: exit uart.
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*/
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s32 uart_exit(void)
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{
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uart_lock = 1;
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uart_pin_not_used = 1;
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pin_set_multi_sel(PIN_GRP_PL, 2, 7);
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pin_set_multi_sel(PIN_GRP_PL, 3, 7);
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/* set uart clock, open apb0 uart gating. */
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ccu_set_mclk_onoff(CCU_MOD_CLK_R_UART, CCU_CLK_OFF);
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/* set reset as assert state. */
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ccu_set_mclk_reset(CCU_MOD_CLK_R_UART, CCU_CLK_RESET);
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return OK;
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}
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/*
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* uart_putc() - put out a charset.
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*
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* @ch: the charset which we want to put out.
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* @return: OK if put out charset succeeded, others if failed.
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* @note: put out a charset.
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*/
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s32 uart_putc(char ch)
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{
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if (uart_lock || uart_pin_not_used)
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return -EACCES;
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while (!(readl(UART_REG_USR) & 2)) /* fifo is full, check again */
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;
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/* write out charset to transmit fifo */
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writel(ch, UART_REG_THR);
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return OK;
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}
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/*
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* uart_getc() - get a charset.
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*
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* @return: the charset we read from uart.
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* @note: get a charset.
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*/
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u32 uart_get(char *buf)
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{
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u32 count = 0;
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if (uart_lock || uart_pin_not_used)
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return -EACCES;
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while (readl(UART_REG_RFL)) {
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*buf++ = (char)(readl(UART_REG_RBR) & 0xff);
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count++;
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}
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return count;
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}
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/*
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* uart_puts() - put out a string.
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*
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* @string: the string which we want to put out.
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* @return: OK if put out string succeeded, others if failed.
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* @note: put out a string.
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*/
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s32 uart_puts(const char *string)
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{
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if (uart_lock || uart_pin_not_used)
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return -EACCES;
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ASSERT(string != NULL);
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while (*string != '\0') {
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if (*string == '\n') /* if current character is '\n', insert output with '\r' */
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uart_putc('\r');
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uart_putc(*string++);
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}
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return OK;
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}
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s32 uart_set_baudrate(u32 rate)
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{
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u32 freq;
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u32 div;
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u32 lcr;
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u32 halt;
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if (uart_pin_not_used)
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return -EACCES;
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/* update current uart baudrate */
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LOG("uart buadrate change from [%d] to [%d]\n", uart_rate, rate);
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uart_rate = rate;
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/* wait uart transmit fifo empty */
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while (readl(UART_REG_TFL))
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continue;
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/* reconfig uart baudrate */
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#ifdef CFG_FPGA_PLATFORM
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freq = 24000000;
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#else
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freq = ccu_get_sclk_freq(CCU_SYS_CLK_APBS2);
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#endif
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div = (freq + (uart_rate << 3)) / (uart_rate << 4);
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lcr = readl(UART_REG_LCR);
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if (div == 0) /* avoid config invalid value */
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div = 1;
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/* enable change when busy */
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halt = readl(UART_REG_HALT) | 0x2;
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writel(halt, UART_REG_HALT);
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/* select the divsor latch low register and divsor latch high register */
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writel(lcr | 0x80, UART_REG_LCR);
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/* set divsor of uart */
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writel(div & 0xff, UART_REG_DLL);
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writel((div >> 8) & 0xff, UART_REG_DLH);
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/* unselect the divsor latch low register and divsor latch high register */
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writel(lcr & (~0x80), UART_REG_LCR);
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/* update baudrate */
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halt = readl(UART_REG_HALT) | 0x4;
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writel(halt, UART_REG_HALT);
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/* waiting update */
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while (readl(UART_REG_HALT) & 0x4)
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continue;
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/* disable change when busy */
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halt = readl(UART_REG_HALT) | 0x4;
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writel(halt & (~0x2), UART_REG_HALT);
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return OK;
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}
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u32 uart_get_baudrate(void)
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{
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return uart_rate;
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}
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