/*
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* Copyright (C) 2014 The Android Open Source Project
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef ART_COMPILER_OPTIMIZING_REGISTER_ALLOCATOR_LINEAR_SCAN_H_
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#define ART_COMPILER_OPTIMIZING_REGISTER_ALLOCATOR_LINEAR_SCAN_H_
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#include "arch/instruction_set.h"
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#include "base/scoped_arena_containers.h"
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#include "base/macros.h"
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#include "register_allocator.h"
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namespace art {
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class CodeGenerator;
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class HBasicBlock;
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class HGraph;
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class HInstruction;
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class HParallelMove;
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class HPhi;
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class LiveInterval;
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class Location;
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class SsaLivenessAnalysis;
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/**
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* An implementation of a linear scan register allocator on an `HGraph` with SSA form.
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*/
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class RegisterAllocatorLinearScan : public RegisterAllocator {
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public:
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RegisterAllocatorLinearScan(ScopedArenaAllocator* allocator,
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CodeGenerator* codegen,
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const SsaLivenessAnalysis& analysis);
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~RegisterAllocatorLinearScan() override;
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void AllocateRegisters() override;
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bool Validate(bool log_fatal_on_failure) override {
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processing_core_registers_ = true;
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if (!ValidateInternal(log_fatal_on_failure)) {
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return false;
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}
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processing_core_registers_ = false;
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return ValidateInternal(log_fatal_on_failure);
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}
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size_t GetNumberOfSpillSlots() const {
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return int_spill_slots_.size()
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+ long_spill_slots_.size()
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+ float_spill_slots_.size()
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+ double_spill_slots_.size()
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+ catch_phi_spill_slots_;
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}
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private:
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// Main methods of the allocator.
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void LinearScan();
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bool TryAllocateFreeReg(LiveInterval* interval);
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bool AllocateBlockedReg(LiveInterval* interval);
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// Add `interval` in the given sorted list.
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static void AddSorted(ScopedArenaVector<LiveInterval*>* array, LiveInterval* interval);
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// Returns whether `reg` is blocked by the code generator.
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bool IsBlocked(int reg) const;
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// Update the interval for the register in `location` to cover [start, end).
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void BlockRegister(Location location, size_t start, size_t end);
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void BlockRegisters(size_t start, size_t end, bool caller_save_only = false);
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// Allocate a spill slot for the given interval. Should be called in linear
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// order of interval starting positions.
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void AllocateSpillSlotFor(LiveInterval* interval);
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// Allocate a spill slot for the given catch phi. Will allocate the same slot
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// for phis which share the same vreg. Must be called in reverse linear order
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// of lifetime positions and ascending vreg numbers for correctness.
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void AllocateSpillSlotForCatchPhi(HPhi* phi);
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// Helper methods.
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void AllocateRegistersInternal();
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void ProcessInstruction(HInstruction* instruction);
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bool ValidateInternal(bool log_fatal_on_failure) const;
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void DumpInterval(std::ostream& stream, LiveInterval* interval) const;
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void DumpAllIntervals(std::ostream& stream) const;
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int FindAvailableRegisterPair(size_t* next_use, size_t starting_at) const;
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int FindAvailableRegister(size_t* next_use, LiveInterval* current) const;
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bool IsCallerSaveRegister(int reg) const;
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// Try splitting an active non-pair or unaligned pair interval at the given `position`.
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// Returns whether it was successful at finding such an interval.
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bool TrySplitNonPairOrUnalignedPairIntervalAt(size_t position,
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size_t first_register_use,
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size_t* next_use);
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// List of intervals for core registers that must be processed, ordered by start
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// position. Last entry is the interval that has the lowest start position.
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// This list is initially populated before doing the linear scan.
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ScopedArenaVector<LiveInterval*> unhandled_core_intervals_;
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// List of intervals for floating-point registers. Same comments as above.
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ScopedArenaVector<LiveInterval*> unhandled_fp_intervals_;
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// Currently processed list of unhandled intervals. Either `unhandled_core_intervals_`
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// or `unhandled_fp_intervals_`.
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ScopedArenaVector<LiveInterval*>* unhandled_;
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// List of intervals that have been processed.
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ScopedArenaVector<LiveInterval*> handled_;
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// List of intervals that are currently active when processing a new live interval.
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// That is, they have a live range that spans the start of the new interval.
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ScopedArenaVector<LiveInterval*> active_;
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// List of intervals that are currently inactive when processing a new live interval.
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// That is, they have a lifetime hole that spans the start of the new interval.
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ScopedArenaVector<LiveInterval*> inactive_;
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// Fixed intervals for physical registers. Such intervals cover the positions
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// where an instruction requires a specific register.
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ScopedArenaVector<LiveInterval*> physical_core_register_intervals_;
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ScopedArenaVector<LiveInterval*> physical_fp_register_intervals_;
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// Intervals for temporaries. Such intervals cover the positions
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// where an instruction requires a temporary.
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ScopedArenaVector<LiveInterval*> temp_intervals_;
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// The spill slots allocated for live intervals. We ensure spill slots
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// are typed to avoid (1) doing moves and swaps between two different kinds
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// of registers, and (2) swapping between a single stack slot and a double
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// stack slot. This simplifies the parallel move resolver.
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ScopedArenaVector<size_t> int_spill_slots_;
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ScopedArenaVector<size_t> long_spill_slots_;
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ScopedArenaVector<size_t> float_spill_slots_;
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ScopedArenaVector<size_t> double_spill_slots_;
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// Spill slots allocated to catch phis. This category is special-cased because
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// (1) slots are allocated prior to linear scan and in reverse linear order,
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// (2) equivalent phis need to share slots despite having different types.
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size_t catch_phi_spill_slots_;
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// Instructions that need a safepoint.
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ScopedArenaVector<HInstruction*> safepoints_;
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// True if processing core registers. False if processing floating
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// point registers.
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bool processing_core_registers_;
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// Number of registers for the current register kind (core or floating point).
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size_t number_of_registers_;
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// Temporary array, allocated ahead of time for simplicity.
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size_t* registers_array_;
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// Blocked registers, as decided by the code generator.
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bool* const blocked_core_registers_;
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bool* const blocked_fp_registers_;
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// Slots reserved for out arguments.
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size_t reserved_out_slots_;
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ART_FRIEND_TEST(RegisterAllocatorTest, FreeUntil);
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ART_FRIEND_TEST(RegisterAllocatorTest, SpillInactive);
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DISALLOW_COPY_AND_ASSIGN(RegisterAllocatorLinearScan);
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};
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} // namespace art
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#endif // ART_COMPILER_OPTIMIZING_REGISTER_ALLOCATOR_LINEAR_SCAN_H_
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