/*
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* Code borrowed from powerpc/kernel/pci-common.c
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*
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* Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
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* Copyright (C) 2014 ARM Ltd.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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*/
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#include <linux/acpi.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/mm.h>
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#include <linux/of_pci.h>
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#include <linux/of_platform.h>
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#include <linux/pci.h>
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#include <linux/pci-acpi.h>
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#include <linux/pci-ecam.h>
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#include <linux/slab.h>
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/*
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* If the bus contains any of these devices, then we must not turn on
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* parity checking of any kind. Currently this is CyberPro 20x0 only.
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*/
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static inline int pdev_bad_for_parity(struct pci_dev *dev)
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{
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return ((dev->vendor == PCI_VENDOR_ID_INTERG &&
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(dev->device == PCI_DEVICE_ID_INTERG_2000 ||
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dev->device == PCI_DEVICE_ID_INTERG_2010)) ||
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(dev->vendor == PCI_VENDOR_ID_ITE &&
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dev->device == PCI_DEVICE_ID_ITE_8152));
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}
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/*
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* Called after each bus is probed, but before its children are examined
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*/
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void pcibios_fixup_bus(struct pci_bus *bus)
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{
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struct pci_dev *dev;
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u16 features = PCI_COMMAND_SERR | PCI_COMMAND_PARITY | PCI_COMMAND_FAST_BACK;
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/*
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* Walk the devices on this bus, working out what we can
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* and can't support.
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*/
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list_for_each_entry(dev, &bus->devices, bus_list) {
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u16 status;
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pci_read_config_word(dev, PCI_STATUS, &status);
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/*
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* If any device on this bus does not support fast back
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* to back transfers, then the bus as a whole is not able
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* to support them. Having fast back to back transfers
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* on saves us one PCI cycle per transaction.
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*/
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if (!(status & PCI_STATUS_FAST_BACK))
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features &= ~PCI_COMMAND_FAST_BACK;
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if (pdev_bad_for_parity(dev))
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features &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
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switch (dev->class >> 8) {
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case PCI_CLASS_BRIDGE_PCI:
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pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &status);
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status |= PCI_BRIDGE_CTL_PARITY|PCI_BRIDGE_CTL_MASTER_ABORT;
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status &= ~(PCI_BRIDGE_CTL_BUS_RESET|PCI_BRIDGE_CTL_FAST_BACK);
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pci_write_config_word(dev, PCI_BRIDGE_CONTROL, status);
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break;
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case PCI_CLASS_BRIDGE_CARDBUS:
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pci_read_config_word(dev, PCI_CB_BRIDGE_CONTROL, &status);
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status |= PCI_CB_BRIDGE_CTL_PARITY|PCI_CB_BRIDGE_CTL_MASTER_ABORT;
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pci_write_config_word(dev, PCI_CB_BRIDGE_CONTROL, status);
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break;
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}
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}
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/*
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* Now walk the devices again, this time setting them up.
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*/
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list_for_each_entry(dev, &bus->devices, bus_list) {
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u16 cmd;
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pci_read_config_word(dev, PCI_COMMAND, &cmd);
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cmd |= features;
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pci_write_config_word(dev, PCI_COMMAND, cmd);
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pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE,
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L1_CACHE_BYTES >> 2);
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}
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/*
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* Propagate the flags to the PCI bridge.
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*/
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if (bus->self && bus->self->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
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if (features & PCI_COMMAND_FAST_BACK)
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bus->bridge_ctl |= PCI_BRIDGE_CTL_FAST_BACK;
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if (features & PCI_COMMAND_PARITY)
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bus->bridge_ctl |= PCI_BRIDGE_CTL_PARITY;
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}
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/*
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* Report what we did for this bus
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*/
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pr_info("PCI: bus%d: Fast back to back transfers %sabled\n",
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bus->number, (features & PCI_COMMAND_FAST_BACK) ? "en" : "dis");
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}
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/*
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* We don't have to worry about legacy ISA devices, so nothing to do here
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*/
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resource_size_t pcibios_align_resource(void *data, const struct resource *res,
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resource_size_t size, resource_size_t align)
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{
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return res->start;
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}
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/*
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* Try to assign the IRQ number when probing a new device
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*/
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int pcibios_alloc_irq(struct pci_dev *dev)
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{
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if (acpi_disabled)
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dev->irq = of_irq_parse_and_map_pci(dev, 0, 0);
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#ifdef CONFIG_ACPI
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else
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return acpi_pci_irq_enable(dev);
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#endif
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return 0;
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}
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/*
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* raw_pci_read/write - Platform-specific PCI config space access.
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*/
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int raw_pci_read(unsigned int domain, unsigned int bus,
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unsigned int devfn, int reg, int len, u32 *val)
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{
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struct pci_bus *b = pci_find_bus(domain, bus);
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if (!b)
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return PCIBIOS_DEVICE_NOT_FOUND;
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return b->ops->read(b, devfn, reg, len, val);
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}
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int raw_pci_write(unsigned int domain, unsigned int bus,
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unsigned int devfn, int reg, int len, u32 val)
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{
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struct pci_bus *b = pci_find_bus(domain, bus);
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if (!b)
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return PCIBIOS_DEVICE_NOT_FOUND;
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return b->ops->write(b, devfn, reg, len, val);
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}
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#ifdef CONFIG_NUMA
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int pcibus_to_node(struct pci_bus *bus)
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{
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return dev_to_node(&bus->dev);
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}
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EXPORT_SYMBOL(pcibus_to_node);
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#endif
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#ifdef CONFIG_ACPI
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struct acpi_pci_generic_root_info {
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struct acpi_pci_root_info common;
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struct pci_config_window *cfg; /* config space mapping */
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};
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int acpi_pci_bus_find_domain_nr(struct pci_bus *bus)
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{
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struct pci_config_window *cfg = bus->sysdata;
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struct acpi_device *adev = to_acpi_device(cfg->parent);
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struct acpi_pci_root *root = acpi_driver_data(adev);
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return root->segment;
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}
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int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
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{
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if (!acpi_disabled) {
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struct pci_config_window *cfg = bridge->bus->sysdata;
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struct acpi_device *adev = to_acpi_device(cfg->parent);
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ACPI_COMPANION_SET(&bridge->dev, adev);
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}
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return 0;
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}
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/*
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* Lookup the bus range for the domain in MCFG, and set up config space
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* mapping.
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*/
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static struct pci_config_window *
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pci_acpi_setup_ecam_mapping(struct acpi_pci_root *root)
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{
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struct device *dev = &root->device->dev;
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struct resource *bus_res = &root->secondary;
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u16 seg = root->segment;
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struct pci_config_window *cfg;
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struct resource cfgres;
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unsigned int bsz;
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/* Use address from _CBA if present, otherwise lookup MCFG */
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if (!root->mcfg_addr)
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root->mcfg_addr = pci_mcfg_lookup(seg, bus_res);
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if (!root->mcfg_addr) {
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dev_err(dev, "%04x:%pR ECAM region not found\n", seg, bus_res);
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return NULL;
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}
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bsz = 1 << pci_generic_ecam_ops.bus_shift;
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cfgres.start = root->mcfg_addr + bus_res->start * bsz;
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cfgres.end = cfgres.start + resource_size(bus_res) * bsz - 1;
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cfgres.flags = IORESOURCE_MEM;
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cfg = pci_ecam_create(dev, &cfgres, bus_res, &pci_generic_ecam_ops);
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if (IS_ERR(cfg)) {
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dev_err(dev, "%04x:%pR error %ld mapping ECAM\n", seg, bus_res,
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PTR_ERR(cfg));
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return NULL;
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}
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return cfg;
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}
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/* release_info: free resources allocated by init_info */
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static void pci_acpi_generic_release_info(struct acpi_pci_root_info *ci)
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{
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struct acpi_pci_generic_root_info *ri;
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ri = container_of(ci, struct acpi_pci_generic_root_info, common);
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pci_ecam_free(ri->cfg);
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kfree(ci->ops);
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kfree(ri);
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}
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/* Interface called from ACPI code to setup PCI host controller */
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struct pci_bus *pci_acpi_scan_root(struct acpi_pci_root *root)
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{
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int node = acpi_get_node(root->device->handle);
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struct acpi_pci_generic_root_info *ri;
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struct pci_bus *bus, *child;
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struct acpi_pci_root_ops *root_ops;
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ri = kzalloc_node(sizeof(*ri), GFP_KERNEL, node);
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if (!ri)
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return NULL;
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root_ops = kzalloc_node(sizeof(*root_ops), GFP_KERNEL, node);
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if (!root_ops) {
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kfree(ri);
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return NULL;
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}
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ri->cfg = pci_acpi_setup_ecam_mapping(root);
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if (!ri->cfg) {
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kfree(ri);
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kfree(root_ops);
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return NULL;
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}
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root_ops->release_info = pci_acpi_generic_release_info;
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root_ops->pci_ops = &ri->cfg->ops->pci_ops;
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bus = acpi_pci_root_create(root, root_ops, &ri->common, ri->cfg);
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if (!bus)
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return NULL;
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pci_bus_size_bridges(bus);
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pci_bus_assign_resources(bus);
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list_for_each_entry(child, &bus->children, node)
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pcie_bus_configure_settings(child);
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return bus;
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}
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void pcibios_add_bus(struct pci_bus *bus)
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{
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acpi_pci_add_bus(bus);
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}
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void pcibios_remove_bus(struct pci_bus *bus)
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{
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acpi_pci_remove_bus(bus);
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}
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#endif
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