/*
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* Broadcom Starfighter 2 switch register defines
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*
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* Copyright (C) 2014, Broadcom Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef __BCM_SF2_REGS_H
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#define __BCM_SF2_REGS_H
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/* Register set relative to 'REG' */
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#define REG_SWITCH_CNTRL 0x00
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#define MDIO_MASTER_SEL (1 << 0)
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#define REG_SWITCH_STATUS 0x04
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#define REG_DIR_DATA_WRITE 0x08
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#define REG_DIR_DATA_READ 0x0C
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#define REG_SWITCH_REVISION 0x18
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#define SF2_REV_MASK 0xffff
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#define SWITCH_TOP_REV_SHIFT 16
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#define SWITCH_TOP_REV_MASK 0xffff
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#define REG_PHY_REVISION 0x1C
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#define PHY_REVISION_MASK 0xffff
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#define REG_SPHY_CNTRL 0x2C
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#define IDDQ_BIAS (1 << 0)
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#define EXT_PWR_DOWN (1 << 1)
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#define FORCE_DLL_EN (1 << 2)
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#define IDDQ_GLOBAL_PWR (1 << 3)
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#define CK25_DIS (1 << 4)
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#define PHY_RESET (1 << 5)
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#define PHY_PHYAD_SHIFT 8
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#define PHY_PHYAD_MASK 0x1F
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#define REG_RGMII_0_BASE 0x34
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#define REG_RGMII_CNTRL 0x00
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#define REG_RGMII_IB_STATUS 0x04
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#define REG_RGMII_RX_CLOCK_DELAY_CNTRL 0x08
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#define REG_RGMII_CNTRL_SIZE 0x0C
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#define REG_RGMII_CNTRL_P(x) (REG_RGMII_0_BASE + \
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((x) * REG_RGMII_CNTRL_SIZE))
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/* Relative to REG_RGMII_CNTRL */
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#define RGMII_MODE_EN (1 << 0)
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#define ID_MODE_DIS (1 << 1)
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#define PORT_MODE_SHIFT 2
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#define INT_EPHY (0 << PORT_MODE_SHIFT)
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#define INT_GPHY (1 << PORT_MODE_SHIFT)
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#define EXT_EPHY (2 << PORT_MODE_SHIFT)
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#define EXT_GPHY (3 << PORT_MODE_SHIFT)
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#define EXT_REVMII (4 << PORT_MODE_SHIFT)
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#define PORT_MODE_MASK 0x7
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#define RVMII_REF_SEL (1 << 5)
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#define RX_PAUSE_EN (1 << 6)
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#define TX_PAUSE_EN (1 << 7)
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#define TX_CLK_STOP_EN (1 << 8)
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#define LPI_COUNT_SHIFT 9
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#define LPI_COUNT_MASK 0x3F
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#define REG_LED_CNTRL_BASE 0x90
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#define REG_LED_CNTRL(x) (REG_LED_CNTRL_BASE + (x) * 4)
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#define SPDLNK_SRC_SEL (1 << 24)
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/* Register set relative to 'INTRL2_0' and 'INTRL2_1' */
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#define INTRL2_CPU_STATUS 0x00
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#define INTRL2_CPU_SET 0x04
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#define INTRL2_CPU_CLEAR 0x08
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#define INTRL2_CPU_MASK_STATUS 0x0c
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#define INTRL2_CPU_MASK_SET 0x10
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#define INTRL2_CPU_MASK_CLEAR 0x14
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/* Shared INTRL2_0 and INTRL2_ interrupt sources macros */
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#define P_LINK_UP_IRQ(x) (1 << (0 + (x)))
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#define P_LINK_DOWN_IRQ(x) (1 << (1 + (x)))
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#define P_ENERGY_ON_IRQ(x) (1 << (2 + (x)))
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#define P_ENERGY_OFF_IRQ(x) (1 << (3 + (x)))
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#define P_GPHY_IRQ(x) (1 << (4 + (x)))
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#define P_NUM_IRQ 5
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#define P_IRQ_MASK(x) (P_LINK_UP_IRQ((x)) | \
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P_LINK_DOWN_IRQ((x)) | \
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P_ENERGY_ON_IRQ((x)) | \
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P_ENERGY_OFF_IRQ((x)) | \
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P_GPHY_IRQ((x)))
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/* INTRL2_0 interrupt sources */
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#define P0_IRQ_OFF 0
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#define MEM_DOUBLE_IRQ (1 << 5)
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#define EEE_LPI_IRQ (1 << 6)
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#define P5_CPU_WAKE_IRQ (1 << 7)
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#define P8_CPU_WAKE_IRQ (1 << 8)
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#define P7_CPU_WAKE_IRQ (1 << 9)
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#define IEEE1588_IRQ (1 << 10)
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#define MDIO_ERR_IRQ (1 << 11)
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#define MDIO_DONE_IRQ (1 << 12)
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#define GISB_ERR_IRQ (1 << 13)
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#define UBUS_ERR_IRQ (1 << 14)
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#define FAILOVER_ON_IRQ (1 << 15)
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#define FAILOVER_OFF_IRQ (1 << 16)
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#define TCAM_SOFT_ERR_IRQ (1 << 17)
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/* INTRL2_1 interrupt sources */
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#define P7_IRQ_OFF 0
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#define P_IRQ_OFF(x) ((6 - (x)) * P_NUM_IRQ)
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/* Register set relative to 'CORE' */
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#define CORE_G_PCTL_PORT0 0x00000
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#define CORE_G_PCTL_PORT(x) (CORE_G_PCTL_PORT0 + (x * 0x4))
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#define CORE_IMP_CTL 0x00020
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#define RX_DIS (1 << 0)
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#define TX_DIS (1 << 1)
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#define RX_BCST_EN (1 << 2)
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#define RX_MCST_EN (1 << 3)
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#define RX_UCST_EN (1 << 4)
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#define CORE_SWMODE 0x0002c
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#define SW_FWDG_MODE (1 << 0)
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#define SW_FWDG_EN (1 << 1)
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#define RTRY_LMT_DIS (1 << 2)
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#define CORE_STS_OVERRIDE_IMP 0x00038
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#define GMII_SPEED_UP_2G (1 << 6)
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#define MII_SW_OR (1 << 7)
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#define CORE_NEW_CTRL 0x00084
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#define IP_MC (1 << 0)
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#define OUTRANGEERR_DISCARD (1 << 1)
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#define INRANGEERR_DISCARD (1 << 2)
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#define CABLE_DIAG_LEN (1 << 3)
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#define OVERRIDE_AUTO_PD_WAR (1 << 4)
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#define EN_AUTO_PD_WAR (1 << 5)
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#define UC_FWD_EN (1 << 6)
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#define MC_FWD_EN (1 << 7)
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#define CORE_SWITCH_CTRL 0x00088
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#define MII_DUMB_FWDG_EN (1 << 6)
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#define CORE_SFT_LRN_CTRL 0x000f8
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#define SW_LEARN_CNTL(x) (1 << (x))
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#define CORE_STS_OVERRIDE_GMIIP_PORT(x) (0x160 + (x) * 4)
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#define LINK_STS (1 << 0)
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#define DUPLX_MODE (1 << 1)
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#define SPEED_SHIFT 2
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#define SPEED_MASK 0x3
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#define RXFLOW_CNTL (1 << 4)
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#define TXFLOW_CNTL (1 << 5)
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#define SW_OVERRIDE (1 << 6)
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#define CORE_WATCHDOG_CTRL 0x001e4
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#define SOFTWARE_RESET (1 << 7)
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#define EN_CHIP_RST (1 << 6)
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#define EN_SW_RESET (1 << 4)
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#define CORE_FAST_AGE_CTRL 0x00220
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#define EN_FAST_AGE_STATIC (1 << 0)
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#define EN_AGE_DYNAMIC (1 << 1)
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#define EN_AGE_PORT (1 << 2)
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#define EN_AGE_VLAN (1 << 3)
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#define EN_AGE_SPT (1 << 4)
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#define EN_AGE_MCAST (1 << 5)
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#define FAST_AGE_STR_DONE (1 << 7)
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#define CORE_FAST_AGE_PORT 0x00224
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#define AGE_PORT_MASK 0xf
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#define CORE_FAST_AGE_VID 0x00228
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#define AGE_VID_MASK 0x3fff
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#define CORE_LNKSTS 0x00400
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#define LNK_STS_MASK 0x1ff
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#define CORE_SPDSTS 0x00410
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#define SPDSTS_10 0
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#define SPDSTS_100 1
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#define SPDSTS_1000 2
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#define SPDSTS_SHIFT 2
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#define SPDSTS_MASK 0x3
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#define CORE_DUPSTS 0x00420
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#define CORE_DUPSTS_MASK 0x1ff
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#define CORE_PAUSESTS 0x00428
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#define PAUSESTS_TX_PAUSE_SHIFT 9
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#define CORE_GMNCFGCFG 0x0800
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#define RST_MIB_CNT (1 << 0)
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#define RXBPDU_EN (1 << 1)
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#define CORE_IMP0_PRT_ID 0x0804
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#define CORE_BRCM_HDR_CTRL 0x0080c
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#define BRCM_HDR_EN_P8 (1 << 0)
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#define BRCM_HDR_EN_P5 (1 << 1)
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#define BRCM_HDR_EN_P7 (1 << 2)
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#define CORE_RST_MIB_CNT_EN 0x0950
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#define CORE_BRCM_HDR_RX_DIS 0x0980
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#define CORE_BRCM_HDR_TX_DIS 0x0988
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#define CORE_ARLA_VTBL_RWCTRL 0x1600
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#define ARLA_VTBL_CMD_WRITE 0
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#define ARLA_VTBL_CMD_READ 1
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#define ARLA_VTBL_CMD_CLEAR 2
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#define ARLA_VTBL_STDN (1 << 7)
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#define CORE_ARLA_VTBL_ADDR 0x1604
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#define VTBL_ADDR_INDEX_MASK 0xfff
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#define CORE_ARLA_VTBL_ENTRY 0x160c
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#define FWD_MAP_MASK 0x1ff
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#define UNTAG_MAP_MASK 0x1ff
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#define UNTAG_MAP_SHIFT 9
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#define MSTP_INDEX_MASK 0x7
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#define MSTP_INDEX_SHIFT 18
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#define FWD_MODE (1 << 21)
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#define CORE_MEM_PSM_VDD_CTRL 0x2380
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#define P_TXQ_PSM_VDD_SHIFT 2
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#define P_TXQ_PSM_VDD_MASK 0x3
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#define P_TXQ_PSM_VDD(x) (P_TXQ_PSM_VDD_MASK << \
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((x) * P_TXQ_PSM_VDD_SHIFT))
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#define CORE_PORT_VLAN_CTL_PORT(x) (0xc400 + ((x) * 0x8))
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#define PORT_VLAN_CTRL_MASK 0x1ff
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#define CORE_DEFAULT_1Q_TAG_P(x) (0xd040 + ((x) * 8))
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#define CFI_SHIFT 12
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#define PRI_SHIFT 13
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#define PRI_MASK 0x7
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#define CORE_JOIN_ALL_VLAN_EN 0xd140
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#define CORE_EEE_EN_CTRL 0x24800
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#define CORE_EEE_LPI_INDICATE 0x24810
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#endif /* __BCM_SF2_REGS_H */
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