/*
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* Sunxi SD/MMC host driver
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*
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* Copyright (C) 2015 AllWinnertech Ltd.
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* Author: lixiang <lixiang@allwinnertech>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/clk.h>
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#include <linux/clk/sunxi.h>
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#include <linux/gpio.h>
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#include <linux/platform_device.h>
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#include <linux/spinlock.h>
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#include <linux/scatterlist.h>
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#include <linux/dma-mapping.h>
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#include <linux/slab.h>
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#include <linux/reset.h>
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#include <linux/of_address.h>
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#include <linux/of_gpio.h>
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#include <linux/of_platform.h>
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#include <linux/mmc/host.h>
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#include <linux/mmc/sd.h>
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#include <linux/mmc/sdio.h>
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#include <linux/mmc/mmc.h>
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#include <linux/mmc/core.h>
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#include <linux/mmc/card.h>
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#include <linux/mmc/slot-gpio.h>
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#ifndef __SUNXI_MMC_H__
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#define __SUNXI_MMC_H__
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#define DRIVER_NAME "sunxi-mmc"
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#define DRIVER_RIVISION "v3.46 2020-6-1 11:33-202006021635"
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#define DRIVER_VERSION "SD/MMC/SDIO Host Controller Driver(" DRIVER_RIVISION ")"
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#if defined CONFIG_FPGA_V4_PLATFORM || defined CONFIG_FPGA_V7_PLATFORM
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#define MMC_FPGA
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#endif
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/* register offset definitions */
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#define SDXC_REG_GCTRL (0x00) /* SMC Global Control Register */
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#define SDXC_REG_CLKCR (0x04) /* SMC Clock Control Register */
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#define SDXC_REG_TMOUT (0x08) /* SMC Time Out Register */
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#define SDXC_REG_WIDTH (0x0C) /* SMC Bus Width Register */
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#define SDXC_REG_BLKSZ (0x10) /* SMC Block Size Register */
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#define SDXC_REG_BCNTR (0x14) /* SMC Byte Count Register */
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#define SDXC_REG_CMDR (0x18) /* SMC Command Register */
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#define SDXC_REG_CARG (0x1C) /* SMC Argument Register */
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#define SDXC_REG_RESP0 (0x20) /* SMC Response Register 0 */
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#define SDXC_REG_RESP1 (0x24) /* SMC Response Register 1 */
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#define SDXC_REG_RESP2 (0x28) /* SMC Response Register 2 */
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#define SDXC_REG_RESP3 (0x2C) /* SMC Response Register 3 */
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#define SDXC_REG_IMASK (0x30) /* SMC Interrupt Mask Register */
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#define SDXC_REG_MISTA (0x34) /* SMC Masked Interrupt Status Register */
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#define SDXC_REG_RINTR (0x38) /* SMC Raw Interrupt Status Register */
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#define SDXC_REG_STAS (0x3C) /* SMC Status Register */
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#define SDXC_REG_FTRGL (0x40) /* SMC FIFO Threshold Watermark Registe */
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#define SDXC_REG_FUNS (0x44) /* SMC Function Select Register */
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#define SDXC_REG_CBCR (0x48) /* SMC CIU Byte Count Register */
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#define SDXC_REG_BBCR (0x4C) /* SMC BIU Byte Count Register */
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#define SDXC_REG_DBGC (0x50) /* SMC Debug Enable Register */
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#define SDXC_REG_A12A (0x58) /*auto cmd12 arg*/
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#define SDXC_REG_HWRST (0x78) /* SMC Card Hardware Reset for Register */
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#define SDXC_REG_DMAC (0x80) /* SMC IDMAC Control Register */
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#define SDXC_REG_DLBA (0x84) /* SMC IDMAC Descriptor List Base Addre */
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#define SDXC_REG_IDST (0x88) /* SMC IDMAC Status Register */
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#define SDXC_REG_IDIE (0x8C) /* SMC IDMAC Interrupt Enable Register */
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#define SDXC_REG_CHDA (0x90)
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#define SDXC_REG_CBDA (0x94)
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#define SDXC_REG_FIFO (0x200)
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#define mmc_readl(host, reg) \
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readl((host)->reg_base + SDXC_##reg)
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#define mmc_writel(host, reg, value) \
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writel((value), (host)->reg_base + SDXC_##reg)
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/* global control register bits */
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#define SDXC_SOFT_RESET BIT(0)
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#define SDXC_FIFO_RESET BIT(1)
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#define SDXC_DMA_RESET BIT(2)
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#define SDXC_INTERRUPT_ENABLE_BIT BIT(4)
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#define SDXC_DMA_ENABLE_BIT BIT(5)
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#define SDXC_DEBOUNCE_ENABLE_BIT BIT(8)
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#define SDXC_POSEDGE_LATCH_DATA BIT(9)
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#define SDXC_DDR_MODE BIT(10)
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#define SDXC_MEMORY_ACCESS_DONE BIT(29)
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#define SDXC_ACCESS_DONE_DIRECT BIT(30)
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#define SDXC_ACCESS_BY_AHB BIT(31)
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#define SDXC_ACCESS_BY_DMA (0 << 31)
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#define SDXC_HARDWARE_RESET \
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(SDXC_SOFT_RESET | SDXC_FIFO_RESET | SDXC_DMA_RESET)
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/* clock control bits */
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#define SDXC_CARD_CLOCK_ON BIT(16)
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#define SDXC_LOW_POWER_ON BIT(17)
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#define SDXC_MASK_DATA0 BIT(31)
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/* bus width */
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#define SDXC_WIDTH1 0
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#define SDXC_WIDTH4 1
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#define SDXC_WIDTH8 2
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/* smc command bits */
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#define SDXC_RESP_EXPECT BIT(6)
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#define SDXC_LONG_RESPONSE BIT(7)
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#define SDXC_CHECK_RESPONSE_CRC BIT(8)
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#define SDXC_DATA_EXPECT BIT(9)
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#define SDXC_WRITE BIT(10)
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#define SDXC_SEQUENCE_MODE BIT(11)
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#define SDXC_SEND_AUTO_STOP BIT(12)
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#define SDXC_WAIT_PRE_OVER BIT(13)
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#define SDXC_STOP_ABORT_CMD BIT(14)
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#define SDXC_SEND_INIT_SEQUENCE BIT(15)
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#define SDXC_UPCLK_ONLY BIT(21)
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#define SDXC_READ_CEATA_DEV BIT(22)
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#define SDXC_CCS_EXPECT BIT(23)
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#define SDXC_ENABLE_BIT_BOOT BIT(24)
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#define SDXC_ALT_BOOT_OPTIONS BIT(25)
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#define SDXC_BOOT_ACK_EXPECT BIT(26)
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#define SDXC_BOOT_ABORT BIT(27)
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#define SDXC_VOLTAGE_SWITCH BIT(28)
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#define SDXC_USE_HOLD_REGISTER BIT(29)
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#define SDXC_START BIT(31)
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/* interrupt bits */
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#define SDXC_RESP_ERROR BIT(1)
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#define SDXC_COMMAND_DONE BIT(2)
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#define SDXC_DATA_OVER BIT(3)
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#define SDXC_TX_DATA_REQUEST BIT(4)
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#define SDXC_RX_DATA_REQUEST BIT(5)
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#define SDXC_RESP_CRC_ERROR BIT(6)
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#define SDXC_DATA_CRC_ERROR BIT(7)
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#define SDXC_RESP_TIMEOUT BIT(8)
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#define SDXC_DATA_TIMEOUT BIT(9)
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#define SDXC_VOLTAGE_CHANGE_DONE BIT(10)
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#define SDXC_FIFO_RUN_ERROR BIT(11)
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#define SDXC_HARD_WARE_LOCKED BIT(12)
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#define SDXC_START_BIT_ERROR BIT(13)
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#define SDXC_AUTO_COMMAND_DONE BIT(14)
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#define SDXC_END_BIT_ERROR BIT(15)
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#define SDXC_SDIO_INTERRUPT BIT(16)
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#define SDXC_CARD_INSERT BIT(30)
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#define SDXC_CARD_REMOVE BIT(31)
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#define SDXC_INTERRUPT_ERROR_BIT \
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(SDXC_RESP_ERROR | SDXC_RESP_CRC_ERROR | SDXC_DATA_CRC_ERROR | \
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SDXC_RESP_TIMEOUT | SDXC_DATA_TIMEOUT | SDXC_FIFO_RUN_ERROR | \
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SDXC_HARD_WARE_LOCKED | SDXC_START_BIT_ERROR | SDXC_END_BIT_ERROR)
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#define SDXC_INTERRUPT_CMD_ERROR_BIT \
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(SDXC_RESP_ERROR | SDXC_RESP_CRC_ERROR | SDXC_RESP_TIMEOUT)
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#define SDXC_INTERRUPT_DONE_BIT \
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(SDXC_AUTO_COMMAND_DONE | SDXC_DATA_OVER | \
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SDXC_COMMAND_DONE | SDXC_VOLTAGE_CHANGE_DONE)
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#define SDXC_INTERRUPT_DDONE_BIT \
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(SDXC_AUTO_COMMAND_DONE | SDXC_DATA_OVER)
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#define SDXC_SWITCH_DDONE_BIT \
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(SDXC_VOLTAGE_CHANGE_DONE | SDXC_COMMAND_DONE)
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/* status */
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#define SDXC_RXWL_FLAG BIT(0)
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#define SDXC_TXWL_FLAG BIT(1)
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#define SDXC_FIFO_EMPTY BIT(2)
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#define SDXC_FIFO_FULL BIT(3)
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#define SDXC_CARD_PRESENT BIT(8)
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#define SDXC_CARD_DATA_BUSY BIT(9)
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#define SDXC_DATA_FSM_BUSY BIT(10)
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#define SDXC_DMA_REQUEST BIT(31)
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#define SDXC_FIFO_SIZE 16
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/* Function select */
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#define SDXC_CEATA_ON (0xceaa << 16)
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#define SDXC_SEND_IRQ_RESPONSE BIT(0)
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#define SDXC_SDIO_READ_WAIT BIT(1)
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#define SDXC_ABORT_READ_DATA BIT(2)
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#define SDXC_SEND_CCSD BIT(8)
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#define SDXC_SEND_AUTO_STOPCCSD BIT(9)
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#define SDXC_CEATA_DEV_IRQ_ENABLE BIT(10)
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/* IDMA controller bus mod bit field */
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#define SDXC_IDMAC_SOFT_RESET BIT(0)
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#define SDXC_IDMAC_FIX_BURST BIT(1)
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#define SDXC_IDMAC_IDMA_ON BIT(7)
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#define SDXC_IDMAC_REFETCH_DES BIT(31)
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/* IDMA status bit field */
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#define SDXC_IDMAC_TRANSMIT_INTERRUPT BIT(0)
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#define SDXC_IDMAC_RECEIVE_INTERRUPT BIT(1)
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#define SDXC_IDMAC_FATAL_BUS_ERROR BIT(2)
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#define SDXC_IDMAC_DESTINATION_INVALID BIT(4)
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#define SDXC_IDMAC_CARD_ERROR_SUM BIT(5)
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#define SDXC_IDMAC_NORMAL_INTERRUPT_SUM BIT(8)
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#define SDXC_IDMAC_ABNORMAL_INTERRUPT_SUM BIT(9)
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#define SDXC_IDMAC_HOST_ABORT_INTERRUPT BIT(10)
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#define SDXC_IDMAC_IDLE (0 << 13)
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#define SDXC_IDMAC_SUSPEND (1 << 13)
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#define SDXC_IDMAC_DESC_READ (2 << 13)
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#define SDXC_IDMAC_DESC_CHECK (3 << 13)
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#define SDXC_IDMAC_READ_REQUEST_WAIT (4 << 13)
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#define SDXC_IDMAC_WRITE_REQUEST_WAIT (5 << 13)
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#define SDXC_IDMAC_READ (6 << 13)
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#define SDXC_IDMAC_WRITE (7 << 13)
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#define SDXC_IDMAC_DESC_CLOSE (8 << 13)
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/*When one dma des transfer 4k,PAGE_SIZE*4 can transfer max 4M data */
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#define SUNXI_REQ_PAGE_SIZE (PAGE_SIZE*4)
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/*
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* If the idma-des-size-bits of property is ie 13, bufsize bits are:
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* Bits 0-12: buf1 size
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* Bits 13-25: buf2 size
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* Bits 26-31: not used
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* Since we only ever set buf1 size, we can simply store it directly.
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*/
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#define SDXC_IDMAC_DES0_DIC BIT(1) /* disable interrupt on completion */
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#define SDXC_IDMAC_DES0_LD BIT(2) /* last descriptor */
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#define SDXC_IDMAC_DES0_FD BIT(3) /* first descriptor */
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#define SDXC_IDMAC_DES0_CH BIT(4) /* chain mode */
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#define SDXC_IDMAC_DES0_ER BIT(5) /* end of ring */
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#define SDXC_IDMAC_DES0_CES BIT(30) /* card error summary */
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#define SDXC_IDMAC_DES0_OWN BIT(31) /* 1-idma owns it, 0-host owns it */
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void sunxi_dump_reg(struct mmc_host *mmc);
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#if 0
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#define sunxi_r_op(host, op) (\
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{\
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int rval = 0;\
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struct mmc_host *mmc = host->mmc;\
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clk_disable_unprepare(host->clk_mmc);\
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dev_dbg(mmc_dev(mmc), "%s, %d\n", __FUNCTION__, __LINE__);\
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sunxi_dump_reg(mmc);\
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op;\
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rval = clk_prepare_enable(host->clk_mmc);\
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if (rval) {\
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dev_err(mmc_dev(mmc), "Enable mmc clk err %d\n", rval);\
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} \
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rval;\
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} \
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)
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#else
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#define sunxi_r_op(host, op) (\
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{\
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int __ret_val = 0;\
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struct mmc_host *mmc = host->mmc;\
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clk_disable_unprepare(host->clk_mmc);\
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dev_dbg(mmc_dev(mmc), "%s, %d\n", __FUNCTION__, __LINE__);\
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op;\
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__ret_val = clk_prepare_enable(host->clk_mmc);\
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if (__ret_val) {\
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dev_err(mmc_dev(mmc), "Enable mmc clk err %d\n", __ret_val);\
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} \
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__ret_val;\
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} \
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)
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#endif
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enum sunxi_cookie {
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COOKIE_UNMAPPED,
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COOKIE_PRE_MAPPED, /* mapped by sunxi_mmc_pre_req() */
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COOKIE_MAPPED, /* mapped by sunxi_mmc_request() or retry*/
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};
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struct sunxi_idma_des {
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u32 config;
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u32 buf_size;
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u32 buf_addr_ptr1;
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u32 buf_addr_ptr2;
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};
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struct sunxi_mmc_ctrl_regs {
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u32 gctrl;
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u32 clkc;
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u32 timeout;
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u32 buswid;
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u32 waterlvl;
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u32 funcsel;
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u32 debugc;
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u32 idmacc;
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u32 dlba;
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u32 imask;
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};
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struct sunxi_mmc_host_perf{
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ktime_t start;
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int64_t rbytes;
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int64_t wbytes;
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ktime_t rtime;
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ktime_t wtime;
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/***use to compute the time no include busy***/
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int64_t wbytestran;
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ktime_t wtimetran;
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};
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struct sunxi_mmc_host {
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struct mmc_host *mmc;
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struct reset_control *reset;
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/* IO mapping base */
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void __iomem *reg_base;
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/* clock management */
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struct clk *clk_ahb;
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struct clk *clk_mmc;
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struct clk *clk_rst;
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int (*sunxi_mmc_clk_set_rate)(struct sunxi_mmc_host *host,
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struct mmc_ios *ios);
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int crypt_flag;
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/* irq */
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spinlock_t lock;
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int irq;
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u32 int_sum;
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u32 sdio_imask;
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/* dma */
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u32 idma_des_size_bits;
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dma_addr_t sg_dma;
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void *sg_cpu;
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bool wait_dma;
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u32 dma_tl;
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u64 dma_mask;
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void (*sunxi_mmc_thld_ctl)(struct sunxi_mmc_host *host,
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struct mmc_ios *ios,
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struct mmc_data *data);
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struct mmc_request *mrq;
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struct mmc_request *mrq_busy;
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struct mmc_request *mrq_retry;
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struct mmc_request *manual_stop_mrq;
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int ferror;
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u32 power_on;
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u32 time_pwroff_ms;
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/* pinctrl handles */
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struct pinctrl *pinctrl;
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struct pinctrl_state *pins_default;
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struct pinctrl_state *pins_sleep;
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struct pinctrl_state *pins_uart_jtag;
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/*sys node */
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struct device_attribute maual_insert;
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struct device_attribute *dump_register;
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struct device_attribute dump_clk_dly;
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struct device_attribute host_sample_dly;
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struct device_attribute host_ds_dly;
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struct device_attribute host_send_status;
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void (*sunxi_mmc_dump_dly_table)(struct sunxi_mmc_host *host);
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/* backup register structrue */
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struct sunxi_mmc_ctrl_regs bak_regs;
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void (*sunxi_mmc_save_spec_reg)(struct sunxi_mmc_host *host);
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void (*sunxi_mmc_restore_spec_reg)(struct sunxi_mmc_host *host);
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void (*sunxi_mmc_set_acmda)(struct sunxi_mmc_host *host);
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void (*sunxi_mmc_shutdown)(struct platform_device *pdev);
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int (*sunxi_mmc_oclk_en)(struct sunxi_mmc_host *host, u32 oclk_en);
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int (*sunxi_mmc_updata_pha)(struct sunxi_mmc_host *host,
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struct mmc_command *cmd, struct mmc_data *data);
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void (*sunxi_mmc_on_off_emce)(struct sunxi_mmc_host *host,
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u32 en_crypt, u32 ac_mode, u32 en_emce, int data_len,
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int bypass, int task_load);
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bool (*sunxi_mmc_hw_busy)(struct sunxi_mmc_host *host);
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/*really controller id,no logic id */
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int phy_index;
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u32 dat3_imask;
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/*no wait busy if wrtie end, only for customer need */
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#define NO_WBUSY_WR_END 0x1
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#define NO_REINIT_SHUTDOWN 0x2
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#define CARD_PWR_GPIO_HIGH_ACTIVE 0x4
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#define SUNXI_SC_EN_RETRY 0x8
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/**If set this bit,when use sunxi_check_r1_ready_may_sleep,
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*we will wait 0xFFFFFFFF ms, for debug use
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*it is no meant on linux4.4
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*/
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#define SUNXI_R1B_WAIT_MAX 0x10
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/*#define SUNXI_MANUAL_READ_DATA_TIMEOUT 0x20*/
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/*
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*Disable linux kernel native broken cd function,use host defined.
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*Host defined cd function only report true when it detect cd pin change.
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*If not detect cd pin change,it return false.
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*We use it to deal with some bad card which cannot init at all
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*But host defined cd function has a disadvantage that it may not detect card
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*If card is inserted too often.
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*/
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#define SUNXI_DIS_KER_NAT_CD 0x40
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/*#define SUNXI_NO_ERASE 0x80*/
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#define SUNXI_SC_EN_RETRY_CMD 0x100
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#define SUNXI_SC_EN_TIMEOUT_DETECT 0x200
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/*control specal function control,for customer need*/
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u32 ctl_spec_cap;
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int card_pwr_gpio;
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u32 retry_cnt;
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u32 errno_retry;
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int (*sunxi_mmc_judge_retry)(struct sunxi_mmc_host *host,
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struct mmc_command *cmd, u32 rcnt,
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u32 errno, void *other);
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u32 sunxi_ds_dl;
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u32 sunxi_samp_dl;
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u32 sunxi_ds_dl_cnt;
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u32 sunxi_samp_dl_cnt;
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/*only use for MMC_CAP_NEEDS_POLL and SUNXI_DIS_KER_NAT_CD is on*/
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u32 present;
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u32 voltage_switching;
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bool perf_enable;
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struct device_attribute host_perf;
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struct sunxi_mmc_host_perf perf;
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struct device_attribute filter_sector_perf;
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struct device_attribute filter_speed_perf;
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unsigned int filter_sector;
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unsigned int filter_speed;
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struct device_attribute host_mwr;
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void *version_priv_dat;
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/*auto command 23 operate*/
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/*set auto cmd 23 val and enable bit,or get respose*/
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bool (*sunxi_mmc_opacmd23)(struct sunxi_mmc_host *host, bool set, u32 arg, u32 *rep);
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/*sample fifo contral */
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bool sfc_dis;
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/*des phy address shift,use for over 4G phy ddrest*/
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size_t des_addr_shift;
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char name[32];
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struct delayed_work sunxi_timerout_work;
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};
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/*the struct as the the kernel version changes,which copy form core/slot-gpio.c*/
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struct mmc_gpio {
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struct gpio_desc *ro_gpio;
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struct gpio_desc *cd_gpio;
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bool override_ro_active_level;
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bool override_cd_active_level;
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irqreturn_t (*cd_gpio_isr)(int irq, void *dev_id);
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char *ro_label;
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char cd_label[0];
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};
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/*use to check ddr mode,not include hs400*/
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#define sunxi_mmc_ddr_timing(it) \
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(((it) == MMC_TIMING_UHS_DDR50) || ((it) == MMC_TIMING_MMC_DDR52))
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void sunxi_mmc_set_a12a(struct sunxi_mmc_host *host);
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void sunxi_mmc_do_shutdown_com(struct platform_device *pdev);
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extern int mmc_go_idle(struct mmc_host *host);
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extern int mmc_send_op_cond(struct mmc_host *host, u32 ocr, u32 *rocr);
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extern int mmc_send_status(struct mmc_card *card, u32 *status);
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extern void mmc_set_clock(struct mmc_host *host, unsigned int hz);
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extern void mmc_set_timing(struct mmc_host *host, unsigned int timing);
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extern void mmc_set_bus_width(struct mmc_host *host, unsigned int width);
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extern int sunxi_sel_pio_mode(struct pinctrl *pinctrl, u32 pm_sel);
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#endif
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