/*
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* Sunxi SD/MMC host driver
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*
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* Copyright (C) 2015 AllWinnertech Ltd.
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* Author: lixiang <lixiang@allwinnertech>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifdef CONFIG_ARCH_SUN50IW1P1
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#include <linux/clk.h>
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#include <linux/clk/sunxi.h>
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#include <linux/gpio.h>
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#include <linux/platform_device.h>
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#include <linux/spinlock.h>
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#include <linux/scatterlist.h>
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#include <linux/dma-mapping.h>
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#include <linux/slab.h>
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#include <linux/reset.h>
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#include <linux/of_address.h>
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#include <linux/of_gpio.h>
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#include <linux/of_platform.h>
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#include <linux/mmc/host.h>
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#include <linux/mmc/sd.h>
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#include <linux/mmc/sdio.h>
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#include <linux/mmc/mmc.h>
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#include <linux/mmc/core.h>
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#include <linux/mmc/card.h>
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#include <linux/mmc/slot-gpio.h>
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#include "sunxi-mmc.h"
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#include "sunxi-mmc-sun50iw1p1-2.h"
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/*reg*/
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/*SMHC eMMC4.5 DDR Start Bit Detection Control Register */
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/*SMHC CRC Status Detect Control Register */
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/*SMHC Card Threshold Control Register */
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/*SMHC Drive Delay Control Register */
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/*SMHC Sample Delay Control Register */
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/*SMHC Data Strobe Delay Control Register */
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#define SDXC_REG_EDSD (0x010C)
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#define SDXC_REG_CSDC (0x0054)
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#define SDXC_REG_THLD (0x0100)
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#define SDXC_REG_DRV_DL (0x0140)
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#define SDXC_REG_SAMP_DL (0x0144)
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#define SDXC_REG_DS_DL (0x0148)
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/*bit*/
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#define SDXC_HS400_MD_EN (1U<<31)
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#define SDXC_CARD_WR_THLD_ENB (1U<<2)
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#define SDXC_CARD_RD_THLD_ENB (1U)
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#define SDXC_DAT_DRV_PH_SEL (1U<<17)
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#define SDXC_CMD_DRV_PH_SEL (1U<<16)
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#define SDXC_SAMP_DL_SW_EN (1u<<7)
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#define SDXC_DS_DL_SW_EN (1u<<7)
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/*mask*/
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#define SDXC_CRC_DET_PARA_MASK (0xf)
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#define SDXC_CARD_RD_THLD_MASK (0x0FFF0000)
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#define SDXC_TX_TL_MASK (0xff)
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#define SDXC_RX_TL_MASK (0x00FF0000)
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#define SDXC_SAMP_DL_SW_MASK (0x0000003F)
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#define SDXC_DS_DL_SW_MASK (0x0000003F)
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/*value*/
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#define SDXC_CRC_DET_PARA_HS400 (6)
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#define SDXC_CRC_DET_PARA_OTHER (3)
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#define SDXC_FIFO_DETH (1024>>2)
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/*size*/
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#define SDXC_CARD_RD_THLD_SIZE (0x00000FFF)
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/*shit*/
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#define SDXC_CARD_RD_THLD_SIZE_SHIFT (16)
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struct sunxi_mmc_spec_regs {
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u32 drv_dl; /*REG_DRV_DL */
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u32 samp_dl; /*REG_SAMP_DL */
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u32 ds_dl; /*REG_DS_DL */
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/*u32 sd_ntsr;//REG_SD_NTSR */
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u32 edsd; /*REG_EDSD */
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u32 csdc; /*REG_CSDC */
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};
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static struct sunxi_mmc_spec_regs bak_spec_regs;
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enum sunxi_mmc_speed_mode {
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SM0_DS26_SDR12 = 0,
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SM1_HSSDR52_SDR25,
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SM2_HSDDR52_DDR50,
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SM3_HS200_SDR104,
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SM4_HS400,
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SM_NUM,
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};
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struct sunxi_mmc_clk_dly {
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enum sunxi_mmc_speed_mode spm;
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char *mod_str;
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char *raw_tm_sm_str[2];
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u32 raw_tm_sm[2];
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u32 raw_tm_sm_def[2];
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};
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static struct sunxi_mmc_clk_dly mmc_clk_dly[SM_NUM] = {
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[SM0_DS26_SDR12] = {
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.spm = SM0_DS26_SDR12,
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.mod_str = "DS26_SDR12",
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.raw_tm_sm_str[0] = "sdc_tm4_sm0_freq0",
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.raw_tm_sm_str[1] = "sdc_tm4_sm0_freq1",
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.raw_tm_sm[0] = 0,
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.raw_tm_sm[1] = 0,
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.raw_tm_sm_def[0] = 0,
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.raw_tm_sm_def[1] = 0,
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},
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[SM1_HSSDR52_SDR25] = {
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.spm = SM1_HSSDR52_SDR25,
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.mod_str = "HSSDR52_SDR25",
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.raw_tm_sm_str[0] = "sdc_tm4_sm1_freq0",
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.raw_tm_sm_str[1] = "sdc_tm4_sm1_freq1",
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.raw_tm_sm[0] = 0,
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.raw_tm_sm[1] = 0,
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.raw_tm_sm_def[0] = 0,
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.raw_tm_sm_def[1] = 0,
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},
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[SM2_HSDDR52_DDR50] = {
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.spm = SM2_HSDDR52_DDR50,
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.mod_str = "HSDDR52_DDR50",
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.raw_tm_sm_str[0] = "sdc_tm4_sm2_freq0",
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.raw_tm_sm_str[1] = "sdc_tm4_sm2_freq1",
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.raw_tm_sm[0] = 0,
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.raw_tm_sm[1] = 0,
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.raw_tm_sm_def[0] = 0,
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.raw_tm_sm_def[1] = 0,
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},
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[SM3_HS200_SDR104] = {
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.spm = SM3_HS200_SDR104,
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.mod_str = "HS200_SDR104",
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.raw_tm_sm_str[0] = "sdc_tm4_sm3_freq0",
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.raw_tm_sm_str[1] = "sdc_tm4_sm3_freq1",
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.raw_tm_sm[0] = 0,
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.raw_tm_sm[1] = 0,
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.raw_tm_sm_def[0] = 0,
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.raw_tm_sm_def[1] = 0x00000405,
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},
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[SM4_HS400] = {
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.spm = SM4_HS400,
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.mod_str = "HS400",
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.raw_tm_sm_str[0] = "sdc_tm4_sm4_freq0",
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.raw_tm_sm_str[1] = "sdc_tm4_sm4_freq1",
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.raw_tm_sm[0] = 0,
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.raw_tm_sm[1] = 0x00000608,
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.raw_tm_sm_def[0] = 0,
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.raw_tm_sm_def[1] = 0x00000408,
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},
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};
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static void sunxi_mmc_set_clk_dly(struct sunxi_mmc_host *host, int clk,
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int bus_width, int timing)
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{
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struct mmc_host *mmc = host->mmc;
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enum sunxi_mmc_speed_mode speed_mod = SM0_DS26_SDR12;
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char *raw_sm_str = NULL;
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char *m_str = NULL;
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struct device_node *np = NULL;
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u32 *raw_sm = 0;
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u32 *raw_sm_def = 0;
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u32 rval = 0;
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int frq_index = 0;
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u32 cmd_drv_ph = 1;
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u32 dat_drv_ph = 0;
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u32 sam_dly = 0;
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u32 ds_dly = 0;
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if (!mmc->parent || !mmc->parent->of_node) {
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dev_err(mmc_dev(host->mmc),
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"no dts to parse clk dly,use default\n");
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return;
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}
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np = mmc->parent->of_node;
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switch (timing) {
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case MMC_TIMING_LEGACY:
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case MMC_TIMING_UHS_SDR12:
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speed_mod = SM0_DS26_SDR12;
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break;
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case MMC_TIMING_MMC_HS:
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case MMC_TIMING_SD_HS:
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case MMC_TIMING_UHS_SDR25:
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speed_mod = SM1_HSSDR52_SDR25;
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break;
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case MMC_TIMING_UHS_DDR50:
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case MMC_TIMING_MMC_DDR52:
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speed_mod = SM2_HSDDR52_DDR50;
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dat_drv_ph = 1;
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break;
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case MMC_TIMING_UHS_SDR50:
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case MMC_TIMING_UHS_SDR104:
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case MMC_TIMING_MMC_HS200:
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speed_mod = SM3_HS200_SDR104;
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break;
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case MMC_TIMING_MMC_HS400:
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speed_mod = SM4_HS400;
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break;
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default:
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dev_err(mmc_dev(mmc), "Wrong timing input\n");
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return;
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}
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if (clk <= 400 * 1000) {
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frq_index = 0;
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} else if (clk <= 25 * 1000 * 1000) {
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frq_index = 1;
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} else if (clk <= 50 * 1000 * 1000) {
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frq_index = 2;
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} else if (clk <= 100 * 1000 * 1000) {
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frq_index = 3;
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} else if (clk <= 150 * 1000 * 1000) {
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frq_index = 4;
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} else if (clk <= 200 * 1000 * 1000) {
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frq_index = 5;
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} else if (clk <= 250 * 1000 * 1000) {
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frq_index = 6;
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} else if (clk <= 300 * 1000 * 1000) {
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frq_index = 7;
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} else {
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dev_err(mmc_dev(mmc), "clk is over 300mhz\n");
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return;
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}
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if (frq_index / 4 > 2) {
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dev_err(mmc_dev(host->mmc), "err frq_index\n");
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return;
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}
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dev_dbg(mmc_dev(host->mmc), "freq %d frq index %d,frq/4 %x\n", clk,
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frq_index, frq_index / 4);
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raw_sm_str = mmc_clk_dly[speed_mod].raw_tm_sm_str[frq_index / 4];
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raw_sm = &mmc_clk_dly[speed_mod].raw_tm_sm[frq_index / 4];
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raw_sm_def = &mmc_clk_dly[speed_mod].raw_tm_sm_def[frq_index / 4];
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m_str = mmc_clk_dly[speed_mod].mod_str;
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rval = of_property_read_u32(np, raw_sm_str, raw_sm);
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if (rval) {
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dev_info(mmc_dev(host->mmc), "failded to get %s used default\n",
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m_str);
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} else {
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u32 sm_shift = (frq_index % 4) * 8;
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rval = ((*raw_sm) >> sm_shift) & 0xff;
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if (rval != 0xff) {
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if (timing == MMC_TIMING_MMC_HS400) {
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u32 raw_sm_hs200 = 0;
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ds_dly = rval;
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raw_sm_hs200 =
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mmc_clk_dly[SM3_HS200_SDR104].
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raw_tm_sm[frq_index / 4];
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sam_dly = ((raw_sm_hs200) >> sm_shift) & 0xff;
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} else {
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sam_dly = rval;
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}
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dev_dbg(mmc_dev(host->mmc),
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"Get speed mode %s clk dly %s ok\n", m_str,
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raw_sm_str);
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} else {
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u32 sm_shift = (frq_index % 4) * 8;
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dev_dbg(mmc_dev(host->mmc), "%s use default value\n",
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m_str);
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rval = ((*raw_sm_def) >> sm_shift) & 0xff;
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if (timing == MMC_TIMING_MMC_HS400) {
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u32 raw_sm_hs200 = 0;
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ds_dly = rval;
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raw_sm_hs200 =
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mmc_clk_dly[SM3_HS200_SDR104].
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raw_tm_sm_def[frq_index / 4];
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sam_dly = ((raw_sm_hs200) >> sm_shift) & 0xff;
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} else {
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sam_dly = rval;
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}
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}
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}
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dev_dbg(mmc_dev(host->mmc), "Try set %s clk dly ok\n", m_str);
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dev_dbg(mmc_dev(host->mmc), "cmd_drv_ph %d\n", cmd_drv_ph);
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dev_dbg(mmc_dev(host->mmc), "dat_drv_ph %d\n", dat_drv_ph);
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dev_dbg(mmc_dev(host->mmc), "sam_dly %d\n", sam_dly);
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dev_dbg(mmc_dev(host->mmc), "ds_dly %d\n", ds_dly);
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rval = mmc_readl(host, REG_DRV_DL);
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if (cmd_drv_ph)
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rval |= SDXC_CMD_DRV_PH_SEL; /*180 phase */
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else
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rval &= ~SDXC_CMD_DRV_PH_SEL; /*90 phase */
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if (dat_drv_ph)
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rval |= SDXC_DAT_DRV_PH_SEL; /*180 phase */
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else
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rval &= ~SDXC_DAT_DRV_PH_SEL; /*90 phase */
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sunxi_r_op(host, mmc_writel(host, REG_DRV_DL, rval));
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rval = mmc_readl(host, REG_SAMP_DL);
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rval &= ~SDXC_SAMP_DL_SW_MASK;
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rval |= sam_dly & SDXC_SAMP_DL_SW_MASK;
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rval |= SDXC_SAMP_DL_SW_EN;
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mmc_writel(host, REG_SAMP_DL, rval);
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rval = mmc_readl(host, REG_DS_DL);
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rval &= ~SDXC_DS_DL_SW_MASK;
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rval |= ds_dly & SDXC_DS_DL_SW_MASK;
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rval |= SDXC_DS_DL_SW_EN;
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mmc_writel(host, REG_DS_DL, rval);
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dev_dbg(mmc_dev(host->mmc), " REG_DRV_DL %08x\n",
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mmc_readl(host, REG_DRV_DL));
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dev_dbg(mmc_dev(host->mmc), " REG_SAMP_DL %08x\n",
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mmc_readl(host, REG_SAMP_DL));
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dev_dbg(mmc_dev(host->mmc), " REG_DS_DL %08x\n",
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mmc_readl(host, REG_DS_DL));
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}
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void sunxi_mmc_dump_dly2(struct sunxi_mmc_host *host)
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{
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int i = 0;
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for (i = 0; i < SM_NUM; i++) {
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pr_info("mod_str %s\n", mmc_clk_dly[i].mod_str);
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pr_info("raw_tm_sm_str %s\n", mmc_clk_dly[i].raw_tm_sm_str[0]);
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pr_info("raw_tm_sm_str %s\n", mmc_clk_dly[i].raw_tm_sm_str[1]);
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pr_info("raw_tm_sm0 %x\n", mmc_clk_dly[i].raw_tm_sm[0]);
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pr_info("raw_tm_sm1 %x\n", mmc_clk_dly[i].raw_tm_sm[1]);
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pr_info("********************\n");
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}
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}
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static int __sunxi_mmc_do_oclk_onoff(struct sunxi_mmc_host *host, u32 oclk_en,
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u32 pwr_save, u32 ignore_dat0)
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{
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unsigned long expire = jiffies + msecs_to_jiffies(250);
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u32 rval;
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rval = mmc_readl(host, REG_CLKCR);
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rval &= ~(SDXC_CARD_CLOCK_ON | SDXC_LOW_POWER_ON | SDXC_MASK_DATA0);
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if (oclk_en)
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rval |= SDXC_CARD_CLOCK_ON;
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if (pwr_save)
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rval |= SDXC_LOW_POWER_ON;
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if (ignore_dat0)
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rval |= SDXC_MASK_DATA0;
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mmc_writel(host, REG_CLKCR, rval);
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dev_dbg(mmc_dev(host->mmc), "%s REG_CLKCR:%x\n", __func__,
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mmc_readl(host, REG_CLKCR));
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rval = SDXC_START | SDXC_UPCLK_ONLY | SDXC_WAIT_PRE_OVER;
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mmc_writel(host, REG_CMDR, rval);
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do {
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rval = mmc_readl(host, REG_CMDR);
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} while (time_before(jiffies, expire) && (rval & SDXC_START));
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/* clear irq status bits set by the command */
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/*? */
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mmc_writel(host, REG_RINTR,
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mmc_readl(host, REG_RINTR) & ~SDXC_SDIO_INTERRUPT);
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if (rval & SDXC_START) {
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dev_err(mmc_dev(host->mmc), "fatal err update clk timeout\n");
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return -EIO;
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}
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/*only use mask data0 when update clk,clear it when not update clk */
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if (ignore_dat0)
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mmc_writel(host, REG_CLKCR,
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mmc_readl(host, REG_CLKCR) & ~SDXC_MASK_DATA0);
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return 0;
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}
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static int sunxi_mmc_oclk_onoff(struct sunxi_mmc_host *host, u32 oclk_en)
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{
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struct device_node *np = NULL;
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struct mmc_host *mmc = host->mmc;
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int pwr_save = 0;
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int len = 0;
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if (!mmc->parent || !mmc->parent->of_node) {
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dev_err(mmc_dev(host->mmc),
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"no dts to parse power save mode\n");
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return -EIO;
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}
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np = mmc->parent->of_node;
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if (of_find_property(np, "sunxi-power-save-mode", &len))
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pwr_save = 1;
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return __sunxi_mmc_do_oclk_onoff(host, oclk_en, pwr_save, 1);
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}
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int sunxi_mmc_oclk_onoff_sdmmc2(struct sunxi_mmc_host *host, u32 oclk_en)
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{
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return sunxi_mmc_oclk_onoff(host, oclk_en);
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}
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int sunxi_mmc_clk_set_rate_for_sdmmc2(struct sunxi_mmc_host *host,
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struct mmc_ios *ios)
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{
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u32 mod_clk = 0;
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u32 src_clk = 0;
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u32 rval = 0;
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s32 err = 0;
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u32 rate = 0;
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char *sclk_name = NULL;
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struct clk *mclk = host->clk_mmc;
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struct clk *sclk = NULL;
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struct device *dev = mmc_dev(host->mmc);
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int div = 0;
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if (ios->clock == 0) {
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__sunxi_mmc_do_oclk_onoff(host, 0, 0, 1);
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return 0;
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}
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if ((ios->bus_width == MMC_BUS_WIDTH_8)
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&& (ios->timing == MMC_TIMING_MMC_DDR52)
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) {
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mod_clk = ios->clock << 2;
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div = 1;
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} else {
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mod_clk = ios->clock << 1;
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div = 0;
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}
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if (ios->clock <= 400000) {
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sclk = clk_get(dev, "osc24m");
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sclk_name = "osc24m";
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} else {
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sclk = clk_get(dev, "pll_periph");
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sclk_name = "pll_periph";
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}
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if (IS_ERR(sclk)) {
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dev_err(mmc_dev(host->mmc), "Error to get source clock %s\n",
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sclk_name);
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return -1;
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}
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sunxi_mmc_oclk_onoff(host, 0);
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err = clk_set_parent(mclk, sclk);
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if (err) {
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dev_err(mmc_dev(host->mmc), "set parent failed\n");
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clk_put(sclk);
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return -1;
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}
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rate = clk_round_rate(mclk, mod_clk);
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dev_dbg(mmc_dev(host->mmc), "get round rate %d\n", rate);
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clk_disable_unprepare(host->clk_mmc);
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err = clk_set_rate(mclk, rate);
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if (err) {
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dev_err(mmc_dev(host->mmc), "set mclk rate error, rate %dHz\n",
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rate);
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clk_put(sclk);
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return -1;
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}
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rval = clk_prepare_enable(host->clk_mmc);
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if (rval) {
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dev_err(mmc_dev(host->mmc), "Enable mmc clk err %d\n", rval);
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return -1;
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}
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src_clk = clk_get_rate(sclk);
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clk_put(sclk);
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dev_dbg(mmc_dev(host->mmc), "set round clock %d, soure clk is %d\n",
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rate, src_clk);
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#ifdef MMC_FPGA
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if ((ios->bus_width == MMC_BUS_WIDTH_8)
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&& (ios->timing == MMC_TIMING_MMC_DDR52)
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) {
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/* clear internal divider */
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rval = mmc_readl(host, REG_CLKCR);
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rval &= ~0xff;
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rval |= 1;
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} else {
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/* support internal divide clock under fpga environment */
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rval = mmc_readl(host, REG_CLKCR);
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rval &= ~0xff;
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rval |= 24000000 / mod_clk / 2; /* =24M/400K/2=0x1E*/
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}
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mmc_writel(host, REG_CLKCR, rval);
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dev_info(mmc_dev(host->mmc), "--FPGA REG_CLKCR: 0x%08x\n",
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mmc_readl(host, REG_CLKCR));
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#else
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/* clear internal divider */
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rval = mmc_readl(host, REG_CLKCR);
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rval &= ~0xff;
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rval |= div;
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mmc_writel(host, REG_CLKCR, rval);
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#endif
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if ((ios->bus_width == MMC_BUS_WIDTH_8)
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&& (ios->timing == MMC_TIMING_MMC_HS400)
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) {
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rval = mmc_readl(host, REG_EDSD);
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rval |= SDXC_HS400_MD_EN;
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mmc_writel(host, REG_EDSD, rval);
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rval = mmc_readl(host, REG_CSDC);
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rval &= ~SDXC_CRC_DET_PARA_MASK;
|
rval |= SDXC_CRC_DET_PARA_HS400;
|
mmc_writel(host, REG_CSDC, rval);
|
} else {
|
rval = mmc_readl(host, REG_EDSD);
|
rval &= ~SDXC_HS400_MD_EN;
|
mmc_writel(host, REG_EDSD, rval);
|
rval = mmc_readl(host, REG_CSDC);
|
rval &= ~SDXC_CRC_DET_PARA_MASK;
|
rval |= SDXC_CRC_DET_PARA_OTHER;
|
mmc_writel(host, REG_CSDC, rval);
|
}
|
dev_dbg(mmc_dev(host->mmc), "SDXC_REG_EDSD: 0x%08x\n",
|
mmc_readl(host, REG_EDSD));
|
dev_dbg(mmc_dev(host->mmc), "SDXC_REG_CSDC: 0x%08x\n",
|
mmc_readl(host, REG_CSDC));
|
|
if ((ios->bus_width == MMC_BUS_WIDTH_8)
|
&& (ios->timing == MMC_TIMING_MMC_DDR52)
|
) {
|
ios->clock = rate >> 2;
|
} else {
|
ios->clock = rate >> 1;
|
}
|
|
sunxi_mmc_set_clk_dly(host, ios->clock, ios->bus_width, ios->timing);
|
|
return sunxi_mmc_oclk_onoff(host, 1);
|
}
|
|
void sunxi_mmc_thld_ctl_for_sdmmc2(struct sunxi_mmc_host *host,
|
struct mmc_ios *ios, struct mmc_data *data)
|
{
|
u32 bsz = data->blksz;
|
/*unit:byte */
|
u32 tdtl = (host->dma_tl & SDXC_TX_TL_MASK) << 2;
|
/*unit:byte */
|
u32 rdtl = ((host->dma_tl & SDXC_RX_TL_MASK) >> 16) << 2;
|
u32 rval = 0;
|
|
if ((data->flags & MMC_DATA_WRITE)
|
&& (bsz <= SDXC_CARD_RD_THLD_SIZE)
|
&& (bsz <= tdtl)) {
|
rval = mmc_readl(host, REG_THLD);
|
rval &= ~SDXC_CARD_RD_THLD_MASK;
|
rval |= data->blksz << SDXC_CARD_RD_THLD_SIZE_SHIFT;
|
rval |= SDXC_CARD_WR_THLD_ENB;
|
mmc_writel(host, REG_THLD, rval);
|
} else {
|
rval = mmc_readl(host, REG_THLD);
|
rval &= ~SDXC_CARD_WR_THLD_ENB;
|
mmc_writel(host, REG_THLD, rval);
|
}
|
|
if ((data->flags & MMC_DATA_READ)
|
&& (bsz <= SDXC_CARD_RD_THLD_SIZE)
|
/*((SDXC_FIFO_DETH<<2)-bsz) >= (rdtl) */
|
&& ((SDXC_FIFO_DETH << 2) >= (rdtl + bsz))
|
&& ((ios->timing == MMC_TIMING_MMC_HS200)
|
|| (ios->timing == MMC_TIMING_MMC_HS400))) {
|
rval = mmc_readl(host, REG_THLD);
|
rval &= ~SDXC_CARD_RD_THLD_MASK;
|
rval |= data->blksz << SDXC_CARD_RD_THLD_SIZE_SHIFT;
|
rval |= SDXC_CARD_RD_THLD_ENB;
|
mmc_writel(host, REG_THLD, rval);
|
} else {
|
rval = mmc_readl(host, REG_THLD);
|
rval &= ~SDXC_CARD_RD_THLD_ENB;
|
mmc_writel(host, REG_THLD, rval);
|
}
|
|
dev_dbg(mmc_dev(host->mmc), "--SDXC_REG_THLD: 0x%08x\n",
|
mmc_readl(host, REG_THLD));
|
|
}
|
|
void sunxi_mmc_save_spec_reg2(struct sunxi_mmc_host *host)
|
{
|
bak_spec_regs.drv_dl = mmc_readl(host, REG_DRV_DL);
|
bak_spec_regs.samp_dl = mmc_readl(host, REG_SAMP_DL);
|
bak_spec_regs.ds_dl = mmc_readl(host, REG_DS_DL);
|
/*bak_spec_regs.sd_ntsr = mmc_readl(host,REG_SD_NTSR);*/
|
bak_spec_regs.edsd = mmc_readl(host, REG_EDSD);
|
bak_spec_regs.csdc = mmc_readl(host, REG_CSDC);
|
}
|
|
void sunxi_mmc_restore_spec_reg2(struct sunxi_mmc_host *host)
|
{
|
sunxi_r_op(host, mmc_writel(host, REG_DRV_DL, bak_spec_regs.drv_dl));
|
mmc_writel(host, REG_SAMP_DL, bak_spec_regs.samp_dl);
|
mmc_writel(host, REG_DS_DL, bak_spec_regs.ds_dl);
|
/*mmc_writel(host,REG_SD_NTSR,bak_spec_regs.sd_ntsr);*/
|
mmc_writel(host, REG_EDSD, bak_spec_regs.edsd);
|
mmc_writel(host, REG_CSDC, bak_spec_regs.csdc);
|
}
|
#endif
|
