/*
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* sunxi iommu: main structures
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*
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* Copyright (C) 2008-2009 Nokia Corporation
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*
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* Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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/*
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* Register of IOMMU device
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*/
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#define IOMMU_VERSION_REG 0x0000
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#define IOMMU_RESET_REG 0x0010
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#define IOMMU_ENABLE_REG 0x0020
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#define IOMMU_BYPASS_REG 0x0030
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#define IOMMU_AUTO_GATING_REG 0x0040
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#define IOMMU_WBUF_CTRL_REG 0x0044
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#define IOMMU_OOO_CTRL_REG 0x0048
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#define IOMMU_4KB_BDY_PRT_CTRL_REG 0x004C
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#define IOMMU_TTB_REG 0x0050
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#define IOMMU_TLB_ENABLE_REG 0x0060
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#define IOMMU_TLB_PREFETCH_REG 0x0070
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#define IOMMU_TLB_FLUSH_ENABLE_REG 0x0080
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#define IOMMU_TLB_IVLD_MODE_SEL_REG 0x0084
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#define IOMMU_TLB_IVLD_START_ADDR_REG 0x0088
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#define IOMMU_TLB_IVLD_END_ADDR_REG 0x008C
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#define IOMMU_TLB_IVLD_ADDR_REG 0x0090
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#define IOMMU_TLB_IVLD_ADDR_MASK_REG 0x0094
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#define IOMMU_TLB_IVLD_ENABLE_REG 0x0098
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#define IOMMU_PC_IVLD_MODE_SEL_REG 0x009C
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#define IOMMU_PC_IVLD_ADDR_REG 0x00A0
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#define IOMMU_PC_IVLD_START_ADDR_REG 0x00A4
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#define IOMMU_PC_IVLD_ENABLE_REG 0x00A8
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#define IOMMU_PC_IVLD_END_ADDR_REG 0x00Ac
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#define IOMMU_DM_AUT_CTRL_REG0 0x00B0
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#define IOMMU_DM_AUT_CTRL_REG1 0x00B4
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#define IOMMU_DM_AUT_CTRL_REG2 0x00B8
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#define IOMMU_DM_AUT_CTRL_REG3 0x00BC
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#define IOMMU_DM_AUT_CTRL_REG4 0x00C0
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#define IOMMU_DM_AUT_CTRL_REG5 0x00C4
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#define IOMMU_DM_AUT_CTRL_REG6 0x00C8
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#define IOMMU_DM_AUT_CTRL_REG7 0x00CC
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#define IOMMU_DM_AUT_OVWT_REG 0x00D0
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#define IOMMU_INT_ENABLE_REG 0x0100
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#define IOMMU_INT_CLR_REG 0x0104
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#define IOMMU_INT_STA_REG 0x0108
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#define IOMMU_INT_ERR_ADDR_REG0 0x0110
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#define IOMMU_INT_ERR_ADDR_REG1 0x0114 /**/
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#define IOMMU_INT_ERR_ADDR_REG2 0x0118 /**/
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#define IOMMU_INT_ERR_ADDR_REG3 0x011C
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#define IOMMU_INT_ERR_ADDR_REG4 0x0120
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#define IOMMU_INT_ERR_ADDR_REG5 0x0124
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#if defined(CONFIG_ARCH_SUN8IW15) || defined(CONFIG_ARCH_SUN50IW9) \
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|| defined(CONFIG_ARCH_SUN8IW19) || defined(CONFIG_ARCH_SUN50IW10)
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#define IOMMU_INT_ERR_ADDR_REG6 0x0128
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#define IOMMU_INT_ERR_ADDR_REG7 0x0130
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#define IOMMU_INT_ERR_ADDR_REG8 0x0134
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#else
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#define IOMMU_INT_ERR_ADDR_REG6 0x0130
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#define IOMMU_INT_ERR_ADDR_REG7 0x0134
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#endif
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#define IOMMU_INT_ERR_DATA_REG0 0x0150
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#define IOMMU_INT_ERR_DATA_REG1 0x0154 /**/
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#define IOMMU_INT_ERR_DATA_REG2 0x0158 /**/
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#define IOMMU_INT_ERR_DATA_REG3 0x015C
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#define IOMMU_INT_ERR_DATA_REG4 0x0160
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#define IOMMU_INT_ERR_DATA_REG5 0x0164
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#if defined(CONFIG_ARCH_SUN8IW15) || defined(CONFIG_ARCH_SUN50IW9) \
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|| defined(CONFIG_ARCH_SUN8IW19) || defined(CONFIG_ARCH_SUN50IW10)
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#define IOMMU_INT_ERR_DATA_REG6 0x0168
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#define IOMMU_INT_ERR_DATA_REG7 0x0170
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#define IOMMU_INT_ERR_DATA_REG8 0x0174
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#else
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#define IOMMU_INT_ERR_DATA_REG6 0x0170
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#define IOMMU_INT_ERR_DATA_REG7 0x0174
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#endif
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#define IOMMU_L1PG_INT_REG 0x0180
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#define IOMMU_L2PG_INT_REG 0x0184
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#define IOMMU_VA_REG 0x0190
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#define IOMMU_VA_DATA_REG 0x0194
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#define IOMMU_VA_CONFIG_REG 0x0198
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#define IOMMU_PMU_ENABLE_REG 0x0200
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#define IOMMU_PMU_CLR_REG 0x0210
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#define IOMMU_PMU_ACCESS_LOW_REG0 0x0230
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#define IOMMU_PMU_ACCESS_HIGH_REG0 0x0234
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#define IOMMU_PMU_HIT_LOW_REG0 0x0238
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#define IOMMU_PMU_HIT_HIGH_REG0 0x023C
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#define IOMMU_PMU_ACCESS_LOW_REG1 0x0240 /**/
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#define IOMMU_PMU_ACCESS_HIGH_REG1 0x0244 /**/
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#define IOMMU_PMU_HIT_LOW_REG1 0x0248 /**/
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#define IOMMU_PMU_HIT_HIGH_REG1 0x024C /**/
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#define IOMMU_PMU_ACCESS_LOW_REG2 0x0250
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#define IOMMU_PMU_ACCESS_HIGH_REG2 0x0254
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#define IOMMU_PMU_HIT_LOW_REG2 0x0258
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#define IOMMU_PMU_HIT_HIGH_REG2 0x025C
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#define IOMMU_PMU_ACCESS_LOW_REG3 0x0260
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#define IOMMU_PMU_ACCESS_HIGH_REG3 0x0264
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#define IOMMU_PMU_HIT_LOW_REG3 0x0268
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#define IOMMU_PMU_HIT_HIGH_REG3 0x026C
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#define IOMMU_PMU_ACCESS_LOW_REG4 0x0270
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#define IOMMU_PMU_ACCESS_HIGH_REG4 0x0274
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#define IOMMU_PMU_HIT_LOW_REG4 0x0278
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#define IOMMU_PMU_HIT_HIGH_REG4 0x027C
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#define IOMMU_PMU_ACCESS_LOW_REG5 0x0280
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#define IOMMU_PMU_ACCESS_HIGH_REG5 0x0284
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#define IOMMU_PMU_HIT_LOW_REG5 0x0288
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#define IOMMU_PMU_HIT_HIGH_REG5 0x028C
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#if defined(CONFIG_ARCH_SUN8IW15) || defined(CONFIG_ARCH_SUN50IW9) \
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|| defined(CONFIG_ARCH_SUN8IW19) || defined(CONFIG_ARCH_SUN50IW10)
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#define IOMMU_PMU_ACCESS_LOW_REG6 0x0290
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#define IOMMU_PMU_ACCESS_HIGH_REG6 0x0294
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#define IOMMU_PMU_HIT_LOW_REG6 0x0298
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#define IOMMU_PMU_HIT_HIGH_REG6 0x029C
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#define IOMMU_PMU_ACCESS_LOW_REG7 0x02D0
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#define IOMMU_PMU_ACCESS_HIGH_REG7 0x02D4
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#define IOMMU_PMU_HIT_LOW_REG7 0x02D8
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#define IOMMU_PMU_HIT_HIGH_REG7 0x02DC
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#define IOMMU_PMU_ACCESS_LOW_REG8 0x02E0
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#define IOMMU_PMU_ACCESS_HIGH_REG8 0x02E4
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#define IOMMU_PMU_HIT_LOW_REG8 0x02E8
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#define IOMMU_PMU_HIT_HIGH_REG8 0x02EC
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#else
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#define IOMMU_PMU_ACCESS_LOW_REG6 0x02D0
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#define IOMMU_PMU_ACCESS_HIGH_REG6 0x02D4
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#define IOMMU_PMU_HIT_LOW_REG6 0x02D8
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#define IOMMU_PMU_HIT_HIGH_REG6 0x02DC
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#define IOMMU_PMU_ACCESS_LOW_REG7 0x02E0
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#define IOMMU_PMU_ACCESS_HIGH_REG7 0x02E4
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#define IOMMU_PMU_HIT_LOW_REG7 0x02E8
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#define IOMMU_PMU_HIT_HIGH_REG7 0x02EC
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#endif
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#define IOMMU_PMU_TL_LOW_REG0 0x0300
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#define IOMMU_PMU_TL_HIGH_REG0 0x0304
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#if defined(CONFIG_ARCH_SUN8IW15) || defined(CONFIG_ARCH_SUN50IW9) \
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|| defined(CONFIG_ARCH_SUN8IW19) || defined(CONFIG_ARCH_SUN50IW10)
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#define IOMMU_PMU_ML_REG0 0x0308
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#endif
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#define IOMMU_PMU_TL_LOW_REG1 0x0310
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#define IOMMU_PMU_TL_HIGH_REG1 0x0314
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#if defined(CONFIG_ARCH_SUN8IW15) || defined(CONFIG_ARCH_SUN50IW9) \
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|| defined(CONFIG_ARCH_SUN8IW19) || defined(CONFIG_ARCH_SUN50IW10)
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#define IOMMU_PMU_ML_REG1 0x0318
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#endif
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#define IOMMU_PMU_TL_LOW_REG2 0x0320
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#define IOMMU_PMU_TL_HIGH_REG2 0x0324
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#if defined(CONFIG_ARCH_SUN8IW15) || defined(CONFIG_ARCH_SUN50IW9) \
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|| defined(CONFIG_ARCH_SUN8IW19) || defined(CONFIG_ARCH_SUN50IW10)
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#define IOMMU_PMU_ML_REG2 0x0328
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#endif
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#define IOMMU_PMU_TL_LOW_REG3 0x0330
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#define IOMMU_PMU_TL_HIGH_REG3 0x0334
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#if defined(CONFIG_ARCH_SUN8IW15) || defined(CONFIG_ARCH_SUN50IW9) \
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|| defined(CONFIG_ARCH_SUN8IW19) || defined(CONFIG_ARCH_SUN50IW10)
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#define IOMMU_PMU_ML_REG3 0x0338
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#endif
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#define IOMMU_PMU_TL_LOW_REG4 0x0340
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#define IOMMU_PMU_TL_HIGH_REG4 0x0344
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#if defined(CONFIG_ARCH_SUN8IW15) || defined(CONFIG_ARCH_SUN50IW9) \
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|| defined(CONFIG_ARCH_SUN8IW19) || defined(CONFIG_ARCH_SUN50IW10)
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#define IOMMU_PMU_ML_REG4 0x0348
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#endif
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#define IOMMU_PMU_TL_LOW_REG5 0x0350
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#define IOMMU_PMU_TL_HIGH_REG5 0x0354
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#if defined(CONFIG_ARCH_SUN8IW15) || defined(CONFIG_ARCH_SUN50IW9) \
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|| defined(CONFIG_ARCH_SUN8IW19) || defined(CONFIG_ARCH_SUN50IW10)
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#define IOMMU_PMU_ML_REG5 0x0358
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#endif
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#define IOMMU_PMU_TL_LOW_REG6 0x0360
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#define IOMMU_PMU_TL_HIGH_REG6 0x0364
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#if defined(CONFIG_ARCH_SUN8IW15) || defined(CONFIG_ARCH_SUN50IW9) \
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|| defined(CONFIG_ARCH_SUN8IW19) || defined(CONFIG_ARCH_SUN50IW10)
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#define IOMMU_PMU_ML_REG6 0x0368
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#endif
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#define IOMMU_RESET_SHIFT 31
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#define IOMMU_RESET_MASK (1 << IOMMU_RESET_SHIFT)
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#define IOMMU_RESET_SET (0 << 31)
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#define IOMMU_RESET_RELEASE (1 << 31)
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/*
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* IOMMU enable register field
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*/
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#define IOMMU_ENABLE 0x1
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/*
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* IOMMU interrupt id mask
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*/
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#define MICRO_TLB0_INVALID_INTER_MASK 0x1
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#define MICRO_TLB1_INVALID_INTER_MASK 0x2
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#define MICRO_TLB2_INVALID_INTER_MASK 0x4
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#define MICRO_TLB3_INVALID_INTER_MASK 0x8
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#define MICRO_TLB4_INVALID_INTER_MASK 0x10
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#define MICRO_TLB5_INVALID_INTER_MASK 0x20
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#define MICRO_TLB6_INVALID_INTER_MASK 0x40
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#define L1_PAGETABLE_INVALID_INTER_MASK 0x10000
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#define L2_PAGETABLE_INVALID_INTER_MASK 0x20000
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/*
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* This version Hardware just only support 4KB page. It have
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* a two level page table structure, where the first level has
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* 4096 entries, and the second level has 256 entries. And, the
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* first level is "Page Directory(PG)", every entry include a
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* Page Table base address and a few of control bits. Second
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* level is "Page Table(PT)", every entry include a physical
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* page address and a few of control bits. Each entry is one
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* 32-bit word. Most of the bits in the second level entry are
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* used by hardware.
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*
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* Virtual Address Format:
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* 31 20|19 12|11 0
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* +-----------------+------------+--------+
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* | PDE Index | PTE Index | offset |
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* +-----------------+------------+--------+
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*
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* Table Layout:
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*
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* First Level Second Level
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* (Page Directory) (Page Table)
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* ----+---------+0
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* ∧ | PDE | ---> -+--------+----
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* | ----------+1 | PTE | ∧
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* | | | +--------+ |
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* ----------+2 | | 1K
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* 16K | | +--------+ |
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* ----------+3 | | ∨
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* | | | +--------+----
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* | ----------
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* | | |
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* ∨ | |
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* ----+--------+
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*
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* IOPDE:
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* 31 10|9 0
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* +------------------------+--------+
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* | PTE Base Address |CTRL BIT|
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* +------------------------+--------+
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*
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* IOPTE:
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* 31 12|11 0
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* +---------------------+-----------+
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* | Phy Page Address | CTRL BIT |
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* +---------------------+-----------+
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*
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*/
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#define NUM_ENTRIES_PDE 4096
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#define NUM_ENTRIES_PTE 256
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#define PD_SIZE (NUM_ENTRIES_PDE * sizeof(u32))
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#define PT_SIZE (NUM_ENTRIES_PTE * sizeof(u32))
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#define IOMMU_PD_SHIFT 20
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#define IOMMU_PD_MASK (~((1UL << IOMMU_PD_SHIFT) - 1))
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#define IOMMU_PT_SHIFT 12
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#define IOMMU_PT_MASK (~((1UL << IOMMU_PT_SHIFT) - 1))
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#define PAGE_OFFSET_MASK ((1UL << IOMMU_PT_SHIFT) - 1)
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#define IOPTE_BASE_MASK (~(PT_SIZE - 1))
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/*
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* Page Directory Entry Control Bits
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*/
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#define DENT_VALID 0x01
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#define DENT_PTE_SHFIT 10
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#define DENT_WRITABLE BIT(3)
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#define DENT_READABLE BIT(2)
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/*
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* Page Table Entry Control Bits
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*/
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#define SUNXI_PTE_PAGE_WRITABLE BIT(3)
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#define SUNXI_PTE_PAGE_READABLE BIT(2)
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#define SUNXI_PTE_PAGE_VALID BIT(1)
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#define IS_VALID(x) (((x) & 0x03) == DENT_VALID)
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#define IOPDE_INDEX(va) (((va) >> IOMMU_PD_SHIFT) & (NUM_ENTRIES_PDE - 1))
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#define IOPTE_INDEX(va) (((va) >> IOMMU_PT_SHIFT) & (NUM_ENTRIES_PTE - 1))
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#define IOPTE_BASE(ent) ((ent) & IOPTE_BASE_MASK)
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#define IOPTE_TO_PFN(ent) ((*ent) & IOMMU_PT_MASK)
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#define IOVA_PAGE_OFT(va) ((va) & PAGE_OFFSET_MASK)
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#define SPAGE_SIZE (1 << IOMMU_PT_SHIFT)
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#define SPD_SIZE (1 << IOMMU_PD_SHIFT)
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#define SPAGE_ALIGN(addr) ALIGN(addr, SPAGE_SIZE)
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#define SPDE_ALIGN(addr) ALIGN(addr, SPD_SIZE)
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#define MAX_SG_SIZE (128 << 20)
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#define MAX_SG_TABLE_SIZE ((MAX_SG_SIZE / SPAGE_SIZE) * sizeof(u32))
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/* IO virtual address start page frame number */
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#define IOVA_START_PFN (1)
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#define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT)
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#define DMA_32BIT_PFN IOVA_PFN(DMA_BIT_MASK(32))
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/* TLB Invalid ALIGN */
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#define IOVA_4M_ALIGN(iova) ((iova) & (~0x3fffff))
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#ifdef CONFIG_ARCH_SUN50IW3
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#define DEFAULT_BYPASS_VALUE 0x3f
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static const u32 master_id_bitmap[] = {0x3, 0x0, 0x0, 0xc, 0x10, 0x20};
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#endif
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#ifdef CONFIG_ARCH_SUN50IW6
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#define DEFAULT_BYPASS_VALUE 0x3f
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static const u32 master_id_bitmap[] = {0x1, 0x0, 0x4, 0xa, 0x10, 0x20};
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#endif
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#define SUNXI_PHYS_OFFSET 0x40000000UL
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#define SUNXI_4G_PHYS_OFFSET 0x100000000UL
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/**
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* sun8iw15p1
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* DE : masterID 0
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* E_EDMA: masterID 1
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* E_FE: masterID 2
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* VE: masterID 3
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* CSI: masterID 4
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* G2D: masterID 5
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* E_BE: masterID 6
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*
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* sun50iw9p1:
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* DE : masterID 0
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* DI: masterID 1
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* VE_R: masterID 2
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* VE: masterID 3
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* CSI0: masterID 4
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* CSI1: masterID 5
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* G2D: masterID 6
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* sun8iw19p1:
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* DE :>--->-------masterID 0
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* EISE: masterID 1
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* AI: masterID 2
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* VE:>---->-------masterID 3
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* CSI: >-->----masterID 4
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* ISP:>-->------ masterID 5
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* G2D:>--->-------masterID 6
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*/
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#if defined(CONFIG_ARCH_SUN8IW15) || defined(CONFIG_ARCH_SUN50IW9) \
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|| defined(CONFIG_ARCH_SUN8IW19) || defined(CONFIG_ARCH_SUN50IW10)
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#define DEFAULT_BYPASS_VALUE 0x7f
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static const u32 master_id_bitmap[] = {0x1, 0x2, 0x4, 0x8, 0x10, 0x20, 0x40};
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#endif
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#define sunxi_wait_when(COND, MS) ({ \
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unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1; \
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int ret__ = 0; \
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while ((COND)) { \
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if (time_after(jiffies, timeout__)) { \
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ret__ = (!COND) ? 0 : -ETIMEDOUT; \
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break; \
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} \
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udelay(1); \
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} \
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ret__; \
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})
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/*
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* The format of device tree, and client device how to use it.
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*
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* /{
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* ....
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* smmu: iommu@xxxxx {
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* compatible = "allwinner,iommu";
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* reg = <xxx xxx xxx xxx>;
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* interrupts = <GIC_SPI xxx IRQ_TYPE_LEVEL_HIGH>;
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* interrupt-names = "iommu-irq";
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* clocks = <&iommu_clk>;
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* clock-name = "iommu-clk";
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* #iommu-cells = <1>;
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* status = "enabled";
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* };
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*
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* de@xxxxx {
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* .....
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* iommus = <&smmu ID>;
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* };
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*
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* }
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*
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* Here, ID number is 0 ~ 5, every client device have a unique id.
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* Every id represent a micro TLB, also represent a master device.
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*
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*/
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struct sunxi_iommu {
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struct device *dev;
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void __iomem *base;
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struct clk *clk;
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int irq;
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u32 bypass;
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spinlock_t iommu_lock;
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};
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struct sunxi_iommu_domain {
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unsigned int *pgtable; /* first page directory, size is 16KB */
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u32 *sg_buffer;
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struct mutex dt_lock; /* lock for modifying page table @ pgtable */
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struct dma_iommu_mapping *mapping;
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struct iommu_domain domain;
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//struct iova_domain iovad;
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/* list of master device, it represent a micro TLB */
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struct list_head mdevs;
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spinlock_t lock;
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};
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/*
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* sunxi master device which use iommu.
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*/
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struct sunxi_mdev {
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struct list_head node; /* for sunxi_iommu mdevs list */
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struct device *dev; /* the master device */
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unsigned int tlbid; /* micro TLB id, distinguish device by it */
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bool flag;
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};
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struct sunxi_iommu_owner {
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unsigned int tlbid;
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bool flag;
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struct sunxi_iommu *data;
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struct device *dev;
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struct dma_iommu_mapping *mapping;
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};
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int sunxi_iova_test_write(dma_addr_t iova, u32 val);
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unsigned long sunxi_iova_test_read(dma_addr_t iova);
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void sunxi_set_debug_mode(void);
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void sunxi_set_prefetch_mode(void);
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extern struct iommu_domain *global_iommu_domain;
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