/*
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* Copyright (C) 2015 The Android Open Source Project
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef ART_COMPILER_OPTIMIZING_CODE_GENERATOR_MIPS64_H_
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#define ART_COMPILER_OPTIMIZING_CODE_GENERATOR_MIPS64_H_
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#include "code_generator.h"
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#include "dex/type_reference.h"
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#include "driver/compiler_options.h"
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#include "nodes.h"
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#include "parallel_move_resolver.h"
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#include "utils/mips64/assembler_mips64.h"
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namespace art {
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namespace mips64 {
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// InvokeDexCallingConvention registers
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static constexpr GpuRegister kParameterCoreRegisters[] =
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{ A1, A2, A3, A4, A5, A6, A7 };
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static constexpr size_t kParameterCoreRegistersLength = arraysize(kParameterCoreRegisters);
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static constexpr FpuRegister kParameterFpuRegisters[] =
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{ F13, F14, F15, F16, F17, F18, F19 };
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static constexpr size_t kParameterFpuRegistersLength = arraysize(kParameterFpuRegisters);
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// InvokeRuntimeCallingConvention registers
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static constexpr GpuRegister kRuntimeParameterCoreRegisters[] =
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{ A0, A1, A2, A3, A4, A5, A6, A7 };
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static constexpr size_t kRuntimeParameterCoreRegistersLength =
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arraysize(kRuntimeParameterCoreRegisters);
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static constexpr FpuRegister kRuntimeParameterFpuRegisters[] =
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{ F12, F13, F14, F15, F16, F17, F18, F19 };
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static constexpr size_t kRuntimeParameterFpuRegistersLength =
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arraysize(kRuntimeParameterFpuRegisters);
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static constexpr GpuRegister kCoreCalleeSaves[] =
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{ S0, S1, S2, S3, S4, S5, S6, S7, GP, S8, RA };
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static constexpr FpuRegister kFpuCalleeSaves[] =
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{ F24, F25, F26, F27, F28, F29, F30, F31 };
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class CodeGeneratorMIPS64;
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VectorRegister VectorRegisterFrom(Location location);
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class InvokeDexCallingConvention : public CallingConvention<GpuRegister, FpuRegister> {
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public:
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InvokeDexCallingConvention()
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: CallingConvention(kParameterCoreRegisters,
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kParameterCoreRegistersLength,
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kParameterFpuRegisters,
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kParameterFpuRegistersLength,
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kMips64PointerSize) {}
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private:
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DISALLOW_COPY_AND_ASSIGN(InvokeDexCallingConvention);
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};
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class InvokeDexCallingConventionVisitorMIPS64 : public InvokeDexCallingConventionVisitor {
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public:
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InvokeDexCallingConventionVisitorMIPS64() {}
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virtual ~InvokeDexCallingConventionVisitorMIPS64() {}
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Location GetNextLocation(DataType::Type type) override;
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Location GetReturnLocation(DataType::Type type) const override;
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Location GetMethodLocation() const override;
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private:
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InvokeDexCallingConvention calling_convention;
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DISALLOW_COPY_AND_ASSIGN(InvokeDexCallingConventionVisitorMIPS64);
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};
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class InvokeRuntimeCallingConvention : public CallingConvention<GpuRegister, FpuRegister> {
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public:
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InvokeRuntimeCallingConvention()
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: CallingConvention(kRuntimeParameterCoreRegisters,
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kRuntimeParameterCoreRegistersLength,
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kRuntimeParameterFpuRegisters,
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kRuntimeParameterFpuRegistersLength,
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kMips64PointerSize) {}
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Location GetReturnLocation(DataType::Type return_type);
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private:
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DISALLOW_COPY_AND_ASSIGN(InvokeRuntimeCallingConvention);
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};
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class FieldAccessCallingConventionMIPS64 : public FieldAccessCallingConvention {
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public:
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FieldAccessCallingConventionMIPS64() {}
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Location GetObjectLocation() const override {
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return Location::RegisterLocation(A1);
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}
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Location GetFieldIndexLocation() const override {
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return Location::RegisterLocation(A0);
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}
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Location GetReturnLocation(DataType::Type type ATTRIBUTE_UNUSED) const override {
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return Location::RegisterLocation(V0);
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}
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Location GetSetValueLocation(DataType::Type type ATTRIBUTE_UNUSED,
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bool is_instance) const override {
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return is_instance
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? Location::RegisterLocation(A2)
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: Location::RegisterLocation(A1);
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}
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Location GetFpuLocation(DataType::Type type ATTRIBUTE_UNUSED) const override {
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return Location::FpuRegisterLocation(F0);
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}
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private:
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DISALLOW_COPY_AND_ASSIGN(FieldAccessCallingConventionMIPS64);
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};
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class ParallelMoveResolverMIPS64 : public ParallelMoveResolverWithSwap {
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public:
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ParallelMoveResolverMIPS64(ArenaAllocator* allocator, CodeGeneratorMIPS64* codegen)
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: ParallelMoveResolverWithSwap(allocator), codegen_(codegen) {}
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void EmitMove(size_t index) override;
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void EmitSwap(size_t index) override;
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void SpillScratch(int reg) override;
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void RestoreScratch(int reg) override;
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void Exchange(int index1, int index2, bool double_slot);
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void ExchangeQuadSlots(int index1, int index2);
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Mips64Assembler* GetAssembler() const;
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private:
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CodeGeneratorMIPS64* const codegen_;
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DISALLOW_COPY_AND_ASSIGN(ParallelMoveResolverMIPS64);
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};
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class SlowPathCodeMIPS64 : public SlowPathCode {
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public:
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explicit SlowPathCodeMIPS64(HInstruction* instruction)
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: SlowPathCode(instruction), entry_label_(), exit_label_() {}
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Mips64Label* GetEntryLabel() { return &entry_label_; }
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Mips64Label* GetExitLabel() { return &exit_label_; }
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private:
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Mips64Label entry_label_;
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Mips64Label exit_label_;
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DISALLOW_COPY_AND_ASSIGN(SlowPathCodeMIPS64);
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};
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class LocationsBuilderMIPS64 : public HGraphVisitor {
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public:
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LocationsBuilderMIPS64(HGraph* graph, CodeGeneratorMIPS64* codegen)
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: HGraphVisitor(graph), codegen_(codegen) {}
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#define DECLARE_VISIT_INSTRUCTION(name, super) \
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void Visit##name(H##name* instr) override;
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FOR_EACH_CONCRETE_INSTRUCTION_COMMON(DECLARE_VISIT_INSTRUCTION)
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FOR_EACH_CONCRETE_INSTRUCTION_MIPS64(DECLARE_VISIT_INSTRUCTION)
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#undef DECLARE_VISIT_INSTRUCTION
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void VisitInstruction(HInstruction* instruction) override {
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LOG(FATAL) << "Unreachable instruction " << instruction->DebugName()
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<< " (id " << instruction->GetId() << ")";
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}
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private:
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void HandleInvoke(HInvoke* invoke);
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void HandleBinaryOp(HBinaryOperation* operation);
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void HandleCondition(HCondition* instruction);
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void HandleShift(HBinaryOperation* operation);
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void HandleFieldSet(HInstruction* instruction, const FieldInfo& field_info);
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void HandleFieldGet(HInstruction* instruction, const FieldInfo& field_info);
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Location RegisterOrZeroConstant(HInstruction* instruction);
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Location FpuRegisterOrConstantForStore(HInstruction* instruction);
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InvokeDexCallingConventionVisitorMIPS64 parameter_visitor_;
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CodeGeneratorMIPS64* const codegen_;
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DISALLOW_COPY_AND_ASSIGN(LocationsBuilderMIPS64);
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};
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class InstructionCodeGeneratorMIPS64 : public InstructionCodeGenerator {
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public:
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InstructionCodeGeneratorMIPS64(HGraph* graph, CodeGeneratorMIPS64* codegen);
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#define DECLARE_VISIT_INSTRUCTION(name, super) \
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void Visit##name(H##name* instr) override;
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FOR_EACH_CONCRETE_INSTRUCTION_COMMON(DECLARE_VISIT_INSTRUCTION)
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FOR_EACH_CONCRETE_INSTRUCTION_MIPS64(DECLARE_VISIT_INSTRUCTION)
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#undef DECLARE_VISIT_INSTRUCTION
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void VisitInstruction(HInstruction* instruction) override {
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LOG(FATAL) << "Unreachable instruction " << instruction->DebugName()
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<< " (id " << instruction->GetId() << ")";
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}
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Mips64Assembler* GetAssembler() const { return assembler_; }
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// Compare-and-jump packed switch generates approx. 3 + 2.5 * N 32-bit
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// instructions for N cases.
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// Table-based packed switch generates approx. 11 32-bit instructions
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// and N 32-bit data words for N cases.
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// At N = 6 they come out as 18 and 17 32-bit words respectively.
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// We switch to the table-based method starting with 7 cases.
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static constexpr uint32_t kPackedSwitchJumpTableThreshold = 6;
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void GenerateMemoryBarrier(MemBarrierKind kind);
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private:
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void GenerateClassInitializationCheck(SlowPathCodeMIPS64* slow_path, GpuRegister class_reg);
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void GenerateBitstringTypeCheckCompare(HTypeCheckInstruction* check, GpuRegister temp);
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void GenerateSuspendCheck(HSuspendCheck* check, HBasicBlock* successor);
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void HandleBinaryOp(HBinaryOperation* operation);
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void HandleCondition(HCondition* instruction);
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void HandleShift(HBinaryOperation* operation);
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void HandleFieldSet(HInstruction* instruction,
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const FieldInfo& field_info,
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bool value_can_be_null);
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void HandleFieldGet(HInstruction* instruction, const FieldInfo& field_info);
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void GenerateMinMaxInt(LocationSummary* locations, bool is_min);
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void GenerateMinMaxFP(LocationSummary* locations, bool is_min, DataType::Type type);
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void GenerateMinMax(HBinaryOperation* minmax, bool is_min);
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// Generate a heap reference load using one register `out`:
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//
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// out <- *(out + offset)
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//
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// while honoring heap poisoning and/or read barriers (if any).
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//
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// Location `maybe_temp` is used when generating a read barrier and
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// shall be a register in that case; it may be an invalid location
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// otherwise.
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void GenerateReferenceLoadOneRegister(HInstruction* instruction,
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Location out,
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uint32_t offset,
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Location maybe_temp,
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ReadBarrierOption read_barrier_option);
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// Generate a heap reference load using two different registers
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// `out` and `obj`:
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//
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// out <- *(obj + offset)
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//
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// while honoring heap poisoning and/or read barriers (if any).
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//
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// Location `maybe_temp` is used when generating a Baker's (fast
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// path) read barrier and shall be a register in that case; it may
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// be an invalid location otherwise.
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void GenerateReferenceLoadTwoRegisters(HInstruction* instruction,
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Location out,
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Location obj,
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uint32_t offset,
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Location maybe_temp,
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ReadBarrierOption read_barrier_option);
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// Generate a GC root reference load:
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//
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// root <- *(obj + offset)
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//
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// while honoring read barriers (if any).
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void GenerateGcRootFieldLoad(HInstruction* instruction,
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Location root,
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GpuRegister obj,
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uint32_t offset,
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ReadBarrierOption read_barrier_option,
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Mips64Label* label_low = nullptr);
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void GenerateTestAndBranch(HInstruction* instruction,
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size_t condition_input_index,
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Mips64Label* true_target,
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Mips64Label* false_target);
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void DivRemOneOrMinusOne(HBinaryOperation* instruction);
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void DivRemByPowerOfTwo(HBinaryOperation* instruction);
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void GenerateDivRemWithAnyConstant(HBinaryOperation* instruction);
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void GenerateDivRemIntegral(HBinaryOperation* instruction);
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void GenerateIntLongCompare(IfCondition cond, bool is64bit, LocationSummary* locations);
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// When the function returns `false` it means that the condition holds if `dst` is non-zero
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// and doesn't hold if `dst` is zero. If it returns `true`, the roles of zero and non-zero
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// `dst` are exchanged.
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bool MaterializeIntLongCompare(IfCondition cond,
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bool is64bit,
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LocationSummary* input_locations,
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GpuRegister dst);
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void GenerateIntLongCompareAndBranch(IfCondition cond,
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bool is64bit,
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LocationSummary* locations,
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Mips64Label* label);
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void GenerateFpCompare(IfCondition cond,
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bool gt_bias,
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DataType::Type type,
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LocationSummary* locations);
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// When the function returns `false` it means that the condition holds if `dst` is non-zero
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// and doesn't hold if `dst` is zero. If it returns `true`, the roles of zero and non-zero
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// `dst` are exchanged.
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bool MaterializeFpCompare(IfCondition cond,
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bool gt_bias,
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DataType::Type type,
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LocationSummary* input_locations,
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FpuRegister dst);
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void GenerateFpCompareAndBranch(IfCondition cond,
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bool gt_bias,
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DataType::Type type,
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LocationSummary* locations,
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Mips64Label* label);
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void HandleGoto(HInstruction* got, HBasicBlock* successor);
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void GenPackedSwitchWithCompares(GpuRegister value_reg,
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int32_t lower_bound,
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uint32_t num_entries,
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HBasicBlock* switch_block,
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HBasicBlock* default_block);
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void GenTableBasedPackedSwitch(GpuRegister value_reg,
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int32_t lower_bound,
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uint32_t num_entries,
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HBasicBlock* switch_block,
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HBasicBlock* default_block);
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int32_t VecAddress(LocationSummary* locations,
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size_t size,
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/* out */ GpuRegister* adjusted_base);
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void GenConditionalMove(HSelect* select);
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Mips64Assembler* const assembler_;
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CodeGeneratorMIPS64* const codegen_;
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DISALLOW_COPY_AND_ASSIGN(InstructionCodeGeneratorMIPS64);
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};
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class CodeGeneratorMIPS64 : public CodeGenerator {
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public:
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CodeGeneratorMIPS64(HGraph* graph,
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const CompilerOptions& compiler_options,
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OptimizingCompilerStats* stats = nullptr);
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virtual ~CodeGeneratorMIPS64() {}
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void GenerateFrameEntry() override;
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void GenerateFrameExit() override;
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void Bind(HBasicBlock* block) override;
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size_t GetWordSize() const override { return kMips64DoublewordSize; }
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size_t GetFloatingPointSpillSlotSize() const override {
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return GetGraph()->HasSIMD()
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? 2 * kMips64DoublewordSize // 16 bytes for each spill.
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: 1 * kMips64DoublewordSize; // 8 bytes for each spill.
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}
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uintptr_t GetAddressOf(HBasicBlock* block) override {
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return assembler_.GetLabelLocation(GetLabelOf(block));
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}
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HGraphVisitor* GetLocationBuilder() override { return &location_builder_; }
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HGraphVisitor* GetInstructionVisitor() override { return &instruction_visitor_; }
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Mips64Assembler* GetAssembler() override { return &assembler_; }
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const Mips64Assembler& GetAssembler() const override { return assembler_; }
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// Emit linker patches.
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void EmitLinkerPatches(ArenaVector<linker::LinkerPatch>* linker_patches) override;
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void EmitJitRootPatches(uint8_t* code, const uint8_t* roots_data) override;
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// Fast path implementation of ReadBarrier::Barrier for a heap
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// reference field load when Baker's read barriers are used.
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void GenerateFieldLoadWithBakerReadBarrier(HInstruction* instruction,
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Location ref,
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GpuRegister obj,
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uint32_t offset,
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Location temp,
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bool needs_null_check);
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// Fast path implementation of ReadBarrier::Barrier for a heap
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// reference array load when Baker's read barriers are used.
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void GenerateArrayLoadWithBakerReadBarrier(HInstruction* instruction,
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Location ref,
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GpuRegister obj,
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uint32_t data_offset,
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Location index,
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Location temp,
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bool needs_null_check);
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// Factored implementation, used by GenerateFieldLoadWithBakerReadBarrier,
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// GenerateArrayLoadWithBakerReadBarrier and some intrinsics.
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//
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// Load the object reference located at the address
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// `obj + offset + (index << scale_factor)`, held by object `obj`, into
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// `ref`, and mark it if needed.
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//
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// If `always_update_field` is true, the value of the reference is
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// atomically updated in the holder (`obj`).
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void GenerateReferenceLoadWithBakerReadBarrier(HInstruction* instruction,
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Location ref,
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GpuRegister obj,
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uint32_t offset,
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Location index,
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ScaleFactor scale_factor,
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Location temp,
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bool needs_null_check,
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bool always_update_field = false);
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// Generate a read barrier for a heap reference within `instruction`
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// using a slow path.
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//
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// A read barrier for an object reference read from the heap is
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// implemented as a call to the artReadBarrierSlow runtime entry
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// point, which is passed the values in locations `ref`, `obj`, and
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// `offset`:
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//
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// mirror::Object* artReadBarrierSlow(mirror::Object* ref,
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// mirror::Object* obj,
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// uint32_t offset);
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//
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// The `out` location contains the value returned by
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// artReadBarrierSlow.
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//
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// When `index` is provided (i.e. for array accesses), the offset
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// value passed to artReadBarrierSlow is adjusted to take `index`
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// into account.
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void GenerateReadBarrierSlow(HInstruction* instruction,
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Location out,
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Location ref,
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Location obj,
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uint32_t offset,
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Location index = Location::NoLocation());
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// If read barriers are enabled, generate a read barrier for a heap
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// reference using a slow path. If heap poisoning is enabled, also
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// unpoison the reference in `out`.
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void MaybeGenerateReadBarrierSlow(HInstruction* instruction,
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Location out,
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Location ref,
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Location obj,
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uint32_t offset,
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Location index = Location::NoLocation());
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// Generate a read barrier for a GC root within `instruction` using
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// a slow path.
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//
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// A read barrier for an object reference GC root is implemented as
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// a call to the artReadBarrierForRootSlow runtime entry point,
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// which is passed the value in location `root`:
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//
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// mirror::Object* artReadBarrierForRootSlow(GcRoot<mirror::Object>* root);
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//
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// The `out` location contains the value returned by
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// artReadBarrierForRootSlow.
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void GenerateReadBarrierForRootSlow(HInstruction* instruction, Location out, Location root);
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void MarkGCCard(GpuRegister object, GpuRegister value, bool value_can_be_null);
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// Register allocation.
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void SetupBlockedRegisters() const override;
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size_t SaveCoreRegister(size_t stack_index, uint32_t reg_id) override;
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size_t RestoreCoreRegister(size_t stack_index, uint32_t reg_id) override;
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size_t SaveFloatingPointRegister(size_t stack_index, uint32_t reg_id) override;
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size_t RestoreFloatingPointRegister(size_t stack_index, uint32_t reg_id) override;
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void DumpCoreRegister(std::ostream& stream, int reg) const override;
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void DumpFloatingPointRegister(std::ostream& stream, int reg) const override;
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InstructionSet GetInstructionSet() const override { return InstructionSet::kMips64; }
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const Mips64InstructionSetFeatures& GetInstructionSetFeatures() const;
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Mips64Label* GetLabelOf(HBasicBlock* block) const {
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return CommonGetLabelOf<Mips64Label>(block_labels_, block);
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}
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void Initialize() override {
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block_labels_ = CommonInitializeLabels<Mips64Label>();
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}
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// We prefer aligned loads and stores (less code), so spill and restore registers in slow paths
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// at aligned locations.
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uint32_t GetPreferredSlotsAlignment() const override { return kMips64DoublewordSize; }
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void Finalize(CodeAllocator* allocator) override;
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// Code generation helpers.
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void MoveLocation(Location dst, Location src, DataType::Type dst_type) override;
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void MoveConstant(Location destination, int32_t value) override;
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void AddLocationAsTemp(Location location, LocationSummary* locations) override;
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void SwapLocations(Location loc1, Location loc2, DataType::Type type);
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// Generate code to invoke a runtime entry point.
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void InvokeRuntime(QuickEntrypointEnum entrypoint,
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HInstruction* instruction,
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uint32_t dex_pc,
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SlowPathCode* slow_path = nullptr) override;
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// Generate code to invoke a runtime entry point, but do not record
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// PC-related information in a stack map.
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void InvokeRuntimeWithoutRecordingPcInfo(int32_t entry_point_offset,
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HInstruction* instruction,
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SlowPathCode* slow_path);
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void GenerateInvokeRuntime(int32_t entry_point_offset);
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ParallelMoveResolver* GetMoveResolver() override { return &move_resolver_; }
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bool NeedsTwoRegisters(DataType::Type type ATTRIBUTE_UNUSED) const override { return false; }
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// Check if the desired_string_load_kind is supported. If it is, return it,
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// otherwise return a fall-back kind that should be used instead.
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HLoadString::LoadKind GetSupportedLoadStringKind(
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HLoadString::LoadKind desired_string_load_kind) override;
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// Check if the desired_class_load_kind is supported. If it is, return it,
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// otherwise return a fall-back kind that should be used instead.
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HLoadClass::LoadKind GetSupportedLoadClassKind(
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HLoadClass::LoadKind desired_class_load_kind) override;
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// Check if the desired_dispatch_info is supported. If it is, return it,
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// otherwise return a fall-back info that should be used instead.
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HInvokeStaticOrDirect::DispatchInfo GetSupportedInvokeStaticOrDirectDispatch(
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const HInvokeStaticOrDirect::DispatchInfo& desired_dispatch_info,
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ArtMethod* method) override;
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void GenerateStaticOrDirectCall(
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HInvokeStaticOrDirect* invoke, Location temp, SlowPathCode* slow_path = nullptr) override;
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void GenerateVirtualCall(
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HInvokeVirtual* invoke, Location temp, SlowPathCode* slow_path = nullptr) override;
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void MoveFromReturnRegister(Location trg ATTRIBUTE_UNUSED,
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DataType::Type type ATTRIBUTE_UNUSED) override {
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UNIMPLEMENTED(FATAL) << "Not implemented on MIPS64";
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}
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void GenerateNop() override;
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void GenerateImplicitNullCheck(HNullCheck* instruction) override;
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void GenerateExplicitNullCheck(HNullCheck* instruction) override;
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// The PcRelativePatchInfo is used for PC-relative addressing of methods/strings/types,
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// whether through .data.bimg.rel.ro, .bss, or directly in the boot image.
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//
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// The 16-bit halves of the 32-bit PC-relative offset are patched separately, necessitating
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// two patches/infos. There can be more than two patches/infos if the instruction supplying
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// the high half is shared with e.g. a slow path, while the low half is supplied by separate
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// instructions, e.g.:
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// auipc r1, high // patch
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// lwu r2, low(r1) // patch
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// beqzc r2, slow_path
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// back:
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// ...
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// slow_path:
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// ...
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// sw r2, low(r1) // patch
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// bc back
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struct PcRelativePatchInfo : PatchInfo<Mips64Label> {
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PcRelativePatchInfo(const DexFile* dex_file,
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uint32_t off_or_idx,
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const PcRelativePatchInfo* info_high)
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: PatchInfo<Mips64Label>(dex_file, off_or_idx),
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patch_info_high(info_high) { }
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// Pointer to the info for the high half patch or nullptr if this is the high half patch info.
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const PcRelativePatchInfo* patch_info_high;
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private:
|
PcRelativePatchInfo(PcRelativePatchInfo&& other) = delete;
|
DISALLOW_COPY_AND_ASSIGN(PcRelativePatchInfo);
|
};
|
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PcRelativePatchInfo* NewBootImageIntrinsicPatch(uint32_t intrinsic_data,
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const PcRelativePatchInfo* info_high = nullptr);
|
PcRelativePatchInfo* NewBootImageRelRoPatch(uint32_t boot_image_offset,
|
const PcRelativePatchInfo* info_high = nullptr);
|
PcRelativePatchInfo* NewBootImageMethodPatch(MethodReference target_method,
|
const PcRelativePatchInfo* info_high = nullptr);
|
PcRelativePatchInfo* NewMethodBssEntryPatch(MethodReference target_method,
|
const PcRelativePatchInfo* info_high = nullptr);
|
PcRelativePatchInfo* NewBootImageTypePatch(const DexFile& dex_file,
|
dex::TypeIndex type_index,
|
const PcRelativePatchInfo* info_high = nullptr);
|
PcRelativePatchInfo* NewTypeBssEntryPatch(const DexFile& dex_file,
|
dex::TypeIndex type_index,
|
const PcRelativePatchInfo* info_high = nullptr);
|
PcRelativePatchInfo* NewBootImageStringPatch(const DexFile& dex_file,
|
dex::StringIndex string_index,
|
const PcRelativePatchInfo* info_high = nullptr);
|
PcRelativePatchInfo* NewStringBssEntryPatch(const DexFile& dex_file,
|
dex::StringIndex string_index,
|
const PcRelativePatchInfo* info_high = nullptr);
|
Literal* DeduplicateBootImageAddressLiteral(uint64_t address);
|
|
void EmitPcRelativeAddressPlaceholderHigh(PcRelativePatchInfo* info_high,
|
GpuRegister out,
|
PcRelativePatchInfo* info_low = nullptr);
|
|
void LoadBootImageAddress(GpuRegister reg, uint32_t boot_image_reference);
|
void AllocateInstanceForIntrinsic(HInvokeStaticOrDirect* invoke, uint32_t boot_image_offset);
|
|
void PatchJitRootUse(uint8_t* code,
|
const uint8_t* roots_data,
|
const Literal* literal,
|
uint64_t index_in_table) const;
|
Literal* DeduplicateJitStringLiteral(const DexFile& dex_file,
|
dex::StringIndex string_index,
|
Handle<mirror::String> handle);
|
Literal* DeduplicateJitClassLiteral(const DexFile& dex_file,
|
dex::TypeIndex type_index,
|
Handle<mirror::Class> handle);
|
|
private:
|
using Uint32ToLiteralMap = ArenaSafeMap<uint32_t, Literal*>;
|
using Uint64ToLiteralMap = ArenaSafeMap<uint64_t, Literal*>;
|
using StringToLiteralMap = ArenaSafeMap<StringReference,
|
Literal*,
|
StringReferenceValueComparator>;
|
using TypeToLiteralMap = ArenaSafeMap<TypeReference,
|
Literal*,
|
TypeReferenceValueComparator>;
|
|
Literal* DeduplicateUint32Literal(uint32_t value, Uint32ToLiteralMap* map);
|
Literal* DeduplicateUint64Literal(uint64_t value);
|
|
PcRelativePatchInfo* NewPcRelativePatch(const DexFile* dex_file,
|
uint32_t offset_or_index,
|
const PcRelativePatchInfo* info_high,
|
ArenaDeque<PcRelativePatchInfo>* patches);
|
|
template <linker::LinkerPatch (*Factory)(size_t, const DexFile*, uint32_t, uint32_t)>
|
void EmitPcRelativeLinkerPatches(const ArenaDeque<PcRelativePatchInfo>& infos,
|
ArenaVector<linker::LinkerPatch>* linker_patches);
|
|
// Labels for each block that will be compiled.
|
Mips64Label* block_labels_; // Indexed by block id.
|
Mips64Label frame_entry_label_;
|
LocationsBuilderMIPS64 location_builder_;
|
InstructionCodeGeneratorMIPS64 instruction_visitor_;
|
ParallelMoveResolverMIPS64 move_resolver_;
|
Mips64Assembler assembler_;
|
|
// Deduplication map for 32-bit literals, used for non-patchable boot image addresses.
|
Uint32ToLiteralMap uint32_literals_;
|
// Deduplication map for 64-bit literals, used for non-patchable method address or method code
|
// address.
|
Uint64ToLiteralMap uint64_literals_;
|
// PC-relative method patch info for kBootImageLinkTimePcRelative/kBootImageRelRo.
|
// Also used for type/string patches for kBootImageRelRo (same linker patch as for methods).
|
ArenaDeque<PcRelativePatchInfo> boot_image_method_patches_;
|
// PC-relative method patch info for kBssEntry.
|
ArenaDeque<PcRelativePatchInfo> method_bss_entry_patches_;
|
// PC-relative type patch info for kBootImageLinkTimePcRelative.
|
ArenaDeque<PcRelativePatchInfo> boot_image_type_patches_;
|
// PC-relative type patch info for kBssEntry.
|
ArenaDeque<PcRelativePatchInfo> type_bss_entry_patches_;
|
// PC-relative String patch info for kBootImageLinkTimePcRelative.
|
ArenaDeque<PcRelativePatchInfo> boot_image_string_patches_;
|
// PC-relative type patch info for kBssEntry.
|
ArenaDeque<PcRelativePatchInfo> string_bss_entry_patches_;
|
// PC-relative patch info for IntrinsicObjects.
|
ArenaDeque<PcRelativePatchInfo> boot_image_intrinsic_patches_;
|
|
// Patches for string root accesses in JIT compiled code.
|
StringToLiteralMap jit_string_patches_;
|
// Patches for class root accesses in JIT compiled code.
|
TypeToLiteralMap jit_class_patches_;
|
|
DISALLOW_COPY_AND_ASSIGN(CodeGeneratorMIPS64);
|
};
|
|
} // namespace mips64
|
} // namespace art
|
|
#endif // ART_COMPILER_OPTIMIZING_CODE_GENERATOR_MIPS64_H_
|
