/*
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* Copyright (C) 2015 The Android Open Source Project
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef ART_COMPILER_OPTIMIZING_CODE_GENERATOR_MIPS_H_
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#define ART_COMPILER_OPTIMIZING_CODE_GENERATOR_MIPS_H_
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#include "code_generator.h"
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#include "dex/dex_file_types.h"
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#include "dex/string_reference.h"
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#include "dex/type_reference.h"
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#include "driver/compiler_options.h"
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#include "nodes.h"
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#include "parallel_move_resolver.h"
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#include "utils/mips/assembler_mips.h"
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namespace art {
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namespace mips {
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// InvokeDexCallingConvention registers
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static constexpr Register kParameterCoreRegisters[] =
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{ A1, A2, A3, T0, T1 };
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static constexpr size_t kParameterCoreRegistersLength = arraysize(kParameterCoreRegisters);
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static constexpr FRegister kParameterFpuRegisters[] =
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{ F8, F10, F12, F14, F16, F18 };
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static constexpr size_t kParameterFpuRegistersLength = arraysize(kParameterFpuRegisters);
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// InvokeRuntimeCallingConvention registers
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static constexpr Register kRuntimeParameterCoreRegisters[] =
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{ A0, A1, A2, A3 };
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static constexpr size_t kRuntimeParameterCoreRegistersLength =
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arraysize(kRuntimeParameterCoreRegisters);
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static constexpr FRegister kRuntimeParameterFpuRegisters[] =
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{ F12, F14 };
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static constexpr size_t kRuntimeParameterFpuRegistersLength =
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arraysize(kRuntimeParameterFpuRegisters);
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static constexpr Register kCoreCalleeSaves[] =
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{ S0, S1, S2, S3, S4, S5, S6, S7, FP, RA };
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static constexpr FRegister kFpuCalleeSaves[] =
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{ F20, F22, F24, F26, F28, F30 };
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class CodeGeneratorMIPS;
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VectorRegister VectorRegisterFrom(Location location);
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class InvokeDexCallingConvention : public CallingConvention<Register, FRegister> {
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public:
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InvokeDexCallingConvention()
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: CallingConvention(kParameterCoreRegisters,
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kParameterCoreRegistersLength,
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kParameterFpuRegisters,
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kParameterFpuRegistersLength,
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kMipsPointerSize) {}
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private:
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DISALLOW_COPY_AND_ASSIGN(InvokeDexCallingConvention);
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};
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class InvokeDexCallingConventionVisitorMIPS : public InvokeDexCallingConventionVisitor {
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public:
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InvokeDexCallingConventionVisitorMIPS() {}
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virtual ~InvokeDexCallingConventionVisitorMIPS() {}
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Location GetNextLocation(DataType::Type type) override;
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Location GetReturnLocation(DataType::Type type) const override;
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Location GetMethodLocation() const override;
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private:
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InvokeDexCallingConvention calling_convention;
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DISALLOW_COPY_AND_ASSIGN(InvokeDexCallingConventionVisitorMIPS);
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};
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class InvokeRuntimeCallingConvention : public CallingConvention<Register, FRegister> {
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public:
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InvokeRuntimeCallingConvention()
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: CallingConvention(kRuntimeParameterCoreRegisters,
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kRuntimeParameterCoreRegistersLength,
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kRuntimeParameterFpuRegisters,
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kRuntimeParameterFpuRegistersLength,
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kMipsPointerSize) {}
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Location GetReturnLocation(DataType::Type return_type);
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private:
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DISALLOW_COPY_AND_ASSIGN(InvokeRuntimeCallingConvention);
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};
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class FieldAccessCallingConventionMIPS : public FieldAccessCallingConvention {
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public:
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FieldAccessCallingConventionMIPS() {}
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Location GetObjectLocation() const override {
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return Location::RegisterLocation(A1);
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}
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Location GetFieldIndexLocation() const override {
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return Location::RegisterLocation(A0);
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}
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Location GetReturnLocation(DataType::Type type) const override {
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return DataType::Is64BitType(type)
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? Location::RegisterPairLocation(V0, V1)
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: Location::RegisterLocation(V0);
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}
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Location GetSetValueLocation(DataType::Type type, bool is_instance) const override {
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return DataType::Is64BitType(type)
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? Location::RegisterPairLocation(A2, A3)
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: (is_instance ? Location::RegisterLocation(A2) : Location::RegisterLocation(A1));
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}
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Location GetFpuLocation(DataType::Type type ATTRIBUTE_UNUSED) const override {
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return Location::FpuRegisterLocation(F0);
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}
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private:
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DISALLOW_COPY_AND_ASSIGN(FieldAccessCallingConventionMIPS);
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};
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class ParallelMoveResolverMIPS : public ParallelMoveResolverWithSwap {
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public:
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ParallelMoveResolverMIPS(ArenaAllocator* allocator, CodeGeneratorMIPS* codegen)
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: ParallelMoveResolverWithSwap(allocator), codegen_(codegen) {}
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void EmitMove(size_t index) override;
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void EmitSwap(size_t index) override;
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void SpillScratch(int reg) override;
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void RestoreScratch(int reg) override;
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void Exchange(int index1, int index2, bool double_slot);
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void ExchangeQuadSlots(int index1, int index2);
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MipsAssembler* GetAssembler() const;
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private:
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CodeGeneratorMIPS* const codegen_;
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DISALLOW_COPY_AND_ASSIGN(ParallelMoveResolverMIPS);
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};
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class SlowPathCodeMIPS : public SlowPathCode {
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public:
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explicit SlowPathCodeMIPS(HInstruction* instruction)
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: SlowPathCode(instruction), entry_label_(), exit_label_() {}
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MipsLabel* GetEntryLabel() { return &entry_label_; }
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MipsLabel* GetExitLabel() { return &exit_label_; }
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private:
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MipsLabel entry_label_;
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MipsLabel exit_label_;
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DISALLOW_COPY_AND_ASSIGN(SlowPathCodeMIPS);
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};
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class LocationsBuilderMIPS : public HGraphVisitor {
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public:
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LocationsBuilderMIPS(HGraph* graph, CodeGeneratorMIPS* codegen)
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: HGraphVisitor(graph), codegen_(codegen) {}
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#define DECLARE_VISIT_INSTRUCTION(name, super) \
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void Visit##name(H##name* instr) override;
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FOR_EACH_CONCRETE_INSTRUCTION_COMMON(DECLARE_VISIT_INSTRUCTION)
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FOR_EACH_CONCRETE_INSTRUCTION_MIPS(DECLARE_VISIT_INSTRUCTION)
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#undef DECLARE_VISIT_INSTRUCTION
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void VisitInstruction(HInstruction* instruction) override {
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LOG(FATAL) << "Unreachable instruction " << instruction->DebugName()
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<< " (id " << instruction->GetId() << ")";
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}
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private:
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void HandleInvoke(HInvoke* invoke);
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void HandleBinaryOp(HBinaryOperation* operation);
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void HandleCondition(HCondition* instruction);
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void HandleShift(HBinaryOperation* operation);
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void HandleFieldSet(HInstruction* instruction, const FieldInfo& field_info);
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void HandleFieldGet(HInstruction* instruction, const FieldInfo& field_info);
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Location RegisterOrZeroConstant(HInstruction* instruction);
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Location FpuRegisterOrConstantForStore(HInstruction* instruction);
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InvokeDexCallingConventionVisitorMIPS parameter_visitor_;
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CodeGeneratorMIPS* const codegen_;
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DISALLOW_COPY_AND_ASSIGN(LocationsBuilderMIPS);
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};
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class InstructionCodeGeneratorMIPS : public InstructionCodeGenerator {
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public:
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InstructionCodeGeneratorMIPS(HGraph* graph, CodeGeneratorMIPS* codegen);
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#define DECLARE_VISIT_INSTRUCTION(name, super) \
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void Visit##name(H##name* instr) override;
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FOR_EACH_CONCRETE_INSTRUCTION_COMMON(DECLARE_VISIT_INSTRUCTION)
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FOR_EACH_CONCRETE_INSTRUCTION_MIPS(DECLARE_VISIT_INSTRUCTION)
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#undef DECLARE_VISIT_INSTRUCTION
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void VisitInstruction(HInstruction* instruction) override {
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LOG(FATAL) << "Unreachable instruction " << instruction->DebugName()
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<< " (id " << instruction->GetId() << ")";
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}
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MipsAssembler* GetAssembler() const { return assembler_; }
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// Compare-and-jump packed switch generates approx. 3 + 2.5 * N 32-bit
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// instructions for N cases.
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// Table-based packed switch generates approx. 11 32-bit instructions
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// and N 32-bit data words for N cases.
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// At N = 6 they come out as 18 and 17 32-bit words respectively.
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// We switch to the table-based method starting with 7 cases.
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static constexpr uint32_t kPackedSwitchJumpTableThreshold = 6;
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void GenerateMemoryBarrier(MemBarrierKind kind);
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private:
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void GenerateClassInitializationCheck(SlowPathCodeMIPS* slow_path, Register class_reg);
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void GenerateSuspendCheck(HSuspendCheck* check, HBasicBlock* successor);
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void GenerateBitstringTypeCheckCompare(HTypeCheckInstruction* check, Register temp);
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void HandleBinaryOp(HBinaryOperation* operation);
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void HandleCondition(HCondition* instruction);
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void HandleShift(HBinaryOperation* operation);
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void HandleFieldSet(HInstruction* instruction,
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const FieldInfo& field_info,
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uint32_t dex_pc,
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bool value_can_be_null);
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void HandleFieldGet(HInstruction* instruction, const FieldInfo& field_info, uint32_t dex_pc);
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void GenerateMinMaxInt(LocationSummary* locations, bool is_min, bool isR6, DataType::Type type);
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void GenerateMinMaxFP(LocationSummary* locations, bool is_min, bool isR6, DataType::Type type);
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void GenerateMinMax(HBinaryOperation*, bool is_min);
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void GenerateAbsFP(LocationSummary* locations, DataType::Type type, bool isR2OrNewer, bool isR6);
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// Generate a heap reference load using one register `out`:
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//
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// out <- *(out + offset)
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//
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// while honoring heap poisoning and/or read barriers (if any).
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//
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// Location `maybe_temp` is used when generating a read barrier and
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// shall be a register in that case; it may be an invalid location
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// otherwise.
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void GenerateReferenceLoadOneRegister(HInstruction* instruction,
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Location out,
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uint32_t offset,
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Location maybe_temp,
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ReadBarrierOption read_barrier_option);
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// Generate a heap reference load using two different registers
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// `out` and `obj`:
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//
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// out <- *(obj + offset)
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//
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// while honoring heap poisoning and/or read barriers (if any).
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//
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// Location `maybe_temp` is used when generating a Baker's (fast
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// path) read barrier and shall be a register in that case; it may
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// be an invalid location otherwise.
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void GenerateReferenceLoadTwoRegisters(HInstruction* instruction,
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Location out,
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Location obj,
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uint32_t offset,
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Location maybe_temp,
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ReadBarrierOption read_barrier_option);
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// Generate a GC root reference load:
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//
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// root <- *(obj + offset)
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//
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// while honoring read barriers (if any).
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void GenerateGcRootFieldLoad(HInstruction* instruction,
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Location root,
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Register obj,
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uint32_t offset,
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ReadBarrierOption read_barrier_option,
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MipsLabel* label_low = nullptr);
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void GenerateIntCompare(IfCondition cond, LocationSummary* locations);
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// When the function returns `false` it means that the condition holds if `dst` is non-zero
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// and doesn't hold if `dst` is zero. If it returns `true`, the roles of zero and non-zero
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// `dst` are exchanged.
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bool MaterializeIntCompare(IfCondition cond,
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LocationSummary* input_locations,
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Register dst);
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void GenerateIntCompareAndBranch(IfCondition cond,
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LocationSummary* locations,
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MipsLabel* label);
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void GenerateLongCompare(IfCondition cond, LocationSummary* locations);
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void GenerateLongCompareAndBranch(IfCondition cond,
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LocationSummary* locations,
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MipsLabel* label);
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void GenerateFpCompare(IfCondition cond,
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bool gt_bias,
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DataType::Type type,
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LocationSummary* locations);
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// When the function returns `false` it means that the condition holds if the condition
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// code flag `cc` is non-zero and doesn't hold if `cc` is zero. If it returns `true`,
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// the roles of zero and non-zero values of the `cc` flag are exchanged.
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bool MaterializeFpCompareR2(IfCondition cond,
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bool gt_bias,
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DataType::Type type,
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LocationSummary* input_locations,
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int cc);
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// When the function returns `false` it means that the condition holds if `dst` is non-zero
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// and doesn't hold if `dst` is zero. If it returns `true`, the roles of zero and non-zero
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// `dst` are exchanged.
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bool MaterializeFpCompareR6(IfCondition cond,
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bool gt_bias,
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DataType::Type type,
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LocationSummary* input_locations,
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FRegister dst);
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void GenerateFpCompareAndBranch(IfCondition cond,
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bool gt_bias,
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DataType::Type type,
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LocationSummary* locations,
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MipsLabel* label);
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void GenerateTestAndBranch(HInstruction* instruction,
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size_t condition_input_index,
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MipsLabel* true_target,
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MipsLabel* false_target);
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void DivRemOneOrMinusOne(HBinaryOperation* instruction);
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void DivRemByPowerOfTwo(HBinaryOperation* instruction);
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void GenerateDivRemWithAnyConstant(HBinaryOperation* instruction);
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void GenerateDivRemIntegral(HBinaryOperation* instruction);
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void HandleGoto(HInstruction* got, HBasicBlock* successor);
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void GenPackedSwitchWithCompares(Register value_reg,
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int32_t lower_bound,
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uint32_t num_entries,
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HBasicBlock* switch_block,
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HBasicBlock* default_block);
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void GenTableBasedPackedSwitch(Register value_reg,
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Register constant_area,
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int32_t lower_bound,
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uint32_t num_entries,
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HBasicBlock* switch_block,
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HBasicBlock* default_block);
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int32_t VecAddress(LocationSummary* locations,
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size_t size,
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/* out */ Register* adjusted_base);
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void GenConditionalMoveR2(HSelect* select);
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void GenConditionalMoveR6(HSelect* select);
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MipsAssembler* const assembler_;
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CodeGeneratorMIPS* const codegen_;
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DISALLOW_COPY_AND_ASSIGN(InstructionCodeGeneratorMIPS);
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};
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class CodeGeneratorMIPS : public CodeGenerator {
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public:
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CodeGeneratorMIPS(HGraph* graph,
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const CompilerOptions& compiler_options,
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OptimizingCompilerStats* stats = nullptr);
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virtual ~CodeGeneratorMIPS() {}
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void ComputeSpillMask() override;
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bool HasAllocatedCalleeSaveRegisters() const override;
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void GenerateFrameEntry() override;
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void GenerateFrameExit() override;
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void Bind(HBasicBlock* block) override;
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void MoveConstant(Location location, HConstant* c);
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size_t GetWordSize() const override { return kMipsWordSize; }
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size_t GetFloatingPointSpillSlotSize() const override {
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return GetGraph()->HasSIMD()
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? 2 * kMipsDoublewordSize // 16 bytes for each spill.
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: 1 * kMipsDoublewordSize; // 8 bytes for each spill.
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}
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uintptr_t GetAddressOf(HBasicBlock* block) override {
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return assembler_.GetLabelLocation(GetLabelOf(block));
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}
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HGraphVisitor* GetLocationBuilder() override { return &location_builder_; }
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HGraphVisitor* GetInstructionVisitor() override { return &instruction_visitor_; }
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MipsAssembler* GetAssembler() override { return &assembler_; }
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const MipsAssembler& GetAssembler() const override { return assembler_; }
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// Emit linker patches.
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void EmitLinkerPatches(ArenaVector<linker::LinkerPatch>* linker_patches) override;
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void EmitJitRootPatches(uint8_t* code, const uint8_t* roots_data) override;
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// Fast path implementation of ReadBarrier::Barrier for a heap
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// reference field load when Baker's read barriers are used.
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void GenerateFieldLoadWithBakerReadBarrier(HInstruction* instruction,
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Location ref,
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Register obj,
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uint32_t offset,
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Location temp,
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bool needs_null_check);
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// Fast path implementation of ReadBarrier::Barrier for a heap
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// reference array load when Baker's read barriers are used.
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void GenerateArrayLoadWithBakerReadBarrier(HInstruction* instruction,
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Location ref,
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Register obj,
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uint32_t data_offset,
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Location index,
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Location temp,
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bool needs_null_check);
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// Factored implementation, used by GenerateFieldLoadWithBakerReadBarrier,
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// GenerateArrayLoadWithBakerReadBarrier and some intrinsics.
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//
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// Load the object reference located at the address
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// `obj + offset + (index << scale_factor)`, held by object `obj`, into
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// `ref`, and mark it if needed.
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//
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// If `always_update_field` is true, the value of the reference is
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// atomically updated in the holder (`obj`).
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void GenerateReferenceLoadWithBakerReadBarrier(HInstruction* instruction,
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Location ref,
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Register obj,
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uint32_t offset,
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Location index,
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ScaleFactor scale_factor,
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Location temp,
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bool needs_null_check,
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bool always_update_field = false);
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// Generate a read barrier for a heap reference within `instruction`
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// using a slow path.
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//
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// A read barrier for an object reference read from the heap is
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// implemented as a call to the artReadBarrierSlow runtime entry
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// point, which is passed the values in locations `ref`, `obj`, and
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// `offset`:
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//
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// mirror::Object* artReadBarrierSlow(mirror::Object* ref,
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// mirror::Object* obj,
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// uint32_t offset);
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//
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// The `out` location contains the value returned by
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// artReadBarrierSlow.
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//
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// When `index` is provided (i.e. for array accesses), the offset
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// value passed to artReadBarrierSlow is adjusted to take `index`
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// into account.
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void GenerateReadBarrierSlow(HInstruction* instruction,
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Location out,
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Location ref,
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Location obj,
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uint32_t offset,
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Location index = Location::NoLocation());
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// If read barriers are enabled, generate a read barrier for a heap
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// reference using a slow path. If heap poisoning is enabled, also
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// unpoison the reference in `out`.
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void MaybeGenerateReadBarrierSlow(HInstruction* instruction,
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Location out,
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Location ref,
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Location obj,
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uint32_t offset,
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Location index = Location::NoLocation());
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// Generate a read barrier for a GC root within `instruction` using
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// a slow path.
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//
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// A read barrier for an object reference GC root is implemented as
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// a call to the artReadBarrierForRootSlow runtime entry point,
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// which is passed the value in location `root`:
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//
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// mirror::Object* artReadBarrierForRootSlow(GcRoot<mirror::Object>* root);
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//
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// The `out` location contains the value returned by
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// artReadBarrierForRootSlow.
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void GenerateReadBarrierForRootSlow(HInstruction* instruction, Location out, Location root);
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void MarkGCCard(Register object, Register value, bool value_can_be_null);
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// Register allocation.
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void SetupBlockedRegisters() const override;
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size_t SaveCoreRegister(size_t stack_index, uint32_t reg_id) override;
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size_t RestoreCoreRegister(size_t stack_index, uint32_t reg_id) override;
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size_t SaveFloatingPointRegister(size_t stack_index, uint32_t reg_id) override;
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size_t RestoreFloatingPointRegister(size_t stack_index, uint32_t reg_id) override;
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void ClobberRA() {
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clobbered_ra_ = true;
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}
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void DumpCoreRegister(std::ostream& stream, int reg) const override;
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void DumpFloatingPointRegister(std::ostream& stream, int reg) const override;
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InstructionSet GetInstructionSet() const override { return InstructionSet::kMips; }
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const MipsInstructionSetFeatures& GetInstructionSetFeatures() const;
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MipsLabel* GetLabelOf(HBasicBlock* block) const {
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return CommonGetLabelOf<MipsLabel>(block_labels_, block);
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}
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void Initialize() override {
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block_labels_ = CommonInitializeLabels<MipsLabel>();
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}
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void Finalize(CodeAllocator* allocator) override;
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// Code generation helpers.
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void MoveLocation(Location dst, Location src, DataType::Type dst_type) override;
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void MoveConstant(Location destination, int32_t value) override;
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void AddLocationAsTemp(Location location, LocationSummary* locations) override;
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// Generate code to invoke a runtime entry point.
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void InvokeRuntime(QuickEntrypointEnum entrypoint,
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HInstruction* instruction,
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uint32_t dex_pc,
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SlowPathCode* slow_path = nullptr) override;
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// Generate code to invoke a runtime entry point, but do not record
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// PC-related information in a stack map.
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void InvokeRuntimeWithoutRecordingPcInfo(int32_t entry_point_offset,
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HInstruction* instruction,
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SlowPathCode* slow_path,
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bool direct);
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void GenerateInvokeRuntime(int32_t entry_point_offset, bool direct);
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ParallelMoveResolver* GetMoveResolver() override { return &move_resolver_; }
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bool NeedsTwoRegisters(DataType::Type type) const override {
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return type == DataType::Type::kInt64;
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}
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// Check if the desired_string_load_kind is supported. If it is, return it,
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// otherwise return a fall-back kind that should be used instead.
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HLoadString::LoadKind GetSupportedLoadStringKind(
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HLoadString::LoadKind desired_string_load_kind) override;
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// Check if the desired_class_load_kind is supported. If it is, return it,
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// otherwise return a fall-back kind that should be used instead.
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HLoadClass::LoadKind GetSupportedLoadClassKind(
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HLoadClass::LoadKind desired_class_load_kind) override;
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// Check if the desired_dispatch_info is supported. If it is, return it,
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// otherwise return a fall-back info that should be used instead.
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HInvokeStaticOrDirect::DispatchInfo GetSupportedInvokeStaticOrDirectDispatch(
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const HInvokeStaticOrDirect::DispatchInfo& desired_dispatch_info,
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ArtMethod* method) override;
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void GenerateStaticOrDirectCall(
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HInvokeStaticOrDirect* invoke, Location temp, SlowPathCode* slow_path = nullptr) override;
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void GenerateVirtualCall(
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HInvokeVirtual* invoke, Location temp, SlowPathCode* slow_path = nullptr) override;
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void MoveFromReturnRegister(Location trg ATTRIBUTE_UNUSED,
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DataType::Type type ATTRIBUTE_UNUSED) override {
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UNIMPLEMENTED(FATAL) << "Not implemented on MIPS";
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}
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void GenerateNop() override;
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void GenerateImplicitNullCheck(HNullCheck* instruction) override;
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void GenerateExplicitNullCheck(HNullCheck* instruction) override;
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// The PcRelativePatchInfo is used for PC-relative addressing of methods/strings/types,
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// whether through .data.bimg.rel.ro, .bss, or directly in the boot image.
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//
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// The 16-bit halves of the 32-bit PC-relative offset are patched separately, necessitating
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// two patches/infos. There can be more than two patches/infos if the instruction supplying
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// the high half is shared with e.g. a slow path, while the low half is supplied by separate
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// instructions, e.g.:
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// lui r1, high // patch
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// addu r1, r1, rbase
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// lw r2, low(r1) // patch
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// beqz r2, slow_path
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// back:
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// ...
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// slow_path:
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// ...
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// sw r2, low(r1) // patch
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// b back
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struct PcRelativePatchInfo : PatchInfo<MipsLabel> {
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PcRelativePatchInfo(const DexFile* dex_file,
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uint32_t off_or_idx,
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const PcRelativePatchInfo* info_high)
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: PatchInfo<MipsLabel>(dex_file, off_or_idx),
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pc_rel_label(),
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patch_info_high(info_high) { }
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// Label for the instruction corresponding to PC+0. Not bound or used in low half patches.
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// Not bound in high half patches on R2 when using HMipsComputeBaseMethodAddress.
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// Bound in high half patches on R2 when using the NAL instruction instead of
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// HMipsComputeBaseMethodAddress.
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// Bound in high half patches on R6.
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MipsLabel pc_rel_label;
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// Pointer to the info for the high half patch or nullptr if this is the high half patch info.
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const PcRelativePatchInfo* patch_info_high;
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private:
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PcRelativePatchInfo(PcRelativePatchInfo&& other) = delete;
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DISALLOW_COPY_AND_ASSIGN(PcRelativePatchInfo);
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};
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PcRelativePatchInfo* NewBootImageIntrinsicPatch(uint32_t intrinsic_data,
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const PcRelativePatchInfo* info_high = nullptr);
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PcRelativePatchInfo* NewBootImageRelRoPatch(uint32_t boot_image_offset,
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const PcRelativePatchInfo* info_high = nullptr);
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PcRelativePatchInfo* NewBootImageMethodPatch(MethodReference target_method,
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const PcRelativePatchInfo* info_high = nullptr);
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PcRelativePatchInfo* NewMethodBssEntryPatch(MethodReference target_method,
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const PcRelativePatchInfo* info_high = nullptr);
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PcRelativePatchInfo* NewBootImageTypePatch(const DexFile& dex_file,
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dex::TypeIndex type_index,
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const PcRelativePatchInfo* info_high = nullptr);
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PcRelativePatchInfo* NewTypeBssEntryPatch(const DexFile& dex_file,
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dex::TypeIndex type_index,
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const PcRelativePatchInfo* info_high = nullptr);
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PcRelativePatchInfo* NewBootImageStringPatch(const DexFile& dex_file,
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dex::StringIndex string_index,
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const PcRelativePatchInfo* info_high = nullptr);
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PcRelativePatchInfo* NewStringBssEntryPatch(const DexFile& dex_file,
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dex::StringIndex string_index,
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const PcRelativePatchInfo* info_high = nullptr);
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Literal* DeduplicateBootImageAddressLiteral(uint32_t address);
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void EmitPcRelativeAddressPlaceholderHigh(PcRelativePatchInfo* info_high,
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Register out,
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Register base);
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void LoadBootImageAddress(Register reg, uint32_t boot_image_reference);
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void AllocateInstanceForIntrinsic(HInvokeStaticOrDirect* invoke, uint32_t boot_image_offset);
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// The JitPatchInfo is used for JIT string and class loads.
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struct JitPatchInfo {
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JitPatchInfo(const DexFile& dex_file, uint64_t idx)
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: target_dex_file(dex_file), index(idx) { }
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JitPatchInfo(JitPatchInfo&& other) = default;
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const DexFile& target_dex_file;
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// String/type index.
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uint64_t index;
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// Label for the instruction loading the most significant half of the address.
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MipsLabel high_label;
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// Label for the instruction supplying the least significant half of the address.
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MipsLabel low_label;
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};
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void PatchJitRootUse(uint8_t* code,
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const uint8_t* roots_data,
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const JitPatchInfo& info,
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uint64_t index_in_table) const;
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JitPatchInfo* NewJitRootStringPatch(const DexFile& dex_file,
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dex::StringIndex string_index,
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Handle<mirror::String> handle);
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JitPatchInfo* NewJitRootClassPatch(const DexFile& dex_file,
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dex::TypeIndex type_index,
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Handle<mirror::Class> handle);
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private:
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Register GetInvokeStaticOrDirectExtraParameter(HInvokeStaticOrDirect* invoke, Register temp);
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using Uint32ToLiteralMap = ArenaSafeMap<uint32_t, Literal*>;
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Literal* DeduplicateUint32Literal(uint32_t value, Uint32ToLiteralMap* map);
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PcRelativePatchInfo* NewPcRelativePatch(const DexFile* dex_file,
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uint32_t offset_or_index,
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const PcRelativePatchInfo* info_high,
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ArenaDeque<PcRelativePatchInfo>* patches);
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template <linker::LinkerPatch (*Factory)(size_t, const DexFile*, uint32_t, uint32_t)>
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void EmitPcRelativeLinkerPatches(const ArenaDeque<PcRelativePatchInfo>& infos,
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ArenaVector<linker::LinkerPatch>* linker_patches);
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// Labels for each block that will be compiled.
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MipsLabel* block_labels_;
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MipsLabel frame_entry_label_;
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LocationsBuilderMIPS location_builder_;
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InstructionCodeGeneratorMIPS instruction_visitor_;
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ParallelMoveResolverMIPS move_resolver_;
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MipsAssembler assembler_;
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// Deduplication map for 32-bit literals, used for non-patchable boot image addresses.
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Uint32ToLiteralMap uint32_literals_;
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// PC-relative method patch info for kBootImageLinkTimePcRelative/kBootImageRelRo.
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// Also used for type/string patches for kBootImageRelRo (same linker patch as for methods).
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ArenaDeque<PcRelativePatchInfo> boot_image_method_patches_;
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// PC-relative method patch info for kBssEntry.
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ArenaDeque<PcRelativePatchInfo> method_bss_entry_patches_;
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// PC-relative type patch info for kBootImageLinkTimePcRelative.
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ArenaDeque<PcRelativePatchInfo> boot_image_type_patches_;
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// PC-relative type patch info for kBssEntry.
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ArenaDeque<PcRelativePatchInfo> type_bss_entry_patches_;
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// PC-relative String patch info for kBootImageLinkTimePcRelative.
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ArenaDeque<PcRelativePatchInfo> boot_image_string_patches_;
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// PC-relative String patch info for kBssEntry.
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ArenaDeque<PcRelativePatchInfo> string_bss_entry_patches_;
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// PC-relative patch info for IntrinsicObjects.
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ArenaDeque<PcRelativePatchInfo> boot_image_intrinsic_patches_;
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// Patches for string root accesses in JIT compiled code.
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ArenaDeque<JitPatchInfo> jit_string_patches_;
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// Patches for class root accesses in JIT compiled code.
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ArenaDeque<JitPatchInfo> jit_class_patches_;
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// PC-relative loads on R2 clobber RA, which may need to be preserved explicitly in leaf methods.
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// This is a flag set by pc_relative_fixups_mips and dex_cache_array_fixups_mips optimizations.
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bool clobbered_ra_;
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DISALLOW_COPY_AND_ASSIGN(CodeGeneratorMIPS);
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};
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} // namespace mips
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} // namespace art
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#endif // ART_COMPILER_OPTIMIZING_CODE_GENERATOR_MIPS_H_
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