/*
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* Copyright (C) 2016 The Android Open Source Project
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef ART_COMPILER_DEBUG_ELF_DEBUG_FRAME_WRITER_H_
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#define ART_COMPILER_DEBUG_ELF_DEBUG_FRAME_WRITER_H_
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#include <vector>
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#include "arch/instruction_set.h"
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#include "debug/method_debug_info.h"
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#include "dwarf/debug_frame_opcode_writer.h"
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#include "dwarf/dwarf_constants.h"
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#include "dwarf/headers.h"
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#include "elf/elf_builder.h"
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namespace art {
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namespace debug {
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static constexpr bool kWriteDebugFrameHdr = false;
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static void WriteCIE(InstructionSet isa, /*inout*/ std::vector<uint8_t>* buffer) {
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using Reg = dwarf::Reg;
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// Scratch registers should be marked as undefined. This tells the
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// debugger that its value in the previous frame is not recoverable.
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bool is64bit = Is64BitInstructionSet(isa);
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switch (isa) {
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case InstructionSet::kArm:
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case InstructionSet::kThumb2: {
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dwarf::DebugFrameOpCodeWriter<> opcodes;
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opcodes.DefCFA(Reg::ArmCore(13), 0); // R13(SP).
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// core registers.
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for (int reg = 0; reg < 13; reg++) {
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if (reg < 4 || reg == 12) {
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opcodes.Undefined(Reg::ArmCore(reg));
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} else {
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opcodes.SameValue(Reg::ArmCore(reg));
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}
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}
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// fp registers.
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for (int reg = 0; reg < 32; reg++) {
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if (reg < 16) {
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opcodes.Undefined(Reg::ArmFp(reg));
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} else {
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opcodes.SameValue(Reg::ArmFp(reg));
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}
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}
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auto return_reg = Reg::ArmCore(14); // R14(LR).
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WriteCIE(is64bit, return_reg, opcodes, buffer);
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return;
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}
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case InstructionSet::kArm64: {
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dwarf::DebugFrameOpCodeWriter<> opcodes;
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opcodes.DefCFA(Reg::Arm64Core(31), 0); // R31(SP).
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// core registers.
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for (int reg = 0; reg < 30; reg++) {
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if (reg < 8 || reg == 16 || reg == 17) {
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opcodes.Undefined(Reg::Arm64Core(reg));
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} else {
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opcodes.SameValue(Reg::Arm64Core(reg));
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}
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}
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// fp registers.
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for (int reg = 0; reg < 32; reg++) {
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if (reg < 8 || reg >= 16) {
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opcodes.Undefined(Reg::Arm64Fp(reg));
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} else {
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opcodes.SameValue(Reg::Arm64Fp(reg));
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}
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}
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auto return_reg = Reg::Arm64Core(30); // R30(LR).
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WriteCIE(is64bit, return_reg, opcodes, buffer);
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return;
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}
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case InstructionSet::kMips:
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case InstructionSet::kMips64: {
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dwarf::DebugFrameOpCodeWriter<> opcodes;
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opcodes.DefCFA(Reg::MipsCore(29), 0); // R29(SP).
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// core registers.
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for (int reg = 1; reg < 26; reg++) {
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if (reg < 16 || reg == 24 || reg == 25) { // AT, V*, A*, T*.
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opcodes.Undefined(Reg::MipsCore(reg));
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} else {
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opcodes.SameValue(Reg::MipsCore(reg));
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}
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}
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// fp registers.
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for (int reg = 0; reg < 32; reg++) {
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if (reg < 24) {
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opcodes.Undefined(Reg::Mips64Fp(reg));
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} else {
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opcodes.SameValue(Reg::Mips64Fp(reg));
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}
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}
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auto return_reg = Reg::MipsCore(31); // R31(RA).
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WriteCIE(is64bit, return_reg, opcodes, buffer);
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return;
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}
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case InstructionSet::kX86: {
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// FIXME: Add fp registers once libunwind adds support for them. Bug: 20491296
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constexpr bool generate_opcodes_for_x86_fp = false;
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dwarf::DebugFrameOpCodeWriter<> opcodes;
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opcodes.DefCFA(Reg::X86Core(4), 4); // R4(ESP).
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opcodes.Offset(Reg::X86Core(8), -4); // R8(EIP).
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// core registers.
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for (int reg = 0; reg < 8; reg++) {
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if (reg <= 3) {
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opcodes.Undefined(Reg::X86Core(reg));
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} else if (reg == 4) {
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// Stack pointer.
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} else {
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opcodes.SameValue(Reg::X86Core(reg));
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}
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}
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// fp registers.
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if (generate_opcodes_for_x86_fp) {
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for (int reg = 0; reg < 8; reg++) {
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opcodes.Undefined(Reg::X86Fp(reg));
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}
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}
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auto return_reg = Reg::X86Core(8); // R8(EIP).
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WriteCIE(is64bit, return_reg, opcodes, buffer);
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return;
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}
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case InstructionSet::kX86_64: {
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dwarf::DebugFrameOpCodeWriter<> opcodes;
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opcodes.DefCFA(Reg::X86_64Core(4), 8); // R4(RSP).
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opcodes.Offset(Reg::X86_64Core(16), -8); // R16(RIP).
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// core registers.
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for (int reg = 0; reg < 16; reg++) {
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if (reg == 4) {
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// Stack pointer.
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} else if (reg < 12 && reg != 3 && reg != 5) { // except EBX and EBP.
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opcodes.Undefined(Reg::X86_64Core(reg));
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} else {
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opcodes.SameValue(Reg::X86_64Core(reg));
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}
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}
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// fp registers.
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for (int reg = 0; reg < 16; reg++) {
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if (reg < 12) {
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opcodes.Undefined(Reg::X86_64Fp(reg));
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} else {
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opcodes.SameValue(Reg::X86_64Fp(reg));
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}
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}
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auto return_reg = Reg::X86_64Core(16); // R16(RIP).
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WriteCIE(is64bit, return_reg, opcodes, buffer);
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return;
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}
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case InstructionSet::kNone:
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break;
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}
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LOG(FATAL) << "Cannot write CIE frame for ISA " << isa;
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UNREACHABLE();
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}
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template<typename ElfTypes>
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void WriteCFISection(ElfBuilder<ElfTypes>* builder,
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const ArrayRef<const MethodDebugInfo>& method_infos) {
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typedef typename ElfTypes::Addr Elf_Addr;
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// The methods can be written in any order.
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// Let's therefore sort them in the lexicographical order of the opcodes.
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// This has no effect on its own. However, if the final .debug_frame section is
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// compressed it reduces the size since similar opcodes sequences are grouped.
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std::vector<const MethodDebugInfo*> sorted_method_infos;
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sorted_method_infos.reserve(method_infos.size());
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for (size_t i = 0; i < method_infos.size(); i++) {
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if (!method_infos[i].cfi.empty() && !method_infos[i].deduped) {
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sorted_method_infos.push_back(&method_infos[i]);
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}
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}
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if (sorted_method_infos.empty()) {
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return;
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}
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std::stable_sort(
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sorted_method_infos.begin(),
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sorted_method_infos.end(),
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[](const MethodDebugInfo* lhs, const MethodDebugInfo* rhs) {
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ArrayRef<const uint8_t> l = lhs->cfi;
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ArrayRef<const uint8_t> r = rhs->cfi;
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return std::lexicographical_compare(l.begin(), l.end(), r.begin(), r.end());
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});
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std::vector<uint32_t> binary_search_table;
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if (kWriteDebugFrameHdr) {
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binary_search_table.reserve(2 * sorted_method_infos.size());
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}
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// Write .debug_frame section.
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auto* cfi_section = builder->GetDebugFrame();
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{
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cfi_section->Start();
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const bool is64bit = Is64BitInstructionSet(builder->GetIsa());
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std::vector<uint8_t> buffer; // Small temporary buffer.
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WriteCIE(builder->GetIsa(), &buffer);
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cfi_section->WriteFully(buffer.data(), buffer.size());
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buffer.clear();
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for (const MethodDebugInfo* mi : sorted_method_infos) {
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DCHECK(!mi->deduped);
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DCHECK(!mi->cfi.empty());
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const Elf_Addr code_address = mi->code_address +
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(mi->is_code_address_text_relative ? builder->GetText()->GetAddress() : 0);
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if (kWriteDebugFrameHdr) {
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binary_search_table.push_back(dchecked_integral_cast<uint32_t>(code_address));
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binary_search_table.push_back(cfi_section->GetPosition());
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}
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dwarf::WriteFDE(is64bit,
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/* cie_pointer= */ 0,
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code_address,
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mi->code_size,
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mi->cfi,
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&buffer);
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cfi_section->WriteFully(buffer.data(), buffer.size());
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buffer.clear();
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}
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cfi_section->End();
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}
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if (kWriteDebugFrameHdr) {
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std::sort(binary_search_table.begin(), binary_search_table.end());
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// Custom Android section. It is very similar to the official .eh_frame_hdr format.
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std::vector<uint8_t> header_buffer;
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dwarf::Writer<> header(&header_buffer);
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header.PushUint8(1); // Version.
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header.PushUint8(dwarf::DW_EH_PE_omit); // Encoding of .eh_frame pointer - none.
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header.PushUint8(dwarf::DW_EH_PE_udata4); // Encoding of binary search table size.
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header.PushUint8(dwarf::DW_EH_PE_udata4); // Encoding of binary search table data.
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header.PushUint32(dchecked_integral_cast<uint32_t>(binary_search_table.size()/2));
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auto* header_section = builder->GetDebugFrameHdr();
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header_section->Start();
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header_section->WriteFully(header_buffer.data(), header_buffer.size());
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header_section->WriteFully(binary_search_table.data(), binary_search_table.size());
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header_section->End();
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}
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}
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} // namespace debug
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} // namespace art
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#endif // ART_COMPILER_DEBUG_ELF_DEBUG_FRAME_WRITER_H_
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