/*
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* (C) Copyright 2007-2013
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* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
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* Jerry Wang <wangflord@allwinnertech.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/gic.h>
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#include <sunxi_board.h>
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DECLARE_GLOBAL_DATA_PTR;
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struct _irq_handler
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{
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void *m_data;
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void (*m_func)( void * data);
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};
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struct _irq_handler sunxi_int_handlers[GIC_IRQ_NUM];
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extern int interrupts_is_open(void);
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static void gic_spi_set_target(int irq_no, int cpu_id);
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static void default_isr(void *data)
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{
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printf("default_isr(): called from IRQ %d\n", (uint)data);
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while(1);
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}
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int irq_enable(int irq_no)
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{
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uint reg_val;
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uint offset;
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if (irq_no >= GIC_IRQ_NUM) {
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printf("irq NO.(%d) > GIC_IRQ_NUM(%d) !!\n", irq_no, GIC_IRQ_NUM);
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return -1;
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}
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if(irq_no == AW_IRQ_NMI) {
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*(volatile unsigned int *)(0x01f00c00 + 0x10) |= 1;
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*(volatile unsigned int *)(0x01f00c00 + 0x40) |= 1;
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}
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//gic_spi_set_target(irq_no, get_core_pos());
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offset = irq_no >> 5;
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reg_val = readl(GIC_SET_EN(offset));
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reg_val |= 1 << (irq_no & 0x1f);
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writel(reg_val, GIC_SET_EN(offset));
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return 0;
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}
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int irq_disable(int irq_no)
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{
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uint reg_val;
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uint offset;
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if (irq_no >= GIC_IRQ_NUM) {
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printf("irq NO.(%d) > GIC_IRQ_NUM(%d) !!\n", irq_no, GIC_IRQ_NUM);
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return -1;
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}
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if(irq_no == AW_IRQ_NMI) {
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*(volatile unsigned int *)(0x01f00c00 + 0x10) |= 1;
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*(volatile unsigned int *)(0x01f00c00 + 0x40) &= ~1;
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}
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gic_spi_set_target(irq_no, 0);
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offset = irq_no >> 5;
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reg_val = (1 << (irq_no & 0x1f));
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writel(reg_val, GIC_CLR_EN(offset));
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return 0;
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}
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static void gic_sgi_handler(uint irq_no)
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{
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printf("SGI irq %d coming... \n", irq_no);
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}
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static void gic_ppi_handler(uint irq_no)
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{
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printf("PPI irq %d coming... \n", irq_no);
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}
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static void gic_spi_handler(uint irq_no)
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{
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if (sunxi_int_handlers[irq_no].m_func != default_isr)
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{
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sunxi_int_handlers[irq_no].m_func(sunxi_int_handlers[irq_no].m_data);
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}
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}
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static void gic_clear_pending(uint irq_no)
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{
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uint reg_val;
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uint offset;
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offset = irq_no >> 5;
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//reg_val = readl(GIC_PEND_CLR(offset));
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reg_val = (1 << (irq_no & 0x1f));
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writel(reg_val, GIC_PEND_CLR(offset));
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return ;
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}
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void irq_install_handler (int irq, interrupt_handler_t handle_irq, void *data)
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{
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int flag = interrupts_is_open();
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//when irq_handler call this function , irq enable bit has already disabled in irq_mode,so don't need to enable I bit
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if(flag)
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{
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disable_interrupts();
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}
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if (irq >= GIC_IRQ_NUM || !handle_irq)
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{
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goto __END;
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}
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sunxi_int_handlers[irq].m_data = data;
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sunxi_int_handlers[irq].m_func = handle_irq;
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__END:
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if(flag)
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{
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enable_interrupts();
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}
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}
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void irq_free_handler(int irq)
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{
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disable_interrupts();
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if (irq >= GIC_IRQ_NUM)
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{
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enable_interrupts();
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return;
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}
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sunxi_int_handlers[irq].m_data = NULL;
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sunxi_int_handlers[irq].m_func = default_isr;
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enable_interrupts();
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}
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void do_irq (struct pt_regs *pt_regs)
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{
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u32 idnum;
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#ifdef CONFIG_ARCH_SUN8IW6P1
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/* fix gic bug when enable secure*/
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if (sunxi_probe_secure_os())
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idnum = readl(GIC_AIAR_REG);
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else
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idnum = readl(GIC_INT_ACK_REG);
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#else
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idnum = readl(GIC_INT_ACK_REG);
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#endif
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if ((idnum == 1022) || (idnum == 1023))
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{
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printf("spurious irq !!\n");
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return;
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}
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if (idnum >= GIC_IRQ_NUM) {
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debug("irq NO.(%d) > GIC_IRQ_NUM(%d) !!\n", idnum, GIC_IRQ_NUM-32);
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return;
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}
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if (idnum < 16)
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gic_sgi_handler(idnum);
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else if (idnum < 32)
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gic_ppi_handler(idnum);
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else
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gic_spi_handler(idnum);
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#ifdef CONFIG_ARCH_SUN8IW6P1
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/* fix gic bug when enable secure*/
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if (sunxi_probe_secure_os())
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writel(idnum, GIC_AEOI_REG);
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else
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writel(idnum, GIC_END_INT_REG);
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#else
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writel(idnum, GIC_END_INT_REG);
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#endif
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writel(idnum, GIC_DEACT_INT_REG);
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gic_clear_pending(idnum);
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return;
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}
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int do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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int irq;
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printf("Interrupt-Information:\n");
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printf("Nr(Max) Routine Arg\n");
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for (irq = 0; irq < GIC_IRQ_NUM; irq ++)
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{
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if (sunxi_int_handlers[irq].m_func != NULL)
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{
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printf("%d(%d) 0x%08lx 0x%08lx\n",
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irq, GIC_IRQ_NUM,
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(ulong)sunxi_int_handlers[irq].m_func,
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(ulong)sunxi_int_handlers[irq].m_data);
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}
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}
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return 0;
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}
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static void gic_distributor_init(void)
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{
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__u32 cpumask = 0x01010101;
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__u32 gic_irqs;
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__u32 i;
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writel(0, GIC_DIST_CON);
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/* check GIC hardware configutation */
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gic_irqs = ((readl(GIC_CON_TYPE) & 0x1f) + 1) * 32;
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if (gic_irqs > 1020) {
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gic_irqs = 1020;
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}
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if (gic_irqs < GIC_IRQ_NUM) {
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debug("GIC parameter config error, only support %d"
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" irqs < %d(spec define)!!\n", gic_irqs, GIC_IRQ_NUM);
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return ;
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}
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/* set trigger type to be level-triggered, active low */
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for (i=0; i<GIC_IRQ_NUM; i+=16) {
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writel(0, GIC_IRQ_MOD_CFG(i>>4));
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}
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/* set priority */
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for (i=GIC_SRC_SPI(0); i<GIC_IRQ_NUM; i+=4) {
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writel(0xa0a0a0a0, GIC_SPI_PRIO((i-32)>>2));
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}
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/* set processor target */
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for (i=32; i<GIC_IRQ_NUM; i+=4) {
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writel(cpumask, GIC_SPI_PROC_TARG((i-32)>>2));
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}
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/* disable all interrupts */
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for (i=32; i<GIC_IRQ_NUM; i+=32) {
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writel(0xffffffff, GIC_CLR_EN(i>>5));
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}
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/* clear all interrupt active state */
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for (i=32; i<GIC_IRQ_NUM; i+=32) {
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writel(0xffffffff, GIC_ACT_CLR(i>>5));
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}
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writel(1, GIC_DIST_CON);
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return ;
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}
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static void gic_cpuif_init(void)
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{
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uint i;
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writel(0, GIC_CPU_IF_CTRL);
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/*
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* Deal with the banked PPI and SGI interrupts - disable all
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* PPI interrupts, ensure all SGI interrupts are enabled.
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*/
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writel(0xffff0000, GIC_CLR_EN(0));
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writel(0x0000ffff, GIC_SET_EN(0));
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/* Set priority on PPI and SGI interrupts */
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for (i=0; i<16; i+=4) {
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writel(0xa0a0a0a0, GIC_SGI_PRIO(i>>2));
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}
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for (i=16; i<32; i+=4) {
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writel(0xa0a0a0a0, GIC_PPI_PRIO((i-16)>>2));
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}
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writel(0xf0, GIC_INT_PRIO_MASK);
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writel(1, GIC_CPU_IF_CTRL);
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return ;
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}
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static void gic_spi_set_target(int irq_no, int cpu_id)
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{
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uint reg_val, addr, offset;
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irq_no -= 32;
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/* dispatch the usb interrupt to CPU1 */
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addr = GIC_SPI_PROC_TARG(irq_no>>2);
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reg_val = readl(addr);
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offset = 8 * (irq_no & 3);
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reg_val &= ~(0xff<<offset);
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reg_val |= (((1<<cpu_id) & 0xf) <<offset);
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writel(reg_val, addr);
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return ;
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}
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int arch_interrupt_init (void)
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{
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int i;
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for (i=0; i<GIC_IRQ_NUM; i++)
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sunxi_int_handlers[i].m_data = default_isr;
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if (sunxi_probe_secure_monitor() || sunxi_probe_secure_os())
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tick_printf("gic: sec monitor mode\n");
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else {
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tick_printf("gic: normal mode\n");
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gic_distributor_init();
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gic_cpuif_init();
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}
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return 0;
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}
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int arch_interrupt_exit(void)
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{
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if (!(sunxi_probe_secure_monitor() || sunxi_probe_secure_os())) {
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gic_distributor_init();
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gic_cpuif_init();
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}
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return 0;
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}
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int sunxi_gic_cpu_interface_init(int cpu)
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{
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gic_cpuif_init();
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return 0;
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}
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int sunxi_gic_cpu_interface_exit(void)
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{
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writel(0, GIC_CPU_IF_CTRL);
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return 0;
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}
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