/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2015 Hans de Goede <hdegoede@redhat.com>
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*
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* Configuration settings for the Allwinner A80 (sun9i) CPU
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/timer.h>
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void clock_init_uart(void)
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{
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struct sunxi_ccm_reg *const ccm =
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(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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/* uart clock source is apb2 */
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writel(APB2_CLK_SRC_OSC24M|
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APB2_CLK_RATE_N_1|
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APB2_CLK_RATE_M(1),
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&ccm->apb2_cfg);
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/* open the clock for uart */
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setbits_le32(&ccm->uart_gate_reset,
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1 << (CONFIG_CONS_INDEX - 1));
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/* deassert uart reset */
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setbits_le32(&ccm->uart_gate_reset,
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1 << (RESET_SHIFT + CONFIG_CONS_INDEX - 1));
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}
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uint clock_get_pll5(void)
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{
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struct sunxi_ccm_reg *const ccm =
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(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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uint reg_val;
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uint factor_n, factor_m0, factor_m1, pll5;
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reg_val = readl(&ccm->pll5_cfg);
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factor_n = ((reg_val >> 8) & 0xff) + 1;
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factor_m0 = ((reg_val >> 0) & 0x01) + 1;
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factor_m1 = ((reg_val >> 1) & 0x01) + 1;
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/*default DDR0 is 432M */
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pll5 = (24 * factor_n /factor_m0/factor_m1)>>1;
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return pll5;
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}
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uint clock_get_pll6(void)
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{
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struct sunxi_ccm_reg *const ccm =
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(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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uint reg_val;
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uint factor_n, factor_m0, factor_m1, pll6;
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reg_val = readl(&ccm->pll6_cfg);
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factor_n = ((reg_val >> 8) & 0xff) + 1;
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factor_m0 = ((reg_val >> 0) & 0x01) + 1;
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factor_m1 = ((reg_val >> 1) & 0x01) + 1;
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/*default is 1200M, 1X is 600M */
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pll6 = (24 * factor_n /factor_m0/factor_m1)>>1;
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return pll6;
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}
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uint clock_get_corepll(void)
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{
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struct sunxi_ccm_reg *const ccm =
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(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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unsigned int reg_val;
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int div_m, div_p;
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int factor_n;
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int clock, clock_src;
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reg_val = readl(&ccm->cpu_axi_cfg);
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clock_src = (reg_val >> 24) & 0x03;
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switch (clock_src) {
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case 0://OSC24M
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clock = 24;
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break;
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case 1://RTC32K
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clock = 32/1000 ;
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break;
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case 2://RC16M
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clock = 16;
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break;
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case 3://PLL_CPUX
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reg_val = readl(&ccm->pll1_cfg);
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div_p = 1<<((reg_val >>16) & 0x3);
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factor_n = ((reg_val >> 8) & 0xff) + 1;
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div_m = ((reg_val >> 0) & 0x3) + 1;
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clock = 24*factor_n/div_m/div_p;
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break;
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default:
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return 0;
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}
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return clock;
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}
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static int clk_get_pll_para(struct core_pll_freq_tbl *factor, int pll_clk)
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{
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int index;
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index = pll_clk / 24;
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factor->FactorP = 0;
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factor->FactorN = (index - 1);
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factor->FactorM = 0;
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return 0;
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}
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int clock_set_corepll(int frequency)
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{
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unsigned int reg_val = 0;
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struct sunxi_ccm_reg *const ccm =
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(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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struct core_pll_freq_tbl pll_factor;
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if (frequency == clock_get_corepll())
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return 0;
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else if (frequency >= 1008)
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frequency = 1008;
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/* switch to 24M*/
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reg_val = readl(&ccm->cpu_axi_cfg);
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reg_val &= ~(0x03 << 24);
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writel(reg_val, &ccm->cpu_axi_cfg);
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__udelay(20);
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/*pll output disable*/
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reg_val = readl(&ccm->pll1_cfg);
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reg_val &= ~(0x01 << 27);
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writel(reg_val, &ccm->pll1_cfg);
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/*get config para form freq table*/
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clk_get_pll_para(&pll_factor, frequency);
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reg_val = readl(&ccm->pll1_cfg);
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reg_val &= ~((0x03 << 16) | (0xff << 8) | (0x03 << 0));
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reg_val |= (pll_factor.FactorP << 16) | (pll_factor.FactorN << 8) | (pll_factor.FactorM << 0) ;
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writel(reg_val, &ccm->pll1_cfg);
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__udelay(20);
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/*enable lock*/
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reg_val = readl(&ccm->pll1_cfg);
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reg_val |= (0x1 << 29);
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writel(reg_val, &ccm->pll1_cfg);
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#ifndef FPGA_PLATFORM
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do {
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reg_val = readl(&ccm->pll1_cfg);
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} while (!(reg_val & (0x1 << 28)));
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#endif
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/*enable pll output*/
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reg_val = readl(&ccm->pll1_cfg);
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reg_val |= (0x1 << 27);
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writel(reg_val, &ccm->pll1_cfg);
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/* switch clk src to COREPLL*/
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reg_val = readl(&ccm->cpu_axi_cfg);
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reg_val &= ~(0x03 << 24);
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reg_val |= (0x03 << 24);
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writel(reg_val, &ccm->cpu_axi_cfg);
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return 0;
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}
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uint clock_get_axi(void)
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{
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struct sunxi_ccm_reg *const ccm =
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(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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unsigned int reg_val = 0;
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int factor = 0;
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int clock = 0;
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reg_val = readl(&ccm->cpu_axi_cfg);
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factor = ((reg_val >> 0) & 0x03) + 1;
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clock = clock_get_corepll()/factor;
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return clock;
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}
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uint clock_get_ahb(void)
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{
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struct sunxi_ccm_reg *const ccm =
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(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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unsigned int reg_val = 0;
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int factor_m = 0, factor_n = 0;
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int clock = 0;
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int src = 0, src_clock = 0;
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reg_val = readl(&ccm->psi_ahb1_ahb2_cfg);
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src = (reg_val >> 24)&0x3;
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factor_m = ((reg_val >> 0) & 0x03) + 1;
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factor_n = 1<< ((reg_val >> 8) & 0x03);
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switch (src) {
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case 0: //OSC24M
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src_clock = 24;
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break;
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case 1: //CCMU_32K
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src_clock = 32 / 1000;
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break;
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case 2: //RC16M
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src_clock = 16;
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break;
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case 3: //PLL_PERI0(1X)
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src_clock = clock_get_pll6();
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break;
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default:
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return 0;
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}
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clock = src_clock/factor_m/factor_n;
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return clock;
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}
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uint clock_get_apb1(void)
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{
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struct sunxi_ccm_reg *const ccm =
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(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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unsigned int reg_val = 0;
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int src = 0, src_clock = 0;
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int clock = 0, factor_m = 0, factor_n = 0;
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reg_val = readl(&ccm->apb1_cfg);
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factor_m = ((reg_val >> 0) & 0x03) + 1;
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factor_n = 1<<((reg_val >> 8) & 0x03);
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src = (reg_val >> 24)&0x3;
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switch (src) {
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case 0: //OSC24M
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src_clock = 24;
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break;
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case 1: //CCMU_32K
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src_clock = 32 / 1000;
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break;
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case 2: //PSI
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src_clock = clock_get_ahb();
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break;
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case 3: //PLL_PERI0(1X)
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src_clock = clock_get_pll6();
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break;
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default:
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return 0;
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}
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clock = src_clock/factor_m/factor_n;
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return clock;
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}
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uint clock_get_apb2(void)
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{
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struct sunxi_ccm_reg *const ccm =
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(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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unsigned int reg_val = 0;
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int clock = 0, factor_m = 0, factor_n = 0;
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int src = 0, src_clock = 0;
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reg_val = readl(&ccm->apb2_cfg);
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src = (reg_val >> 24)&0x3;
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factor_m = ((reg_val >> 0) & 0x03) + 1;
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factor_n = ((reg_val >> 8) & 0x03) + 1;
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switch (src) {
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case 0: //OSC24M
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src_clock = 24;
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break;
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case 1: //CCMU_32K
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src_clock = 32 / 1000;
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break;
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case 2: //PSI
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src_clock = clock_get_ahb();
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break;
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case 3: //PSI
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src_clock = clock_get_pll6();
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break;
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default:
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return 0;
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}
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clock = src_clock/factor_m/factor_n;
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return clock;
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}
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uint clock_get_mbus(void)
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{
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struct sunxi_ccm_reg *const ccm =
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(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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unsigned int reg_val;
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unsigned int src = 0, clock = 0, div = 0;
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reg_val = readl(&ccm->dram_clk_cfg);
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/*get src*/
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src = (reg_val >> 24)&0x3;
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/*get div M, the divided clock is divided by M+1*/
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div = (reg_val&0x3) + 1;
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switch (src) {
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case 0: /*src is DDR0*/
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clock = clock_get_pll5();
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break;
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case 1: /*src is pll_periph0(1x)/2*/
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clock = clock_get_pll6() * 2;
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break;
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}
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/*mbus clk=dram clk/4*/
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clock = (clock/div)/4;
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return clock;
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}
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int usb_open_clock(void)
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{
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u32 reg_value = 0;
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//USB0 Clock Reg
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//bit30: USB PHY0 reset
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//Bit29: Gating Special Clk for USB PHY0
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reg_value = readl(SUNXI_CCM_BASE + 0xA70);
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reg_value |= (1 << 29) | (1 << 30);
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writel(reg_value, (SUNXI_CCM_BASE + 0xA70));
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//delay some time
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__msdelay(1);
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//USB BUS Gating Reset Reg
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//bit8:USB_OTG Gating
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reg_value = readl(SUNXI_CCM_BASE + 0xA8C);
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reg_value |= (1 << 8);
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writel(reg_value, (SUNXI_CCM_BASE + 0xA8C));
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//delay to wati SIE stable
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__msdelay(1);
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//USB BUS Gating Reset Reg: USB_OTG reset
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reg_value = readl(SUNXI_CCM_BASE + 0xA8C);
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reg_value |= (1 << 24);
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writel(reg_value, (SUNXI_CCM_BASE + 0xA8C));
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__msdelay(1);
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reg_value = readl(SUNXI_USBOTG_BASE + 0x420);
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reg_value |= (0x01 << 0);
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writel(reg_value, (SUNXI_USBOTG_BASE + 0x420));
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__msdelay(1);
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return 0;
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}
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int usb_close_clock(void)
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{
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u32 reg_value = 0;
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/* AHB reset */
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reg_value = readl(SUNXI_CCM_BASE + 0xA8C);
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reg_value &= ~(1 << 24);
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writel(reg_value, (SUNXI_CCM_BASE + 0xA8C));
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__msdelay(1);
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reg_value = readl(SUNXI_CCM_BASE + 0xA8C);
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reg_value &= ~(1 << 8);
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writel(reg_value, (SUNXI_CCM_BASE + 0xA8C));
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__msdelay(1);
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reg_value = readl(SUNXI_CCM_BASE + 0xcc);
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reg_value &= ~((1 << 29) | (1 << 30));
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writel(reg_value, (SUNXI_CCM_BASE + 0xcc));
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__msdelay(1);
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return 0;
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}
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