// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
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*
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* (C) Copyright 2007-2011
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* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
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* Tom Cubie <tangliang@allwinnertech.com>
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*
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* Some init for sunxi platform.
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*/
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#include <common.h>
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#include <mmc.h>
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#include <i2c.h>
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#include <serial.h>
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#include <spl.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/spl.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/timer.h>
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#include <asm/arch/tzpc.h>
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#include <asm/arch/mmc.h>
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#include <linux/compiler.h>
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#include <spare_head.h>
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#include <private_uboot.h>
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#include <asm/arch/efuse.h>
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#include <asm/arch/dram.h>
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#include <asm/sections.h>
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static int gpio_init(void)
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{
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return 0;
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}
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void s_init(void)
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{
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#if !defined(CONFIG_ARM_CORTEX_CPU_IS_UP) && !defined(CONFIG_ARM64)
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/* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
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asm volatile(
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"mrc p15, 0, r0, c1, c0, 1\n"
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"orr r0, r0, #1 << 6\n"
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"mcr p15, 0, r0, c1, c0, 1\n"
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::: "r0");
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#endif
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clock_init();
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timer_init();
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gpio_init();
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eth_init_board();
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}
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/* The sunxi internal brom will try to loader external bootloader
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* from mmc0, nand flash, mmc2.
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*/
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uint32_t sunxi_get_boot_device(void)
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{
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int boot_source;
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/*
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* When booting from the SD card or NAND memory, the "eGON.BT0"
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* signature is expected to be found in memory at the address 0x0004
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* (see the "mksunxiboot" tool, which generates this header).
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*
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* When booting in the FEL mode over USB, this signature is patched in
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* memory and replaced with something else by the 'fel' tool. This other
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* signature is selected in such a way, that it can't be present in a
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* valid bootable SD card image (because the BROM would refuse to
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* execute the SPL in this case).
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*
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* This checks for the signature and if it is not found returns to
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* the FEL code in the BROM to wait and receive the main u-boot
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* binary over USB. If it is found, it determines where SPL was
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* read from.
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*/
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if (!is_boot0_magic(SPL_ADDR + 4)) /* eGON.BT0 */
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return BOOT_DEVICE_BOARD;
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boot_source = readb(SPL_ADDR + 0x28);
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switch (boot_source) {
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case SUNXI_BOOTED_FROM_MMC0:
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return BOOT_DEVICE_MMC1;
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case SUNXI_BOOTED_FROM_NAND:
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return BOOT_DEVICE_NAND;
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case SUNXI_BOOTED_FROM_MMC2:
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return BOOT_DEVICE_MMC2;
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case SUNXI_BOOTED_FROM_SPI:
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return BOOT_DEVICE_SPI;
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}
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panic("Unknown boot source %d\n", boot_source);
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return -1; /* Never reached */
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}
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void reset_cpu(ulong addr)
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{
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#if defined(CONFIG_SUNXI_GEN_SUN4I) || defined(CONFIG_MACH_SUN8I_R40)
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static const struct sunxi_wdog *wdog =
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&((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
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/* Set the watchdog for its shortest interval (.5s) and wait */
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writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
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writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl);
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while (1) {
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/* sun5i sometimes gets stuck without this */
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writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
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}
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#elif defined(CONFIG_SUNXI_GEN_SUN6I)
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static const struct sunxi_wdog *wdog =
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((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
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/* Set the watchdog for its shortest interval (.5s) and wait */
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writel(WDT_CFG_RESET, &wdog->cfg);
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writel(WDT_MODE_EN, &wdog->mode);
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writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl);
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while (1) { }
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#elif defined(CONFIG_SUNXI_NCAT)
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static const struct sunxi_wdog *wdog =
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((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
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/* Set the watchdog for its shortest interval (.5s) and wait */
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writel(WDT_CFG_RESET, &wdog->cfg);
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writel(WDT_MODE_EN, &wdog->mode);
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while (1) { }
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#elif defined(CONFIG_SUNXI_VERSION1)
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struct sunxi_timer_reg *timer_reg = (struct sunxi_timer_reg *)SUNXI_TIMER_BASE;
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struct sunxi_wdog *wdog = &timer_reg->wdog[0];
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/* enable watchdog */
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wdog->mode |= 3;
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while (1) { }
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#endif
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}
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void * board_fdt_blob_setup(void)
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{
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/* check u-boot with dtb.bin*/
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if (fdt_check_header(&_end) == 0)
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return (void *)&_end;
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/* uboot base + 2M offset */
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return (void*)(CONFIG_SYS_TEXT_BASE + SUNXI_DTB_OFFSET);
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}
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#if !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
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void enable_caches(void)
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{
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/* Enable D-cache. I-cache is already enabled in start.S */
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dcache_enable();
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}
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#endif
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