/*
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* Copyright (C) 2019 Allwinner Technology Limited. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <asm/io.h>
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#include <linux/clk.h>
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#include <linux/slab.h>
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#include <linux/platform_device.h>
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#include <asm/uaccess.h>
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#include "platform.h"
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#include <linux/clk-provider.h>
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#include <linux/pm_runtime.h>
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#include <linux/pm_opp.h>
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#include <linux/regulator/consumer.h>
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#ifdef CONFIG_DEVFREQ_THERMAL
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#include <linux/devfreq_cooling.h>
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#endif
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#include <linux/debugfs.h>
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#include <linux/thermal.h>
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#include "rgxdevice.h"
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#if defined(CONFIG_ARCH_SUN50IW10)
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#define PPU_REG_BASE (0x07001000)
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#define GPU_SYS_REG_BASE (0x01880000)
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#define GPU_RSTN_REG (0x0)
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#define GPU_CLK_GATE_REG (0x04)
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#define GPU_POWEROFF_GATING_REG (0x08)
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#define GPU_PSWON_REG (0x0c)
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#define GPU_PSWOFF_REG (0x10)
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#define GPU_PD_STAT_REG (0x20)
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#define PPU_POWER_CTRL_REG (0x24)
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#define PPU_IRQ_MASK_REG (0x2C)
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#define GPU_PD_STAT_MASK (0x03)
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#define GPU_PD_STAT_ALLOFF (0x02)
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#define GPU_PD_STAT_3D_MODE (0x00)
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#define POWER_CTRL_MODE_MASK (0x03)
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#define POWER_CTRL_MODE_SW (0x01)
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#define POWER_CTRL_MODE_HW (0x02)
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#define POWER_IRQ_MASK_REQ (0x01)
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#define PPU_REG_SIZE (0x34)
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#define GPU_PD_STAT_MASK (0x03)
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#define GPU_PD_STAT_3D (0x00)
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#define GPU_PD_STAT_HOST (0x01)
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#define GPU_PD_STAT_ALLOFF (0x02)
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#define GPU_CLK_CTRL_REG (GPU_SYS_REG_BASE + 0x20)
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#define GPU_DFS_MAX (16)
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#define GPU_DFS_MIN (13)
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#endif /* defined(CONFIG_ARCH_SUN50IW10) */
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#define POWER_DEBUG 0
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struct sunxi_platform *sunxi_data;
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static struct dentry *sunxi_debugfs;
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static unsigned long dvfs_status;
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static wait_queue_head_t dvfs_wq;
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static inline int get_clks_wrap(struct device *dev)
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{
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#if defined(CONFIG_OF)
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sunxi_data->clks.pll = of_clk_get(dev->of_node, 0);
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if (IS_ERR_OR_NULL(sunxi_data->clks.pll)) {
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dev_err(dev, "failed to get GPU pll clock");
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return -1;
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}
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sunxi_data->clks.core = of_clk_get(dev->of_node, 1);
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if (IS_ERR_OR_NULL(sunxi_data->clks.core)) {
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dev_err(dev, "failed to get GPU core clock");
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return -1;
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}
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#endif /* defined(CONFIG_OF) */
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return 0;
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}
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static inline long ppu_mode_switch(int mode, bool irq_enable)
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{
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long val;
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/* Mask the power_request irq */
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val = readl(sunxi_data->ppu_reg + PPU_IRQ_MASK_REG);
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if (!irq_enable)
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val = val & (~POWER_IRQ_MASK_REQ);
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else
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val = val | POWER_IRQ_MASK_REQ;
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writel(val, sunxi_data->ppu_reg + PPU_IRQ_MASK_REG);
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/* switch power mode control */
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val = readl(sunxi_data->ppu_reg + PPU_POWER_CTRL_REG);
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val = (val & ~POWER_CTRL_MODE_MASK) + mode;
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writel(val, sunxi_data->ppu_reg + PPU_POWER_CTRL_REG);
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return readl(sunxi_data->ppu_reg + PPU_POWER_CTRL_REG);
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}
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static inline void ppu_power_mode(int mode)
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{
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unsigned int val;
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val = readl(sunxi_data->ppu_reg + GPU_PD_STAT_REG);
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val &= (~GPU_PD_STAT_MASK);
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val += mode;
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writel(val, sunxi_data->ppu_reg + GPU_PD_STAT_REG);
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}
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static inline void switch_interl_dfs(int val)
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{
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unsigned int val2;
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writel(val, sunxi_data->gpu_reg);
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val2 = readl(sunxi_data->gpu_reg);
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WARN_ON(val != val2);
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}
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PVRSRV_ERROR sunxiPrePowerState(IMG_HANDLE hSysData,
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PVRSRV_DEV_POWER_STATE eNewPowerState,
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PVRSRV_DEV_POWER_STATE eCurrentPowerState,
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IMG_BOOL bForced)
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{
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struct sunxi_platform *platform = (struct sunxi_platform *)hSysData;
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if (eNewPowerState == PVRSRV_DEV_POWER_STATE_ON && !platform->power_on) {
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pm_runtime_get_sync(platform->dev);
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if (!sunxi_data->soft_mode) {
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ppu_mode_switch(POWER_CTRL_MODE_HW, false);
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}
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spin_lock(&sunxi_data->lock);
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if (!sunxi_data->man_ctrl)
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switch_interl_dfs(sunxi_data->current_clk->gpu_dfs);
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else
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switch_interl_dfs(0x00000001);
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platform->power_on = 1;
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spin_unlock(&sunxi_data->lock);
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}
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return PVRSRV_OK;
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}
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PVRSRV_ERROR sunxiPostPowerState(IMG_HANDLE hSysData,
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PVRSRV_DEV_POWER_STATE eNewPowerState,
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PVRSRV_DEV_POWER_STATE eCurrentPowerState,
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IMG_BOOL bForced)
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{
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struct sunxi_platform *platform = (struct sunxi_platform *)hSysData;
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if (eNewPowerState == PVRSRV_DEV_POWER_STATE_OFF
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&& platform->power_on && platform->power_idle) {
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spin_lock(&sunxi_data->lock);
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platform->power_on = 0;
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spin_unlock(&sunxi_data->lock);
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if (!sunxi_data->soft_mode) {
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ppu_mode_switch(POWER_CTRL_MODE_SW, false);
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ppu_power_mode(GPU_PD_STAT_HOST);
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}
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pm_runtime_put_sync(platform->dev);
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}
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return PVRSRV_OK;
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}
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static void sunxi_set_freq_safe(IMG_UINT32 ui32Frequency, bool force)
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{
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int i = 0;
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struct sunxi_clks_table *find = NULL, *bak = NULL;
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long updata_core = 0;
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while (i < sunxi_data->table_num) {
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if (ui32Frequency == sunxi_data->clk_table[i].true_clk) {
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find = &sunxi_data->clk_table[i];
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break;
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}
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i++;
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}
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if (find == NULL) {
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dev_err(sunxi_data->dev, "%s:give us illlegal Frequency value =%u!",
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__func__, ui32Frequency);
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return;
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}
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if (find->true_clk == sunxi_data->current_clk->true_clk && !force)
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return;
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bak = sunxi_data->current_clk;
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updata_core = (long)(find->core_clk - sunxi_data->current_clk->core_clk);
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loop:
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sunxi_data->current_clk = find;
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spin_lock(&sunxi_data->lock);
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if (sunxi_data->power_on)
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switch_interl_dfs(find->gpu_dfs);
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spin_unlock(&sunxi_data->lock);
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if (updata_core != 0 || force) {
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if (clk_set_rate(sunxi_data->clks.core, find->core_clk) < 0) {
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dev_err(sunxi_data->dev, "%s:clk_set_rate Frequency value =%u err!",
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__func__, ui32Frequency);
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find = bak;
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updata_core = 0;
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force = 0;
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goto loop;
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}
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}
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}
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void sunxiSetFrequencyDVFS(IMG_UINT32 *ui32Frequency)
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{
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if (sunxi_data->man_ctrl || sunxi_data->scenectrl)
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goto dealed;
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if (!sunxi_data->dvfs)
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*ui32Frequency = sunxi_data->clk_table[0].true_clk;
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sunxi_set_freq_safe(*ui32Frequency, false);
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*ui32Frequency = sunxi_data->current_clk->true_clk;
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dealed:
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dvfs_status++;
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if (dvfs_status%2 == 0)
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wake_up(&dvfs_wq);
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}
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void sunxiSetVoltageDVFS(IMG_UINT32 ui32Volt)
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{
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if (!IS_ERR_OR_NULL(sunxi_data->regula)
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&& sunxi_data->independent_power
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&& !sunxi_data->man_ctrl
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&& !sunxi_data->scenectrl
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&& sunxi_data->dvfs) {
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if (regulator_set_voltage(sunxi_data->regula, ui32Volt, INT_MAX) != 0) {
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dev_err(sunxi_data->dev, "%s:Failed to set gpu power voltage=%d!",
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__func__, ui32Volt);
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}
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}
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dvfs_status++;
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if (dvfs_status%2 == 0)
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wake_up(&dvfs_wq);
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}
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static int sunxi_decide_pll(struct sunxi_platform *sunxi)
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{
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long pll_rate = 500000000, core_rate = 500000000;
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#if defined(CONFIG_PM_OPP) && defined(CONFIG_OF)
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const struct property *prop;
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const __be32 *val;
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int i = 0, j = 0, nr = 0;
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unsigned long step = 0;
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unsigned long core_clk[4];
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u32 val2;
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int err;
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sunxi->pll_clk_rate = 500000000;
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err = of_property_read_u32(sunxi->dev->of_node, "pll_rate", &val2);
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if (!err)
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sunxi->pll_clk_rate = val2 * 1000;
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while (i < 4) {
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core_clk[i] = sunxi->pll_clk_rate / (i + 1);
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core_clk[i] /= 1000;
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core_clk[i] *= 1000;
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i++;
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}
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prop = of_find_property(sunxi->dev->of_node, "operating-points", NULL);
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if (!prop)
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return -ENODEV;
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if (!prop->value)
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return -ENODATA;
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nr = prop->length / sizeof(u32);
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if (nr % 2) {
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dev_err(sunxi->dev, "%s: Invalid OPP table\n", __func__);
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return -EINVAL;
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}
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sunxi->table_num = nr/2;
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if (nr < 2) {
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sunxi->table_num = 1;
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}
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sunxi->clk_table = (struct sunxi_clks_table *)kzalloc(sizeof(struct sunxi_clks_table) * sunxi->table_num, GFP_KERNEL);
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if (!sunxi->clk_table) {
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dev_err(sunxi->dev, "failed to get kzalloc sunxi_clks_table\n");
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return -1;
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}
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sunxi->clk_table[0].core_clk = sunxi->pll_clk_rate;
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sunxi->clk_table[0].true_clk = sunxi->pll_clk_rate;
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sunxi->clk_table[0].gpu_dfs = 0x08;
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i = 0;
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j = 0;
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val = prop->value;
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while (nr) {
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unsigned long freq = be32_to_cpup(val++) * 1000;
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sunxi->clk_table[i].volt = be32_to_cpup(val++);
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sunxi->clk_table[i].true_clk = freq;
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while (freq < (core_clk[j] * GPU_DFS_MIN)/GPU_DFS_MAX && j < 4)
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j++;
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if (j >= 4) {
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dev_err(sunxi->dev, "%s: give us an OPP table\n", __func__);
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}
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step = core_clk[j]/16;
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sunxi->clk_table[i].gpu_dfs = 1<<(GPU_DFS_MAX-freq/step);
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sunxi->clk_table[i].core_clk = core_clk[j];
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dev_info(sunxi->dev, "set gpu core rate:%lu freq:%lu-%luuV dfs:0x%08x\n",
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core_clk[j], freq, sunxi->clk_table[i].volt, sunxi->clk_table[i].gpu_dfs);
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if (freq % step)
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dev_err(sunxi->dev, "%s: give us an error freq:%lu\n", __func__, freq);
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nr -= 2;
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i++;
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}
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pll_rate = sunxi->pll_clk_rate;
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core_rate = sunxi->clk_table[0].core_clk;
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sunxi->current_clk = &sunxi->clk_table[0];
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#endif /* defined(CONFIG_OF) */
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clk_set_rate(sunxi->clks.pll, pll_rate);
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clk_set_rate(sunxi->clks.core, core_rate);
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return 0;
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}
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static int parse_dts(struct device *dev, struct sunxi_platform *sunxi_data)
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{
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#ifdef CONFIG_OF
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u32 val;
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int err;
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err = of_property_read_u32(dev->of_node, "gpu_idle", &val);
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if (!err)
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sunxi_data->power_idle = val ? true : false;
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err = of_property_read_u32(dev->of_node, "independent_power", &val);
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if (!err)
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sunxi_data->independent_power = val ? true : false;
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err = of_property_read_u32(dev->of_node, "dvfs_status", &val);
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if (!err)
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sunxi_data->dvfs = val ? true : false;
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#endif /* CONFIG_OF */
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return 0;
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}
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static ssize_t scene_ctrl_cmd_show(struct device *dev,
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struct device_attribute *attr,
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char *buf)
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{
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return sprintf(buf, "%d\n", sunxi_data->scenectrl);
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}
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static ssize_t scene_ctrl_cmd_store(struct device *dev,
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struct device_attribute *attr,
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const char *buf, size_t count)
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{
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int err;
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unsigned long val;
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unsigned long volt;
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bool first_vol;
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enum scene_ctrl_cmd cmd;
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#if defined(CONFIG_PM_OPP)
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struct dev_pm_opp *opp;
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#endif
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err = kstrtoul(buf, 10, &val);
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if (err) {
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dev_err(dev, "scene_ctrl_cmd_store gets a invalid parameter!\n");
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return count;
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}
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cmd = (enum scene_ctrl_cmd)val;
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switch (cmd) {
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case SCENE_CTRL_NORMAL_MODE:
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sunxi_data->scenectrl = 0;
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break;
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case SCENE_CTRL_PERFORMANCE_MODE:
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if (sunxi_data->man_ctrl) {
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dev_err(dev, "in man mode so not apply!\n");
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return count;
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}
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sunxi_data->scenectrl = 1;
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val = ULONG_MAX;
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#if defined(CONFIG_PM_OPP)
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rcu_read_lock();
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opp = dev_pm_opp_find_freq_floor(dev, &val);
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if (!IS_ERR_OR_NULL(opp)) {
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volt = dev_pm_opp_get_voltage(opp);
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} else {
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val = sunxi_data->clk_table[0].true_clk;
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volt = sunxi_data->clk_table[0].volt;
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}
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rcu_read_unlock();
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#endif
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if (dvfs_status%2)
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wait_event_timeout(dvfs_wq,
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(dvfs_status%2 == 0), msecs_to_jiffies(100));
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first_vol = (sunxi_data->current_clk->true_clk < val);
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if (first_vol && sunxi_data->independent_power) {
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regulator_set_voltage(sunxi_data->regula, volt, INT_MAX);
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}
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sunxi_set_freq_safe(val, false);
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if (!first_vol && sunxi_data->independent_power) {
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regulator_set_voltage(sunxi_data->regula, volt, INT_MAX);
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}
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break;
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default:
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dev_err(dev, "invalid scene control command %d!\n", cmd);
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return count;
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}
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return count;
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}
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static DEVICE_ATTR(command, 0660,
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scene_ctrl_cmd_show, scene_ctrl_cmd_store);
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static struct attribute *scene_ctrl_attributes[] = {
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&dev_attr_command.attr,
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NULL
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};
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static struct attribute_group scene_ctrl_attribute_group = {
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.name = "scenectrl",
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.attrs = scene_ctrl_attributes
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};
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#ifdef CONFIG_DEBUG_FS
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static ssize_t write_write(struct file *filp, const char __user *buf,
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size_t count, loff_t *offp)
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{
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int i, err;
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unsigned long val, val2;
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bool semicolon = false;
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char buffer[50], data[32];
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int head_size = 0, data_size = 0;
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if (count >= sizeof(buffer))
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goto err_out;
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if (copy_from_user(buffer, buf, count))
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return -EFAULT;
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/* The command format is '<head>:<data>' or '<head>:<data>;' */
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for (i = 0; i < count; i++) {
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if (*(buffer+i) == ':')
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head_size = i;
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if (*(buffer+i) == ';' && head_size) {
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data_size = count - head_size - 3;
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semicolon = true;
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break;
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}
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}
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if (!head_size)
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goto err_out;
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if (!semicolon)
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data_size = count - head_size - 2;
|
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if (data_size > 32)
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goto err_out;
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memcpy(data, buffer + head_size + 1, data_size);
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data[data_size] = '\0';
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err = kstrtoul(data, 10, &val);
|
if (err)
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goto err_out;
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|
if (!strncmp("frequency", buffer, head_size)) {
|
if (!sunxi_data->man_ctrl) {
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printk("you must first set man mode\n");
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goto err_out;
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}
|
val *= 1000000;
|
val2 = val;
|
while (val <= 200000000)
|
val *= 2;
|
PVRSRVDevicePreClockSpeedChange(sunxi_data->config->psDevNode, true, NULL);
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clk_set_rate(sunxi_data->clks.pll, val);
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clk_set_rate(sunxi_data->clks.core, val2);
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spin_lock(&sunxi_data->lock);
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if (sunxi_data->power_on)
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switch_interl_dfs(0x00000001);
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spin_unlock(&sunxi_data->lock);
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PVRSRVDevicePostClockSpeedChange(sunxi_data->config->psDevNode, true, NULL);
|
|
} else if (!strncmp("voltage", buffer, head_size)) {
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if (!sunxi_data->man_ctrl) {
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printk("you must first set man mode\n");
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goto err_out;
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}
|
val *= 1000;
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if (sunxi_data->regula) {
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regulator_set_voltage(sunxi_data->regula, val, val);
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printk("set gpu regulator to %lu uV\n", val);
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}
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} else if (!strncmp("idle", buffer, head_size)) {
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sunxi_data->power_idle = !!val;
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} else if (!strncmp("dvfs", buffer, head_size)) {
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sunxi_data->dvfs = !!val;
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} else if (!strncmp("man", buffer, head_size)) {
|
sunxi_data->man_ctrl = !!val;
|
if (sunxi_data->man_ctrl) {
|
wait_event_timeout(dvfs_wq,
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(dvfs_status%2 == 0), msecs_to_jiffies(100));
|
} else {
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PVRSRVDevicePreClockSpeedChange(sunxi_data->config->psDevNode, true, NULL);
|
if (sunxi_data->regula) {
|
regulator_set_voltage(sunxi_data->regula,
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sunxi_data->current_clk->volt, sunxi_data->current_clk->volt);
|
printk("set gpu regulator to %lu uV\n", sunxi_data->current_clk->volt);
|
}
|
clk_set_rate(sunxi_data->clks.pll, sunxi_data->pll_clk_rate);
|
sunxi_set_freq_safe(sunxi_data->current_clk->true_clk, true);
|
PVRSRVDevicePostClockSpeedChange(sunxi_data->config->psDevNode, true, NULL);
|
}
|
} else {
|
goto err_out;
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}
|
|
return count;
|
|
err_out:
|
dev_err(sunxi_data->dev, "sunxi gpu invalid parameter:%s!\n", buffer);
|
return -EINVAL;
|
}
|
|
static const struct file_operations write_fops = {
|
.owner = THIS_MODULE,
|
.write = write_write,
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};
|
|
static int dump_debugfs_show(struct seq_file *s, void *data)
|
{
|
|
#ifdef CONFIG_REGULATOR
|
if (!IS_ERR_OR_NULL(sunxi_data->regula)) {
|
int vol = regulator_get_voltage(sunxi_data->regula);
|
seq_printf(s, "voltage:%dmV;\n", vol);
|
}
|
#endif /* CONFIG_REGULATOR */
|
seq_printf(s, "man:%s;\n", sunxi_data->man_ctrl ? "on" : "off");
|
seq_printf(s, "idle:%s;\n", sunxi_data->power_idle ? "on" : "off");
|
seq_printf(s, "scenectrl:%s;\n",
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sunxi_data->scenectrl ? "on" : "off");
|
seq_printf(s, "dvfs:%s;\n",
|
sunxi_data->dvfs ? "on" : "off");
|
seq_printf(s, "independent_power:%s;\n",
|
sunxi_data->independent_power ? "Yes" : "No");
|
seq_printf(s, "Frequency:%luMHz;\n", sunxi_data->current_clk->true_clk/1000/1000);
|
|
seq_puts(s, "\n");
|
|
return 0;
|
}
|
|
static int dump_debugfs_open(struct inode *inode, struct file *file)
|
{
|
return single_open(file, dump_debugfs_show, inode->i_private);
|
}
|
|
static const struct file_operations dump_fops = {
|
.owner = THIS_MODULE,
|
.open = dump_debugfs_open,
|
.read = seq_read,
|
.llseek = seq_lseek,
|
.release = single_release,
|
};
|
|
static int sunxi_create_debugfs(void)
|
{
|
struct dentry *node;
|
|
sunxi_debugfs = debugfs_create_dir("sunxi_gpu", NULL);
|
if (IS_ERR_OR_NULL(sunxi_debugfs))
|
return -ENOMEM;
|
|
node = debugfs_create_file("write", 0644,
|
sunxi_debugfs, NULL, &write_fops);
|
if (IS_ERR_OR_NULL(node))
|
return -ENOMEM;
|
|
node = debugfs_create_file("dump", 0644,
|
sunxi_debugfs, NULL, &dump_fops);
|
if (IS_ERR_OR_NULL(node))
|
return -ENOMEM;
|
|
return 0;
|
}
|
#endif /* CONFIG_DEBUG_FS */
|
|
int sunxi_platform_init(struct device *dev)
|
{
|
#if defined(CONFIG_OF)
|
struct resource *reg_res;
|
struct platform_device *pdev = to_platform_device(dev);
|
#endif /* defined(CONFIG_OF) */
|
unsigned int val, volt_val = 0;
|
|
sunxi_data = (struct sunxi_platform *)kzalloc(sizeof(struct sunxi_platform), GFP_KERNEL);
|
if (!sunxi_data) {
|
dev_err(dev, "failed to get kzalloc sunxi_platform");
|
return -1;
|
}
|
|
dev->platform_data = sunxi_data;
|
|
#if defined(CONFIG_OF)
|
pdev = to_platform_device(dev);
|
|
reg_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
if (reg_res == NULL) {
|
dev_err(dev, "failed to get register data from device tree");
|
return -1;
|
}
|
sunxi_data->reg_base = reg_res->start;
|
sunxi_data->reg_size = reg_res->end - reg_res->start + 1;
|
sunxi_data->dev = dev;
|
|
sunxi_data->irq_num = platform_get_irq_byname(pdev, "IRQGPU");
|
if (sunxi_data->irq_num < 0) {
|
dev_err(dev, "failed to get irq number from device tree");
|
return -1;
|
}
|
#endif /* defined(CONFIG_OF) */
|
sunxi_data->regula = regulator_get_optional(dev, "gpu");
|
if (!IS_ERR_OR_NULL(sunxi_data->regula))
|
volt_val = regulator_get_voltage(sunxi_data->regula);
|
|
if (get_clks_wrap(dev))
|
return -1;
|
|
sunxi_data->power_idle = 1;
|
sunxi_data->dvfs = 1;
|
sunxi_data->independent_power = 0;
|
sunxi_data->soft_mode = 1;
|
|
parse_dts(dev, sunxi_data);
|
if (!sunxi_data->independent_power)
|
sunxi_data->dvfs = 0;
|
|
sunxi_decide_pll(sunxi_data);
|
spin_lock_init(&sunxi_data->lock);
|
pm_runtime_enable(dev);
|
|
sunxi_data->ppu_reg = ioremap(PPU_REG_BASE, PPU_REG_SIZE);
|
sunxi_data->gpu_reg = ioremap(GPU_CLK_CTRL_REG, 4);
|
clk_prepare_enable(sunxi_data->clks.pll);
|
clk_prepare_enable(sunxi_data->clks.core);
|
sunxi_data->power_on = 0;
|
|
val = readl(sunxi_data->ppu_reg + GPU_PD_STAT_REG);
|
WARN_ON((val & GPU_PD_STAT_MASK) != GPU_PD_STAT_3D_MODE);
|
if (!sunxi_data->soft_mode) {
|
val = ppu_mode_switch(POWER_CTRL_MODE_HW, false);
|
WARN_ON((val & POWER_CTRL_MODE_MASK) != POWER_CTRL_MODE_HW);
|
} else {
|
val = ppu_mode_switch(POWER_CTRL_MODE_SW, true);
|
WARN_ON((val & POWER_CTRL_MODE_MASK) != POWER_CTRL_MODE_SW);
|
}
|
sunxi_create_debugfs();
|
if (sysfs_create_group(&dev->kobj, &scene_ctrl_attribute_group)) {
|
dev_err(dev, "sunxi sysfs group creation failed!\n");
|
}
|
#if POWER_DEBUG
|
sunxi_data->power_idle = 0;
|
regulator_set_voltage(sunxi_data->regula, 900000, 900000);
|
#endif
|
init_waitqueue_head(&dvfs_wq);
|
|
dev_info(dev, "idle:%d dvfs:%d power:%d %s mode:%d volt:%u core:%lu\n",
|
sunxi_data->power_idle, sunxi_data->dvfs, sunxi_data->independent_power,
|
IS_ERR_OR_NULL(sunxi_data->regula)?"No":"Yes", sunxi_data->soft_mode,
|
volt_val, clk_get_rate(sunxi_data->clks.core));
|
|
return 0;
|
}
|
|
void sunxi_platform_term(void)
|
{
|
pm_runtime_disable(sunxi_data->dev);
|
kfree(sunxi_data);
|
|
sunxi_data = NULL;
|
}
|
