// Copyright 2016, VIXL authors
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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// * Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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// * Redistributions in binary form must reproduce the above copyright notice,
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// this list of conditions and the following disclaimer in the documentation
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// and/or other materials provided with the distribution.
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// * Neither the name of ARM Limited nor the names of its contributors may be
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// used to endorse or promote products derived from this software without
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// specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND
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// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
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// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#include <stdlib.h>
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#include "test-runner.h"
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#ifdef VIXL_INCLUDE_TARGET_AARCH32
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#include "aarch32/macro-assembler-aarch32.h"
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#endif
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#ifdef VIXL_INCLUDE_TARGET_AARCH64
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#include "aarch64/macro-assembler-aarch64.h"
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#endif
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#define STRINGIFY(x) #x
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#define TEST_AARCH32(Name) \
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namespace aarch32 { \
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void Test_##Name##_AArch32_Impl(); \
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} \
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void Test_##Name##_AArch32() { aarch32::Test_##Name##_AArch32_Impl(); } \
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Test test_##Name##_AArch32(STRINGIFY(AARCH32_SCRATCH_##Name), \
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&Test_##Name##_AArch32); \
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void aarch32::Test_##Name##_AArch32_Impl()
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#define TEST_AARCH64(Name) \
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namespace aarch64 { \
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void Test_##Name##_AArch64_Impl(); \
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} \
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void Test_##Name##_AArch64() { aarch64::Test_##Name##_AArch64_Impl(); } \
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Test test_##Name##_AArch64(STRINGIFY(AARCH64_SCRATCH_##Name), \
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&Test_##Name##_AArch64); \
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void aarch64::Test_##Name##_AArch64_Impl()
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#define SETUP() MacroAssembler masm
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#define __ masm.
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namespace vixl {
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// UseScratchRegisterScopes must be able to nest perfectly. That is, they may
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// nest, but nested scopes must not outlive less-nested scopes.
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template <typename MacroAssembler, typename UseScratchRegisterScope>
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class PerfectNestingTestHelper {
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public:
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explicit PerfectNestingTestHelper(MacroAssembler* masm) : masm_(masm) {
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uint16_t seed[3] = {4, 5, 6};
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seed48(seed);
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}
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void Run() {
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UseScratchRegisterScope* top_scope =
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masm_->GetCurrentScratchRegisterScope();
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int descendents = 0;
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while (descendents < kMinimumDescendentScopeCount) descendents += Run(0);
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VIXL_CHECK(masm_->GetCurrentScratchRegisterScope() == top_scope);
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}
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private:
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int Run(int depth) {
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// As the depth increases, the probability of recursion decreases.
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// At depth = kDepthLimit, we never recurse.
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int max_children = static_cast<int>(std::abs(mrand48()) % kDepthLimit);
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int children = std::max(0, max_children - depth);
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int descendents = children;
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while (children-- > 0) {
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UseScratchRegisterScope scope(masm_);
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VIXL_CHECK(masm_->GetCurrentScratchRegisterScope() == &scope);
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descendents += Run(depth + 1);
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VIXL_CHECK(masm_->GetCurrentScratchRegisterScope() == &scope);
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}
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return descendents;
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}
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MacroAssembler* masm_;
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static const int kDepthLimit = 12;
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static const int kMinimumDescendentScopeCount = 10000;
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};
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#ifdef VIXL_INCLUDE_TARGET_AARCH32
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TEST_AARCH32(perfect_nesting) {
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SETUP();
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PerfectNestingTestHelper<MacroAssembler, UseScratchRegisterScope>(&masm)
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.Run();
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}
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#endif // VIXL_INCLUDE_TARGET_AARCH32
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#ifdef VIXL_INCLUDE_TARGET_AARCH64
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TEST_AARCH64(perfect_nesting) {
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SETUP();
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PerfectNestingTestHelper<MacroAssembler, UseScratchRegisterScope>(&masm)
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.Run();
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}
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#endif // VIXL_INCLUDE_TARGET_AARCH64
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#ifdef VIXL_INCLUDE_TARGET_AARCH32
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TEST_AARCH32(v_registers) {
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SETUP();
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{
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UseScratchRegisterScope temps(&masm);
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temps.Include(VRegisterList(q0, q1, q2, q3));
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// This test assumes that low-numbered registers are allocated first. The
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// implementation is allowed to use a different strategy; if it does, the
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// test will need to be updated.
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// TODO: Write more flexible (and thorough) tests.
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VIXL_CHECK(q0.Is(temps.AcquireQ()));
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VIXL_CHECK(!temps.IsAvailable(q0));
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VIXL_CHECK(!temps.IsAvailable(d0));
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VIXL_CHECK(!temps.IsAvailable(d1));
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VIXL_CHECK(!temps.IsAvailable(s0));
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VIXL_CHECK(!temps.IsAvailable(s1));
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VIXL_CHECK(!temps.IsAvailable(s2));
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VIXL_CHECK(!temps.IsAvailable(s3));
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VIXL_CHECK(d2.Is(temps.AcquireV(64)));
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VIXL_CHECK(!temps.IsAvailable(q1));
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VIXL_CHECK(!temps.IsAvailable(d2));
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VIXL_CHECK(temps.IsAvailable(d3));
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VIXL_CHECK(!temps.IsAvailable(s4));
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VIXL_CHECK(!temps.IsAvailable(s5));
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VIXL_CHECK(temps.IsAvailable(s6));
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VIXL_CHECK(temps.IsAvailable(s7));
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VIXL_CHECK(s6.Is(temps.AcquireS()));
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VIXL_CHECK(!temps.IsAvailable(d3));
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VIXL_CHECK(!temps.IsAvailable(s6));
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VIXL_CHECK(temps.IsAvailable(s7));
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VIXL_CHECK(q2.Is(temps.AcquireV(128)));
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VIXL_CHECK(!temps.IsAvailable(q2));
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VIXL_CHECK(!temps.IsAvailable(d4));
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VIXL_CHECK(!temps.IsAvailable(d5));
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VIXL_CHECK(!temps.IsAvailable(s8));
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VIXL_CHECK(!temps.IsAvailable(s9));
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VIXL_CHECK(!temps.IsAvailable(s10));
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VIXL_CHECK(!temps.IsAvailable(s11));
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VIXL_CHECK(temps.IsAvailable(s7));
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VIXL_CHECK(d6.Is(temps.AcquireD()));
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VIXL_CHECK(!temps.IsAvailable(q3));
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VIXL_CHECK(!temps.IsAvailable(d6));
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VIXL_CHECK(temps.IsAvailable(d7));
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VIXL_CHECK(!temps.IsAvailable(s12));
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VIXL_CHECK(!temps.IsAvailable(s13));
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VIXL_CHECK(temps.IsAvailable(s14));
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VIXL_CHECK(temps.IsAvailable(s15));
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VIXL_CHECK(temps.IsAvailable(s7));
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VIXL_CHECK(s7.Is(temps.AcquireS()));
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}
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}
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#endif // VIXL_INCLUDE_TARGET_AARCH32
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#ifdef VIXL_INCLUDE_TARGET_AARCH32
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TEST_AARCH32(include_exclude) {
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SETUP();
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{
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UseScratchRegisterScope temps(&masm);
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temps.Include(r0, r1, r2, r3);
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temps.Include(s0, s1, d1, q1);
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VIXL_CHECK(temps.IsAvailable(r0));
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VIXL_CHECK(temps.IsAvailable(r1));
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VIXL_CHECK(temps.IsAvailable(r2));
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VIXL_CHECK(temps.IsAvailable(r3));
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VIXL_CHECK(temps.IsAvailable(s0));
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VIXL_CHECK(temps.IsAvailable(s1));
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VIXL_CHECK(temps.IsAvailable(d1));
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VIXL_CHECK(temps.IsAvailable(s2));
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VIXL_CHECK(temps.IsAvailable(s3));
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VIXL_CHECK(temps.IsAvailable(q1));
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VIXL_CHECK(temps.IsAvailable(d2));
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VIXL_CHECK(temps.IsAvailable(d3));
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VIXL_CHECK(temps.IsAvailable(s4));
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VIXL_CHECK(temps.IsAvailable(s5));
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VIXL_CHECK(temps.IsAvailable(s6));
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VIXL_CHECK(temps.IsAvailable(s7));
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// Test local exclusion.
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{
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UseScratchRegisterScope local_temps(&masm);
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local_temps.Exclude(r1, r2);
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local_temps.Exclude(s1, q1);
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VIXL_CHECK(temps.IsAvailable(r0));
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VIXL_CHECK(!temps.IsAvailable(r1));
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VIXL_CHECK(!temps.IsAvailable(r2));
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VIXL_CHECK(temps.IsAvailable(r3));
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VIXL_CHECK(temps.IsAvailable(s0));
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VIXL_CHECK(!temps.IsAvailable(s1));
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VIXL_CHECK(temps.IsAvailable(d1));
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VIXL_CHECK(temps.IsAvailable(s2));
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VIXL_CHECK(temps.IsAvailable(s3));
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VIXL_CHECK(!temps.IsAvailable(q1));
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VIXL_CHECK(!temps.IsAvailable(d2));
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VIXL_CHECK(!temps.IsAvailable(d3));
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VIXL_CHECK(!temps.IsAvailable(s4));
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VIXL_CHECK(!temps.IsAvailable(s5));
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VIXL_CHECK(!temps.IsAvailable(s6));
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VIXL_CHECK(!temps.IsAvailable(s7));
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}
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// This time, exclude part of included registers, making sure the entire
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// register gets excluded.
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{
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UseScratchRegisterScope local_temps(&masm);
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local_temps.Exclude(s2, d3);
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VIXL_CHECK(temps.IsAvailable(r0));
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VIXL_CHECK(temps.IsAvailable(r1));
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VIXL_CHECK(temps.IsAvailable(r2));
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VIXL_CHECK(temps.IsAvailable(r3));
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VIXL_CHECK(temps.IsAvailable(s0));
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VIXL_CHECK(temps.IsAvailable(s1));
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// Excluding s2 should exclude d1 but not s3.
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VIXL_CHECK(!temps.IsAvailable(d1));
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VIXL_CHECK(!temps.IsAvailable(s2));
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VIXL_CHECK(temps.IsAvailable(s3));
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// Excluding d3 should exclude q1, s7 and s6 but not d2, s5, s4.
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VIXL_CHECK(!temps.IsAvailable(q1));
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VIXL_CHECK(temps.IsAvailable(d2));
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VIXL_CHECK(!temps.IsAvailable(d3));
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VIXL_CHECK(temps.IsAvailable(s4));
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VIXL_CHECK(temps.IsAvailable(s5));
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VIXL_CHECK(!temps.IsAvailable(s6));
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VIXL_CHECK(!temps.IsAvailable(s7));
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}
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// Make sure the initial state was restored.
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VIXL_CHECK(temps.IsAvailable(r0));
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VIXL_CHECK(temps.IsAvailable(r1));
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VIXL_CHECK(temps.IsAvailable(r2));
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VIXL_CHECK(temps.IsAvailable(r3));
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VIXL_CHECK(temps.IsAvailable(s0));
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VIXL_CHECK(temps.IsAvailable(s1));
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VIXL_CHECK(temps.IsAvailable(d1));
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VIXL_CHECK(temps.IsAvailable(s2));
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VIXL_CHECK(temps.IsAvailable(s3));
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VIXL_CHECK(temps.IsAvailable(q1));
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VIXL_CHECK(temps.IsAvailable(d2));
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VIXL_CHECK(temps.IsAvailable(d3));
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VIXL_CHECK(temps.IsAvailable(s4));
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VIXL_CHECK(temps.IsAvailable(s5));
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VIXL_CHECK(temps.IsAvailable(s6));
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VIXL_CHECK(temps.IsAvailable(s7));
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}
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}
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#endif // VIXL_INCLUDE_TARGET_AARCH32
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} // namespace vixl
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