/*
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* Copyright 2016 Freescale Semiconductor, Inc.
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* Copyright 2017 NXP
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __DT_BINDINGS_CLOCK_IMX8MQ_H
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#define __DT_BINDINGS_CLOCK_IMX8MQ_H
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#define IMX8MQ_CLK_DUMMY 0
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#define IMX8MQ_CLK_32K 1
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#define IMX8MQ_CLK_25M 2
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#define IMX8MQ_CLK_27M 3
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#define IMX8MQ_CLK_EXT1 4
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#define IMX8MQ_CLK_EXT2 5
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#define IMX8MQ_CLK_EXT3 6
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#define IMX8MQ_CLK_EXT4 7
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/* ANAMIX PLL clocks */
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/* FRAC PLLs */
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/* ARM PLL */
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#define IMX8MQ_ARM_PLL_REF_SEL 8
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#define IMX8MQ_ARM_PLL_REF_DIV 9
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#define IMX8MQ_ARM_PLL 10
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#define IMX8MQ_ARM_PLL_BYPASS 11
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#define IMX8MQ_ARM_PLL_OUT 12
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/* GPU PLL */
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#define IMX8MQ_GPU_PLL_REF_SEL 13
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#define IMX8MQ_GPU_PLL_REF_DIV 14
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#define IMX8MQ_GPU_PLL 15
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#define IMX8MQ_GPU_PLL_BYPASS 16
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#define IMX8MQ_GPU_PLL_OUT 17
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/* VPU PLL */
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#define IMX8MQ_VPU_PLL_REF_SEL 18
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#define IMX8MQ_VPU_PLL_REF_DIV 19
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#define IMX8MQ_VPU_PLL 20
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#define IMX8MQ_VPU_PLL_BYPASS 21
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#define IMX8MQ_VPU_PLL_OUT 22
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/* AUDIO PLL1 */
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#define IMX8MQ_AUDIO_PLL1_REF_SEL 23
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#define IMX8MQ_AUDIO_PLL1_REF_DIV 24
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#define IMX8MQ_AUDIO_PLL1 25
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#define IMX8MQ_AUDIO_PLL1_BYPASS 26
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#define IMX8MQ_AUDIO_PLL1_OUT 27
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/* AUDIO PLL2 */
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#define IMX8MQ_AUDIO_PLL2_REF_SEL 28
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#define IMX8MQ_AUDIO_PLL2_REF_DIV 29
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#define IMX8MQ_AUDIO_PLL2 30
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#define IMX8MQ_AUDIO_PLL2_BYPASS 31
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#define IMX8MQ_AUDIO_PLL2_OUT 32
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/* VIDEO PLL1 */
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#define IMX8MQ_VIDEO_PLL1_REF_SEL 33
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#define IMX8MQ_VIDEO_PLL1_REF_DIV 34
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#define IMX8MQ_VIDEO_PLL1 35
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#define IMX8MQ_VIDEO_PLL1_BYPASS 36
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#define IMX8MQ_VIDEO_PLL1_OUT 37
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/* SYS1 PLL */
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#define IMX8MQ_SYS1_PLL1_REF_SEL 38
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#define IMX8MQ_SYS1_PLL1_REF_DIV 39
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#define IMX8MQ_SYS1_PLL1 40
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#define IMX8MQ_SYS1_PLL1_OUT 41
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#define IMX8MQ_SYS1_PLL1_OUT_DIV 42
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#define IMX8MQ_SYS1_PLL2 43
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#define IMX8MQ_SYS1_PLL2_DIV 44
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#define IMX8MQ_SYS1_PLL2_OUT 45
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/* SYS2 PLL */
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#define IMX8MQ_SYS2_PLL1_REF_SEL 46
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#define IMX8MQ_SYS2_PLL1_REF_DIV 47
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#define IMX8MQ_SYS2_PLL1 48
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#define IMX8MQ_SYS2_PLL1_OUT 49
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#define IMX8MQ_SYS2_PLL1_OUT_DIV 50
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#define IMX8MQ_SYS2_PLL2 51
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#define IMX8MQ_SYS2_PLL2_DIV 52
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#define IMX8MQ_SYS2_PLL2_OUT 53
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/* SYS3 PLL */
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#define IMX8MQ_SYS3_PLL1_REF_SEL 54
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#define IMX8MQ_SYS3_PLL1_REF_DIV 55
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#define IMX8MQ_SYS3_PLL1 56
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#define IMX8MQ_SYS3_PLL1_OUT 57
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#define IMX8MQ_SYS3_PLL1_OUT_DIV 58
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#define IMX8MQ_SYS3_PLL2 59
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#define IMX8MQ_SYS3_PLL2_DIV 60
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#define IMX8MQ_SYS3_PLL2_OUT 61
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/* DRAM PLL */
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#define IMX8MQ_DRAM_PLL1_REF_SEL 62
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#define IMX8MQ_DRAM_PLL1_REF_DIV 63
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#define IMX8MQ_DRAM_PLL1 64
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#define IMX8MQ_DRAM_PLL1_OUT 65
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#define IMX8MQ_DRAM_PLL1_OUT_DIV 66
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#define IMX8MQ_DRAM_PLL2 67
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#define IMX8MQ_DRAM_PLL2_DIV 68
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#define IMX8MQ_DRAM_PLL2_OUT 69
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/* SYS PLL DIV */
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#define IMX8MQ_SYS1_PLL_40M 70
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#define IMX8MQ_SYS1_PLL_80M 71
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#define IMX8MQ_SYS1_PLL_100M 72
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#define IMX8MQ_SYS1_PLL_133M 73
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#define IMX8MQ_SYS1_PLL_160M 74
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#define IMX8MQ_SYS1_PLL_200M 75
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#define IMX8MQ_SYS1_PLL_266M 76
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#define IMX8MQ_SYS1_PLL_400M 77
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#define IMX8MQ_SYS1_PLL_800M 78
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#define IMX8MQ_SYS2_PLL_50M 79
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#define IMX8MQ_SYS2_PLL_100M 80
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#define IMX8MQ_SYS2_PLL_125M 81
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#define IMX8MQ_SYS2_PLL_166M 82
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#define IMX8MQ_SYS2_PLL_200M 83
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#define IMX8MQ_SYS2_PLL_250M 84
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#define IMX8MQ_SYS2_PLL_333M 85
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#define IMX8MQ_SYS2_PLL_500M 86
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#define IMX8MQ_SYS2_PLL_1000M 87
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/* CCM ROOT clocks */
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/* A53 */
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#define IMX8MQ_CLK_A53_SRC 88
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#define IMX8MQ_CLK_A53_CG 89
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#define IMX8MQ_CLK_A53_DIV 90
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/* M4 */
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#define IMX8MQ_CLK_M4_SRC 91
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#define IMX8MQ_CLK_M4_CG 92
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#define IMX8MQ_CLK_M4_DIV 93
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/* VPU */
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#define IMX8MQ_CLK_VPU_SRC 94
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#define IMX8MQ_CLK_VPU_CG 95
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#define IMX8MQ_CLK_VPU_DIV 96
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/* GPU CORE */
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#define IMX8MQ_CLK_GPU_CORE_SRC 97
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#define IMX8MQ_CLK_GPU_CORE_CG 98
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#define IMX8MQ_CLK_GPU_CORE_DIV 99
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/* GPU SHADER */
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#define IMX8MQ_CLK_GPU_SHADER_SRC 100
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#define IMX8MQ_CLK_GPU_SHADER_CG 101
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#define IMX8MQ_CLK_GPU_SHADER_DIV 102
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/* BUS TYPE */
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/* MAIN AXI */
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#define IMX8MQ_CLK_MAIN_AXI_SRC 103
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#define IMX8MQ_CLK_MAIN_AXI_CG 104
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#define IMX8MQ_CLK_MAIN_AXI_PRE_DIV 105
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#define IMX8MQ_CLK_MAIN_AXI_DIV 106
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/* ENET AXI */
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#define IMX8MQ_CLK_ENET_AXI_SRC 107
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#define IMX8MQ_CLK_ENET_AXI_CG 108
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#define IMX8MQ_CLK_ENET_AXI_PRE_DIV 109
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#define IMX8MQ_CLK_ENET_AXI_DIV 110
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/* NAND_USDHC_BUS */
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#define IMX8MQ_CLK_NAND_USDHC_BUS_SRC 111
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#define IMX8MQ_CLK_NAND_USDHC_BUS_CG 112
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#define IMX8MQ_CLK_NAND_USDHC_BUS_PRE_DIV 113
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#define IMX8MQ_CLK_NAND_USDHC_BUS_DIV 114
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/* VPU BUS */
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#define IMX8MQ_CLK_VPU_BUS_SRC 115
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#define IMX8MQ_CLK_VPU_BUS_CG 116
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#define IMX8MQ_CLK_VPU_BUS_PRE_DIV 117
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#define IMX8MQ_CLK_VPU_BUS_DIV 118
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/* DISP_AXI */
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#define IMX8MQ_CLK_DISP_AXI_SRC 119
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#define IMX8MQ_CLK_DISP_AXI_CG 120
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#define IMX8MQ_CLK_DISP_AXI_PRE_DIV 121
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#define IMX8MQ_CLK_DISP_AXI_DIV 122
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/* DISP APB */
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#define IMX8MQ_CLK_DISP_APB_SRC 123
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#define IMX8MQ_CLK_DISP_APB_CG 124
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#define IMX8MQ_CLK_DISP_APB_PRE_DIV 125
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#define IMX8MQ_CLK_DISP_APB_DIV 126
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/* DISP RTRM */
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#define IMX8MQ_CLK_DISP_RTRM_SRC 127
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#define IMX8MQ_CLK_DISP_RTRM_CG 128
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#define IMX8MQ_CLK_DISP_RTRM_PRE_DIV 129
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#define IMX8MQ_CLK_DISP_RTRM_DIV 130
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/* USB_BUS */
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#define IMX8MQ_CLK_USB_BUS_SRC 131
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#define IMX8MQ_CLK_USB_BUS_CG 132
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#define IMX8MQ_CLK_USB_BUS_PRE_DIV 133
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#define IMX8MQ_CLK_USB_BUS_DIV 134
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/* GPU_AXI */
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#define IMX8MQ_CLK_GPU_AXI_SRC 135
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#define IMX8MQ_CLK_GPU_AXI_CG 136
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#define IMX8MQ_CLK_GPU_AXI_PRE_DIV 137
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#define IMX8MQ_CLK_GPU_AXI_DIV 138
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/* GPU_AHB */
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#define IMX8MQ_CLK_GPU_AHB_SRC 139
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#define IMX8MQ_CLK_GPU_AHB_CG 140
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#define IMX8MQ_CLK_GPU_AHB_PRE_DIV 141
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#define IMX8MQ_CLK_GPU_AHB_DIV 142
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/* NOC */
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#define IMX8MQ_CLK_NOC_SRC 143
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#define IMX8MQ_CLK_NOC_CG 144
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#define IMX8MQ_CLK_NOC_PRE_DIV 145
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#define IMX8MQ_CLK_NOC_DIV 146
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/* NOC_APB */
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#define IMX8MQ_CLK_NOC_APB_SRC 147
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#define IMX8MQ_CLK_NOC_APB_CG 148
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#define IMX8MQ_CLK_NOC_APB_PRE_DIV 149
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#define IMX8MQ_CLK_NOC_APB_DIV 150
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/* AHB */
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#define IMX8MQ_CLK_AHB_SRC 151
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#define IMX8MQ_CLK_AHB_CG 152
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#define IMX8MQ_CLK_AHB_PRE_DIV 153
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#define IMX8MQ_CLK_AHB_DIV 154
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/* AUDIO AHB */
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#define IMX8MQ_CLK_AUDIO_AHB_SRC 155
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#define IMX8MQ_CLK_AUDIO_AHB_CG 156
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#define IMX8MQ_CLK_AUDIO_AHB_PRE_DIV 157
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#define IMX8MQ_CLK_AUDIO_AHB_DIV 158
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/* DRAM_ALT */
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#define IMX8MQ_CLK_DRAM_ALT_SRC 159
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#define IMX8MQ_CLK_DRAM_ALT_CG 160
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#define IMX8MQ_CLK_DRAM_ALT_PRE_DIV 161
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#define IMX8MQ_CLK_DRAM_ALT_DIV 162
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/* DRAM APB */
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#define IMX8MQ_CLK_DRAM_APB_SRC 163
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#define IMX8MQ_CLK_DRAM_APB_CG 164
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#define IMX8MQ_CLK_DRAM_APB_PRE_DIV 165
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#define IMX8MQ_CLK_DRAM_APB_DIV 166
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/* VPU_G1 */
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#define IMX8MQ_CLK_VPU_G1_SRC 167
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#define IMX8MQ_CLK_VPU_G1_CG 168
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#define IMX8MQ_CLK_VPU_G1_PRE_DIV 169
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#define IMX8MQ_CLK_VPU_G1_DIV 170
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/* VPU_G2 */
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#define IMX8MQ_CLK_VPU_G2_SRC 171
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#define IMX8MQ_CLK_VPU_G2_CG 172
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#define IMX8MQ_CLK_VPU_G2_PRE_DIV 173
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#define IMX8MQ_CLK_VPU_G2_DIV 174
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/* DISP_DTRC */
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#define IMX8MQ_CLK_DISP_DTRC_SRC 175
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#define IMX8MQ_CLK_DISP_DTRC_CG 176
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#define IMX8MQ_CLK_DISP_DTRC_PRE_DIV 177
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#define IMX8MQ_CLK_DISP_DTRC_DIV 178
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/* DISP_DC8000 */
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#define IMX8MQ_CLK_DISP_DC8000_SRC 179
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#define IMX8MQ_CLK_DISP_DC8000_CG 180
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#define IMX8MQ_CLK_DISP_DC8000_PRE_DIV 181
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#define IMX8MQ_CLK_DISP_DC8000_DIV 182
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/* PCIE_CTRL */
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#define IMX8MQ_CLK_PCIE1_CTRL_SRC 183
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#define IMX8MQ_CLK_PCIE1_CTRL_CG 184
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#define IMX8MQ_CLK_PCIE1_CTRL_PRE_DIV 185
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#define IMX8MQ_CLK_PCIE1_CTRL_DIV 186
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/* PCIE_PHY */
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#define IMX8MQ_CLK_PCIE1_PHY_SRC 187
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#define IMX8MQ_CLK_PCIE1_PHY_CG 188
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#define IMX8MQ_CLK_PCIE1_PHY_PRE_DIV 189
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#define IMX8MQ_CLK_PCIE1_PHY_DIV 190
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/* PCIE_AUX */
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#define IMX8MQ_CLK_PCIE1_AUX_SRC 191
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#define IMX8MQ_CLK_PCIE1_AUX_CG 192
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#define IMX8MQ_CLK_PCIE1_AUX_PRE_DIV 193
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#define IMX8MQ_CLK_PCIE1_AUX_DIV 194
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/* DC_PIXEL */
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#define IMX8MQ_CLK_DC_PIXEL_SRC 195
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#define IMX8MQ_CLK_DC_PIXEL_CG 196
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#define IMX8MQ_CLK_DC_PIXEL_PRE_DIV 197
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#define IMX8MQ_CLK_DC_PIXEL_DIV 198
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/* LCDIF_PIXEL */
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#define IMX8MQ_CLK_LCDIF_PIXEL_SRC 199
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#define IMX8MQ_CLK_LCDIF_PIXEL_CG 200
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#define IMX8MQ_CLK_LCDIF_PIXEL_PRE_DIV 201
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#define IMX8MQ_CLK_LCDIF_PIXEL_DIV 202
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/* SAI1~6 */
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#define IMX8MQ_CLK_SAI1_SRC 203
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#define IMX8MQ_CLK_SAI1_CG 204
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#define IMX8MQ_CLK_SAI1_PRE_DIV 205
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#define IMX8MQ_CLK_SAI1_DIV 206
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#define IMX8MQ_CLK_SAI2_SRC 207
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#define IMX8MQ_CLK_SAI2_CG 208
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#define IMX8MQ_CLK_SAI2_PRE_DIV 209
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#define IMX8MQ_CLK_SAI2_DIV 210
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#define IMX8MQ_CLK_SAI3_SRC 211
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#define IMX8MQ_CLK_SAI3_CG 212
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#define IMX8MQ_CLK_SAI3_PRE_DIV 213
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#define IMX8MQ_CLK_SAI3_DIV 214
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#define IMX8MQ_CLK_SAI4_SRC 215
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#define IMX8MQ_CLK_SAI4_CG 216
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#define IMX8MQ_CLK_SAI4_PRE_DIV 217
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#define IMX8MQ_CLK_SAI4_DIV 218
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#define IMX8MQ_CLK_SAI5_SRC 219
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#define IMX8MQ_CLK_SAI5_CG 220
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#define IMX8MQ_CLK_SAI5_PRE_DIV 221
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#define IMX8MQ_CLK_SAI5_DIV 222
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#define IMX8MQ_CLK_SAI6_SRC 223
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#define IMX8MQ_CLK_SAI6_CG 224
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#define IMX8MQ_CLK_SAI6_PRE_DIV 225
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#define IMX8MQ_CLK_SAI6_DIV 226
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/* SPDIF1 */
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#define IMX8MQ_CLK_SPDIF1_SRC 227
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#define IMX8MQ_CLK_SPDIF1_CG 228
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#define IMX8MQ_CLK_SPDIF1_PRE_DIV 229
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#define IMX8MQ_CLK_SPDIF1_DIV 230
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/* SPDIF2 */
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#define IMX8MQ_CLK_SPDIF2_SRC 231
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#define IMX8MQ_CLK_SPDIF2_CG 232
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#define IMX8MQ_CLK_SPDIF2_PRE_DIV 233
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#define IMX8MQ_CLK_SPDIF2_DIV 234
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/* ENET_REF */
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#define IMX8MQ_CLK_ENET_REF_SRC 235
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#define IMX8MQ_CLK_ENET_REF_CG 236
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#define IMX8MQ_CLK_ENET_REF_PRE_DIV 237
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#define IMX8MQ_CLK_ENET_REF_DIV 238
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/* ENET_TIMER */
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#define IMX8MQ_CLK_ENET_TIMER_SRC 239
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#define IMX8MQ_CLK_ENET_TIMER_CG 240
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#define IMX8MQ_CLK_ENET_TIMER_PRE_DIV 241
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#define IMX8MQ_CLK_ENET_TIMER_DIV 242
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/* ENET_PHY */
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#define IMX8MQ_CLK_ENET_PHY_REF_SRC 243
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#define IMX8MQ_CLK_ENET_PHY_REF_CG 244
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#define IMX8MQ_CLK_ENET_PHY_REF_PRE_DIV 245
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#define IMX8MQ_CLK_ENET_PHY_REF_DIV 246
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/* NAND */
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#define IMX8MQ_CLK_NAND_SRC 247
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#define IMX8MQ_CLK_NAND_CG 248
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#define IMX8MQ_CLK_NAND_PRE_DIV 249
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#define IMX8MQ_CLK_NAND_DIV 250
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/* QSPI */
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#define IMX8MQ_CLK_QSPI_SRC 251
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#define IMX8MQ_CLK_QSPI_CG 252
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#define IMX8MQ_CLK_QSPI_PRE_DIV 253
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#define IMX8MQ_CLK_QSPI_DIV 254
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/* USDHC1 */
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#define IMX8MQ_CLK_USDHC1_SRC 255
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#define IMX8MQ_CLK_USDHC1_CG 256
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#define IMX8MQ_CLK_USDHC1_PRE_DIV 257
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#define IMX8MQ_CLK_USDHC1_DIV 258
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/* USDHC2 */
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#define IMX8MQ_CLK_USDHC2_SRC 259
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#define IMX8MQ_CLK_USDHC2_CG 260
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#define IMX8MQ_CLK_USDHC2_PRE_DIV 261
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#define IMX8MQ_CLK_USDHC2_DIV 262
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/* I2C1 */
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#define IMX8MQ_CLK_I2C1_SRC 263
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#define IMX8MQ_CLK_I2C1_CG 264
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#define IMX8MQ_CLK_I2C1_PRE_DIV 265
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#define IMX8MQ_CLK_I2C1_DIV 266
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/* I2C2 */
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#define IMX8MQ_CLK_I2C2_SRC 267
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#define IMX8MQ_CLK_I2C2_CG 268
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#define IMX8MQ_CLK_I2C2_PRE_DIV 269
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#define IMX8MQ_CLK_I2C2_DIV 270
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/* I2C3 */
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#define IMX8MQ_CLK_I2C3_SRC 271
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#define IMX8MQ_CLK_I2C3_CG 272
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#define IMX8MQ_CLK_I2C3_PRE_DIV 273
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#define IMX8MQ_CLK_I2C3_DIV 274
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/* I2C4 */
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#define IMX8MQ_CLK_I2C4_SRC 275
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#define IMX8MQ_CLK_I2C4_CG 276
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#define IMX8MQ_CLK_I2C4_PRE_DIV 277
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#define IMX8MQ_CLK_I2C4_DIV 278
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/* UART1 */
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#define IMX8MQ_CLK_UART1_SRC 279
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#define IMX8MQ_CLK_UART1_CG 280
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#define IMX8MQ_CLK_UART1_PRE_DIV 281
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#define IMX8MQ_CLK_UART1_DIV 282
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/* UART2 */
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#define IMX8MQ_CLK_UART2_SRC 283
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#define IMX8MQ_CLK_UART2_CG 284
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#define IMX8MQ_CLK_UART2_PRE_DIV 285
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#define IMX8MQ_CLK_UART2_DIV 286
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/* UART3 */
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#define IMX8MQ_CLK_UART3_SRC 287
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#define IMX8MQ_CLK_UART3_CG 288
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#define IMX8MQ_CLK_UART3_PRE_DIV 289
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#define IMX8MQ_CLK_UART3_DIV 290
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/* UART4 */
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#define IMX8MQ_CLK_UART4_SRC 291
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#define IMX8MQ_CLK_UART4_CG 292
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#define IMX8MQ_CLK_UART4_PRE_DIV 293
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#define IMX8MQ_CLK_UART4_DIV 294
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/* USB_CORE_REF */
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#define IMX8MQ_CLK_USB_CORE_REF_SRC 295
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#define IMX8MQ_CLK_USB_CORE_REF_CG 296
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#define IMX8MQ_CLK_USB_CORE_REF_PRE_DIV 297
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#define IMX8MQ_CLK_USB_CORE_REF_DIV 298
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/* USB_PHY_REF */
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#define IMX8MQ_CLK_USB_PHY_REF_SRC 299
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#define IMX8MQ_CLK_USB_PHY_REF_CG 300
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#define IMX8MQ_CLK_USB_PHY_REF_PRE_DIV 301
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#define IMX8MQ_CLK_USB_PHY_REF_DIV 302
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/* ECSPI1 */
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#define IMX8MQ_CLK_ECSPI1_SRC 303
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#define IMX8MQ_CLK_ECSPI1_CG 304
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#define IMX8MQ_CLK_ECSPI1_PRE_DIV 305
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#define IMX8MQ_CLK_ECSPI1_DIV 306
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/* ECSPI2 */
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#define IMX8MQ_CLK_ECSPI2_SRC 307
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#define IMX8MQ_CLK_ECSPI2_CG 308
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#define IMX8MQ_CLK_ECSPI2_PRE_DIV 309
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#define IMX8MQ_CLK_ECSPI2_DIV 310
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/* PWM1 */
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#define IMX8MQ_CLK_PWM1_SRC 311
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#define IMX8MQ_CLK_PWM1_CG 312
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#define IMX8MQ_CLK_PWM1_PRE_DIV 313
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#define IMX8MQ_CLK_PWM1_DIV 314
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/* PWM2 */
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#define IMX8MQ_CLK_PWM2_SRC 315
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#define IMX8MQ_CLK_PWM2_CG 316
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#define IMX8MQ_CLK_PWM2_PRE_DIV 317
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#define IMX8MQ_CLK_PWM2_DIV 318
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/* PWM3 */
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#define IMX8MQ_CLK_PWM3_SRC 319
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#define IMX8MQ_CLK_PWM3_CG 320
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#define IMX8MQ_CLK_PWM3_PRE_DIV 321
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#define IMX8MQ_CLK_PWM3_DIV 322
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/* PWM4 */
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#define IMX8MQ_CLK_PWM4_SRC 323
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#define IMX8MQ_CLK_PWM4_CG 324
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#define IMX8MQ_CLK_PWM4_PRE_DIV 325
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#define IMX8MQ_CLK_PWM4_DIV 326
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/* GPT1 */
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#define IMX8MQ_CLK_GPT1_SRC 327
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#define IMX8MQ_CLK_GPT1_CG 328
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#define IMX8MQ_CLK_GPT1_PRE_DIV 329
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#define IMX8MQ_CLK_GPT1_DIV 330
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/* WDOG */
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#define IMX8MQ_CLK_WDOG_SRC 331
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#define IMX8MQ_CLK_WDOG_CG 332
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#define IMX8MQ_CLK_WDOG_PRE_DIV 333
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#define IMX8MQ_CLK_WDOG_DIV 334
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/* WRCLK */
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#define IMX8MQ_CLK_WRCLK_SRC 335
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#define IMX8MQ_CLK_WRCLK_CG 336
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#define IMX8MQ_CLK_WRCLK_PRE_DIV 337
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#define IMX8MQ_CLK_WRCLK_DIV 338
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/* DSI_CORE */
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#define IMX8MQ_CLK_DSI_CORE_SRC 339
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#define IMX8MQ_CLK_DSI_CORE_CG 340
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#define IMX8MQ_CLK_DSI_CORE_PRE_DIV 341
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#define IMX8MQ_CLK_DSI_CORE_DIV 342
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/* DSI_PHY */
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#define IMX8MQ_CLK_DSI_PHY_REF_SRC 343
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#define IMX8MQ_CLK_DSI_PHY_REF_CG 344
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#define IMX8MQ_CLK_DSI_PHY_REF_PRE_DIV 345
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#define IMX8MQ_CLK_DSI_PHY_REF_DIV 346
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/* DSI_DBI */
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#define IMX8MQ_CLK_DSI_DBI_SRC 347
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#define IMX8MQ_CLK_DSI_DBI_CG 348
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#define IMX8MQ_CLK_DSI_DBI_PRE_DIV 349
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#define IMX8MQ_CLK_DSI_DBI_DIV 350
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/*DSI_ESC */
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#define IMX8MQ_CLK_DSI_ESC_SRC 351
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#define IMX8MQ_CLK_DSI_ESC_CG 352
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#define IMX8MQ_CLK_DSI_ESC_PRE_DIV 353
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#define IMX8MQ_CLK_DSI_ESC_DIV 354
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/* CSI1_CORE */
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#define IMX8MQ_CLK_CSI1_CORE_SRC 355
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#define IMX8MQ_CLK_CSI1_CORE_CG 356
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#define IMX8MQ_CLK_CSI1_CORE_PRE_DIV 357
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#define IMX8MQ_CLK_CSI1_CORE_DIV 358
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/* CSI1_PHY */
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#define IMX8MQ_CLK_CSI1_PHY_REF_SRC 359
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#define IMX8MQ_CLK_CSI1_PHY_REF_CG 360
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#define IMX8MQ_CLK_CSI1_PHY_REF_PRE_DIV 361
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#define IMX8MQ_CLK_CSI1_PHY_REF_DIV 362
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/* CSI_ESC */
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#define IMX8MQ_CLK_CSI1_ESC_SRC 363
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#define IMX8MQ_CLK_CSI1_ESC_CG 364
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#define IMX8MQ_CLK_CSI1_ESC_PRE_DIV 365
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#define IMX8MQ_CLK_CSI1_ESC_DIV 366
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/* CSI2_CORE */
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#define IMX8MQ_CLK_CSI2_CORE_SRC 367
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#define IMX8MQ_CLK_CSI2_CORE_CG 368
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#define IMX8MQ_CLK_CSI2_CORE_PRE_DIV 369
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#define IMX8MQ_CLK_CSI2_CORE_DIV 370
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/* CSI2_PHY */
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#define IMX8MQ_CLK_CSI2_PHY_REF_SRC 371
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#define IMX8MQ_CLK_CSI2_PHY_REF_CG 372
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#define IMX8MQ_CLK_CSI2_PHY_REF_PRE_DIV 373
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#define IMX8MQ_CLK_CSI2_PHY_REF_DIV 374
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/* CSI2_ESC */
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#define IMX8MQ_CLK_CSI2_ESC_SRC 375
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#define IMX8MQ_CLK_CSI2_ESC_CG 376
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#define IMX8MQ_CLK_CSI2_ESC_PRE_DIV 377
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#define IMX8MQ_CLK_CSI2_ESC_DIV 378
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/* PCIE2_CTRL */
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#define IMX8MQ_CLK_PCIE2_CTRL_SRC 379
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#define IMX8MQ_CLK_PCIE2_CTRL_CG 380
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#define IMX8MQ_CLK_PCIE2_CTRL_PRE_DIV 381
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#define IMX8MQ_CLK_PCIE2_CTRL_DIV 382
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/* PCIE2_PHY */
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#define IMX8MQ_CLK_PCIE2_PHY_SRC 383
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#define IMX8MQ_CLK_PCIE2_PHY_CG 384
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#define IMX8MQ_CLK_PCIE2_PHY_PRE_DIV 385
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#define IMX8MQ_CLK_PCIE2_PHY_DIV 386
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/* PCIE2_AUX */
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#define IMX8MQ_CLK_PCIE2_AUX_SRC 387
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#define IMX8MQ_CLK_PCIE2_AUX_CG 388
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#define IMX8MQ_CLK_PCIE2_AUX_PRE_DIV 389
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#define IMX8MQ_CLK_PCIE2_AUX_DIV 390
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/* ECSPI3 */
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#define IMX8MQ_CLK_ECSPI3_SRC 391
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#define IMX8MQ_CLK_ECSPI3_CG 392
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#define IMX8MQ_CLK_ECSPI3_PRE_DIV 393
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#define IMX8MQ_CLK_ECSPI3_DIV 394
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/* CCGR clocks */
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#define IMX8MQ_CLK_A53_ROOT 395
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#define IMX8MQ_CLK_DRAM_ROOT 396
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#define IMX8MQ_CLK_ECSPI1_ROOT 397
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#define IMX8MQ_CLK_ECSPI2_ROOT 398
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#define IMX8MQ_CLK_ECSPI3_ROOT 399
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#define IMX8MQ_CLK_ENET1_ROOT 400
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#define IMX8MQ_CLK_GPT1_ROOT 401
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#define IMX8MQ_CLK_I2C1_ROOT 402
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#define IMX8MQ_CLK_I2C2_ROOT 403
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#define IMX8MQ_CLK_I2C3_ROOT 404
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#define IMX8MQ_CLK_I2C4_ROOT 405
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#define IMX8MQ_CLK_M4_ROOT 406
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#define IMX8MQ_CLK_PCIE1_ROOT 407
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#define IMX8MQ_CLK_PCIE2_ROOT 408
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#define IMX8MQ_CLK_PWM1_ROOT 409
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#define IMX8MQ_CLK_PWM2_ROOT 410
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#define IMX8MQ_CLK_PWM3_ROOT 411
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#define IMX8MQ_CLK_PWM4_ROOT 412
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#define IMX8MQ_CLK_QSPI_ROOT 413
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#define IMX8MQ_CLK_SAI1_ROOT 414
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#define IMX8MQ_CLK_SAI2_ROOT 415
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#define IMX8MQ_CLK_SAI3_ROOT 416
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#define IMX8MQ_CLK_SAI4_ROOT 417
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#define IMX8MQ_CLK_SAI5_ROOT 418
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#define IMX8MQ_CLK_SAI6_ROOT 419
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#define IMX8MQ_CLK_UART1_ROOT 420
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#define IMX8MQ_CLK_UART2_ROOT 421
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#define IMX8MQ_CLK_UART3_ROOT 422
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#define IMX8MQ_CLK_UART4_ROOT 423
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#define IMX8MQ_CLK_USB1_CTRL_ROOT 424
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#define IMX8MQ_CLK_USB2_CTRL_ROOT 425
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#define IMX8MQ_CLK_USB1_PHY_ROOT 426
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#define IMX8MQ_CLK_USB2_PHY_ROOT 427
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#define IMX8MQ_CLK_USDHC1_ROOT 428
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#define IMX8MQ_CLK_USDHC2_ROOT 429
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#define IMX8MQ_CLK_WDOG1_ROOT 430
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#define IMX8MQ_CLK_WDOG2_ROOT 431
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#define IMX8MQ_CLK_WDOG3_ROOT 432
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#define IMX8MQ_CLK_GPU_ROOT 433
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#define IMX8MQ_CLK_HEVC_ROOT 434
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#define IMX8MQ_CLK_AVC_ROOT 435
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#define IMX8MQ_CLK_VP9_ROOT 436
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#define IMX8MQ_CLK_HEVC_INTER_ROOT 437
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#define IMX8MQ_CLK_DISP_ROOT 438
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#define IMX8MQ_CLK_HDMI_ROOT 439
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#define IMX8MQ_CLK_HDMI_PHY_ROOT 440
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#define IMX8MQ_CLK_VPU_DEC_ROOT 441
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#define IMX8MQ_CLK_CSI1_ROOT 442
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#define IMX8MQ_CLK_CSI2_ROOT 443
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#define IMX8MQ_CLK_RAWNAND_ROOT 444
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#define IMX8MQ_CLK_SDMA1_ROOT 445
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#define IMX8MQ_CLK_SDMA2_ROOT 446
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#define IMX8MQ_CLK_VPU_G1_ROOT 447
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#define IMX8MQ_CLK_VPU_G2_ROOT 448
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/* SCCG PLL GATE */
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#define IMX8MQ_SYS1_PLL_OUT 449
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#define IMX8MQ_SYS2_PLL_OUT 450
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#define IMX8MQ_SYS3_PLL_OUT 451
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#define IMX8MQ_DRAM_PLL_OUT 452
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#define IMX8MQ_GPT_3M_CLK 453
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#define IMX8MQ_CLK_IPG_ROOT 454
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#define IMX8MQ_CLK_IPG_AUDIO_ROOT 455
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#define IMX8MQ_CLK_SAI1_IPG 456
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#define IMX8MQ_CLK_SAI2_IPG 457
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#define IMX8MQ_CLK_SAI3_IPG 458
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#define IMX8MQ_CLK_SAI4_IPG 459
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#define IMX8MQ_CLK_SAI5_IPG 460
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#define IMX8MQ_CLK_SAI6_IPG 461
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/* DSI AHB/IPG clocks */
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/* rxesc clock */
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#define IMX8MQ_CLK_DSI_AHB_SRC 462
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#define IMX8MQ_CLK_DSI_AHB_CG 463
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#define IMX8MQ_CLK_DSI_AHB_PRE_DIV 464
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#define IMX8MQ_CLK_DSI_AHB_DIV 465
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/* txesc clock */
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#define IMX8MQ_CLK_DSI_IPG_DIV 466
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/* VIDEO2 PLL */
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#define IMX8MQ_VIDEO2_PLL1_REF_SEL 467
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#define IMX8MQ_VIDEO2_PLL1_REF_DIV 468
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#define IMX8MQ_VIDEO2_PLL1 469
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#define IMX8MQ_VIDEO2_PLL1_OUT 470
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#define IMX8MQ_VIDEO2_PLL1_OUT_DIV 471
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#define IMX8MQ_VIDEO2_PLL2 472
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#define IMX8MQ_VIDEO2_PLL2_DIV 473
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#define IMX8MQ_VIDEO2_PLL2_OUT 474
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#define IMX8MQ_CLK_TMU_ROOT 475
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#define IMX8MQ_CLK_END 476
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#endif /* __DT_BINDINGS_CLOCK_IMX8MQ_H */
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