/*
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* Copyright 2016 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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#ifdef DRV_AMDGPU
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#include <amdgpu.h>
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#include <amdgpu_drm.h>
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#include <errno.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include <sys/mman.h>
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#include <xf86drm.h>
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#include "dri.h"
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#include "drv_priv.h"
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#include "helpers.h"
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#include "util.h"
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#ifdef __ANDROID__
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#define DRI_PATH "/vendor/lib/dri/radeonsi_dri.so"
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#else
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#define DRI_PATH "/usr/lib64/dri/radeonsi_dri.so"
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#endif
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#define TILE_TYPE_LINEAR 0
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/* DRI backend decides tiling in this case. */
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#define TILE_TYPE_DRI 1
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struct amdgpu_priv {
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struct dri_driver dri;
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int drm_version;
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};
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const static uint32_t render_target_formats[] = { DRM_FORMAT_ABGR8888, DRM_FORMAT_ARGB8888,
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DRM_FORMAT_RGB565, DRM_FORMAT_XBGR8888,
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DRM_FORMAT_XRGB8888 };
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const static uint32_t texture_source_formats[] = { DRM_FORMAT_BGR888, DRM_FORMAT_GR88,
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DRM_FORMAT_R8, DRM_FORMAT_NV21,
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DRM_FORMAT_NV12, DRM_FORMAT_YVU420_ANDROID };
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static int amdgpu_init(struct driver *drv)
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{
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struct amdgpu_priv *priv;
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drmVersionPtr drm_version;
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struct format_metadata metadata;
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uint64_t use_flags = BO_USE_RENDER_MASK;
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priv = calloc(1, sizeof(struct amdgpu_priv));
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if (!priv)
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return -ENOMEM;
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drm_version = drmGetVersion(drv_get_fd(drv));
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if (!drm_version) {
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free(priv);
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return -ENODEV;
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}
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priv->drm_version = drm_version->version_minor;
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drmFreeVersion(drm_version);
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drv->priv = priv;
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if (dri_init(drv, DRI_PATH, "radeonsi")) {
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free(priv);
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drv->priv = NULL;
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return -ENODEV;
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}
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metadata.tiling = TILE_TYPE_LINEAR;
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metadata.priority = 1;
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metadata.modifier = DRM_FORMAT_MOD_LINEAR;
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drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
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&metadata, use_flags);
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drv_add_combinations(drv, texture_source_formats, ARRAY_SIZE(texture_source_formats),
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&metadata, BO_USE_TEXTURE_MASK);
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/* Linear formats supported by display. */
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drv_modify_combination(drv, DRM_FORMAT_ARGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT);
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drv_modify_combination(drv, DRM_FORMAT_XRGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT);
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drv_modify_combination(drv, DRM_FORMAT_XBGR8888, &metadata, BO_USE_SCANOUT);
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/* YUV formats for camera and display. */
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drv_modify_combination(drv, DRM_FORMAT_NV12, &metadata,
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BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE | BO_USE_SCANOUT);
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drv_modify_combination(drv, DRM_FORMAT_NV21, &metadata, BO_USE_SCANOUT);
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/*
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* R8 format is used for Android's HAL_PIXEL_FORMAT_BLOB and is used for JPEG snapshots
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* from camera.
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*/
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drv_modify_combination(drv, DRM_FORMAT_R8, &metadata,
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BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE);
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/*
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* The following formats will be allocated by the DRI backend and may be potentially tiled.
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* Since format modifier support hasn't been implemented fully yet, it's not
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* possible to enumerate the different types of buffers (like i915 can).
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*/
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use_flags &= ~BO_USE_RENDERSCRIPT;
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use_flags &= ~BO_USE_SW_WRITE_OFTEN;
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use_flags &= ~BO_USE_SW_READ_OFTEN;
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use_flags &= ~BO_USE_LINEAR;
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metadata.tiling = TILE_TYPE_DRI;
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metadata.priority = 2;
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drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
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&metadata, use_flags);
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/* Potentially tiled formats supported by display. */
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drv_modify_combination(drv, DRM_FORMAT_ARGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT);
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drv_modify_combination(drv, DRM_FORMAT_XRGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT);
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drv_modify_combination(drv, DRM_FORMAT_XBGR8888, &metadata, BO_USE_SCANOUT);
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return 0;
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}
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static void amdgpu_close(struct driver *drv)
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{
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dri_close(drv);
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free(drv->priv);
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drv->priv = NULL;
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}
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static int amdgpu_create_bo(struct bo *bo, uint32_t width, uint32_t height, uint32_t format,
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uint64_t use_flags)
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{
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int ret;
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uint32_t plane, stride;
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struct combination *combo;
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union drm_amdgpu_gem_create gem_create;
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struct amdgpu_priv *priv = bo->drv->priv;
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combo = drv_get_combination(bo->drv, format, use_flags);
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if (!combo)
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return -EINVAL;
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if (combo->metadata.tiling == TILE_TYPE_DRI)
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return dri_bo_create(bo, width, height, format, use_flags);
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stride = drv_stride_from_format(format, width, 0);
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if (format == DRM_FORMAT_YVU420_ANDROID)
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stride = ALIGN(stride, 128);
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else
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stride = ALIGN(stride, 64);
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drv_bo_from_format(bo, stride, height, format);
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memset(&gem_create, 0, sizeof(gem_create));
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gem_create.in.bo_size = bo->total_size;
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gem_create.in.alignment = 256;
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gem_create.in.domain_flags = 0;
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if (use_flags & (BO_USE_LINEAR | BO_USE_SW))
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gem_create.in.domain_flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
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gem_create.in.domains = AMDGPU_GEM_DOMAIN_GTT;
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if (!(use_flags & (BO_USE_SW_READ_OFTEN | BO_USE_SCANOUT)))
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gem_create.in.domain_flags |= AMDGPU_GEM_CREATE_CPU_GTT_USWC;
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/* If drm_version >= 21 everything exposes explicit synchronization primitives
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and chromeos/arc++ will use them. Disable implicit synchronization. */
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if (priv->drm_version >= 21) {
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gem_create.in.domain_flags |= AMDGPU_GEM_CREATE_EXPLICIT_SYNC;
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}
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/* Allocate the buffer with the preferred heap. */
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ret = drmCommandWriteRead(drv_get_fd(bo->drv), DRM_AMDGPU_GEM_CREATE, &gem_create,
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sizeof(gem_create));
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if (ret < 0)
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return ret;
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for (plane = 0; plane < bo->num_planes; plane++)
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bo->handles[plane].u32 = gem_create.out.handle;
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return 0;
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}
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static int amdgpu_import_bo(struct bo *bo, struct drv_import_fd_data *data)
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{
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struct combination *combo;
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combo = drv_get_combination(bo->drv, data->format, data->use_flags);
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if (!combo)
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return -EINVAL;
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if (combo->metadata.tiling == TILE_TYPE_DRI)
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return dri_bo_import(bo, data);
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else
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return drv_prime_bo_import(bo, data);
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}
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static int amdgpu_destroy_bo(struct bo *bo)
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{
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if (bo->priv)
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return dri_bo_destroy(bo);
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else
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return drv_gem_bo_destroy(bo);
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}
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static void *amdgpu_map_bo(struct bo *bo, struct vma *vma, size_t plane, uint32_t map_flags)
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{
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int ret;
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union drm_amdgpu_gem_mmap gem_map;
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if (bo->priv)
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return dri_bo_map(bo, vma, plane, map_flags);
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memset(&gem_map, 0, sizeof(gem_map));
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gem_map.in.handle = bo->handles[plane].u32;
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ret = drmIoctl(bo->drv->fd, DRM_IOCTL_AMDGPU_GEM_MMAP, &gem_map);
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if (ret) {
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drv_log("DRM_IOCTL_AMDGPU_GEM_MMAP failed\n");
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return MAP_FAILED;
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}
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vma->length = bo->total_size;
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return mmap(0, bo->total_size, drv_get_prot(map_flags), MAP_SHARED, bo->drv->fd,
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gem_map.out.addr_ptr);
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}
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static int amdgpu_unmap_bo(struct bo *bo, struct vma *vma)
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{
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if (bo->priv)
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return dri_bo_unmap(bo, vma);
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else
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return munmap(vma->addr, vma->length);
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}
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static uint32_t amdgpu_resolve_format(uint32_t format, uint64_t use_flags)
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{
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switch (format) {
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case DRM_FORMAT_FLEX_IMPLEMENTATION_DEFINED:
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/* Camera subsystem requires NV12. */
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if (use_flags & (BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE))
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return DRM_FORMAT_NV12;
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/*HACK: See b/28671744 */
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return DRM_FORMAT_XBGR8888;
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case DRM_FORMAT_FLEX_YCbCr_420_888:
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return DRM_FORMAT_NV12;
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default:
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return format;
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}
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}
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const struct backend backend_amdgpu = {
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.name = "amdgpu",
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.init = amdgpu_init,
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.close = amdgpu_close,
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.bo_create = amdgpu_create_bo,
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.bo_destroy = amdgpu_destroy_bo,
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.bo_import = amdgpu_import_bo,
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.bo_map = amdgpu_map_bo,
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.bo_unmap = amdgpu_unmap_bo,
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.resolve_format = amdgpu_resolve_format,
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};
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#endif
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