/*
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* Copyright 2014 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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#ifdef DRV_TEGRA
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#include <assert.h>
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#include <stdio.h>
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#include <string.h>
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#include <sys/mman.h>
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#include <tegra_drm.h>
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#include <xf86drm.h>
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#include "drv_priv.h"
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#include "helpers.h"
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#include "util.h"
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/*
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* GOB (Group Of Bytes) is the basic unit of the blocklinear layout.
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* GOBs are arranged to blocks, where the height of the block (measured
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* in GOBs) is configurable.
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*/
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#define NV_BLOCKLINEAR_GOB_HEIGHT 8
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#define NV_BLOCKLINEAR_GOB_WIDTH 64
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#define NV_DEFAULT_BLOCK_HEIGHT_LOG2 4
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#define NV_PREFERRED_PAGE_SIZE (128 * 1024)
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// clang-format off
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enum nv_mem_kind
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{
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NV_MEM_KIND_PITCH = 0,
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NV_MEM_KIND_C32_2CRA = 0xdb,
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NV_MEM_KIND_GENERIC_16Bx2 = 0xfe,
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};
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enum tegra_map_type {
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TEGRA_READ_TILED_BUFFER = 0,
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TEGRA_WRITE_TILED_BUFFER = 1,
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};
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// clang-format on
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struct tegra_private_map_data {
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void *tiled;
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void *untiled;
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};
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static const uint32_t render_target_formats[] = { DRM_FORMAT_ARGB8888, DRM_FORMAT_XRGB8888 };
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static int compute_block_height_log2(int height)
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{
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int block_height_log2 = NV_DEFAULT_BLOCK_HEIGHT_LOG2;
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if (block_height_log2 > 0) {
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/* Shrink, if a smaller block height could cover the whole
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* surface height. */
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int proposed = NV_BLOCKLINEAR_GOB_HEIGHT << (block_height_log2 - 1);
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while (proposed >= height) {
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block_height_log2--;
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if (block_height_log2 == 0)
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break;
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proposed /= 2;
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}
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}
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return block_height_log2;
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}
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static void compute_layout_blocklinear(int width, int height, int format, enum nv_mem_kind *kind,
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uint32_t *block_height_log2, uint32_t *stride,
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uint32_t *size)
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{
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int pitch = drv_stride_from_format(format, width, 0);
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/* Align to blocklinear blocks. */
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pitch = ALIGN(pitch, NV_BLOCKLINEAR_GOB_WIDTH);
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/* Compute padded height. */
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*block_height_log2 = compute_block_height_log2(height);
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int block_height = 1 << *block_height_log2;
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int padded_height = ALIGN(height, NV_BLOCKLINEAR_GOB_HEIGHT * block_height);
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int bytes = pitch * padded_height;
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/* Pad the allocation to the preferred page size.
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* This will reduce the required page table size (see discussion in NV
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* bug 1321091), and also acts as a WAR for NV bug 1325421.
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*/
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bytes = ALIGN(bytes, NV_PREFERRED_PAGE_SIZE);
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*kind = NV_MEM_KIND_C32_2CRA;
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*stride = pitch;
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*size = bytes;
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}
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static void compute_layout_linear(int width, int height, int format, uint32_t *stride,
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uint32_t *size)
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{
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*stride = ALIGN(drv_stride_from_format(format, width, 0), 64);
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*size = *stride * height;
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}
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static void transfer_tile(struct bo *bo, uint8_t *tiled, uint8_t *untiled, enum tegra_map_type type,
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uint32_t bytes_per_pixel, uint32_t gob_top, uint32_t gob_left,
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uint32_t gob_size_pixels, uint8_t *tiled_last)
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{
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uint8_t *tmp;
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uint32_t x, y, k;
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for (k = 0; k < gob_size_pixels; k++) {
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/*
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* Given the kth pixel starting from the tile specified by
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* gob_top and gob_left, unswizzle to get the standard (x, y)
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* representation.
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*/
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x = gob_left + (((k >> 3) & 8) | ((k >> 1) & 4) | (k & 3));
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y = gob_top + ((k >> 7 << 3) | ((k >> 3) & 6) | ((k >> 2) & 1));
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if (tiled >= tiled_last)
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return;
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if (x >= bo->width || y >= bo->height) {
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tiled += bytes_per_pixel;
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continue;
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}
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tmp = untiled + y * bo->strides[0] + x * bytes_per_pixel;
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if (type == TEGRA_READ_TILED_BUFFER)
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memcpy(tmp, tiled, bytes_per_pixel);
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else if (type == TEGRA_WRITE_TILED_BUFFER)
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memcpy(tiled, tmp, bytes_per_pixel);
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/* Move on to next pixel. */
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tiled += bytes_per_pixel;
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}
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}
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static void transfer_tiled_memory(struct bo *bo, uint8_t *tiled, uint8_t *untiled,
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enum tegra_map_type type)
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{
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uint32_t gob_width, gob_height, gob_size_bytes, gob_size_pixels, gob_count_x, gob_count_y,
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gob_top, gob_left;
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uint32_t i, j, offset;
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uint8_t *tmp, *tiled_last;
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uint32_t bytes_per_pixel = drv_stride_from_format(bo->format, 1, 0);
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/*
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* The blocklinear format consists of 8*(2^n) x 64 byte sized tiles,
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* where 0 <= n <= 4.
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*/
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gob_width = DIV_ROUND_UP(NV_BLOCKLINEAR_GOB_WIDTH, bytes_per_pixel);
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gob_height = NV_BLOCKLINEAR_GOB_HEIGHT * (1 << NV_DEFAULT_BLOCK_HEIGHT_LOG2);
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/* Calculate the height from maximum possible gob height */
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while (gob_height > NV_BLOCKLINEAR_GOB_HEIGHT && gob_height >= 2 * bo->height)
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gob_height /= 2;
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gob_size_bytes = gob_height * NV_BLOCKLINEAR_GOB_WIDTH;
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gob_size_pixels = gob_height * gob_width;
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gob_count_x = DIV_ROUND_UP(bo->strides[0], NV_BLOCKLINEAR_GOB_WIDTH);
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gob_count_y = DIV_ROUND_UP(bo->height, gob_height);
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tiled_last = tiled + bo->total_size;
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offset = 0;
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for (j = 0; j < gob_count_y; j++) {
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gob_top = j * gob_height;
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for (i = 0; i < gob_count_x; i++) {
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tmp = tiled + offset;
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gob_left = i * gob_width;
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transfer_tile(bo, tmp, untiled, type, bytes_per_pixel, gob_top, gob_left,
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gob_size_pixels, tiled_last);
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offset += gob_size_bytes;
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}
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}
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}
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static int tegra_init(struct driver *drv)
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{
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struct format_metadata metadata;
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uint64_t use_flags = BO_USE_RENDER_MASK;
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metadata.tiling = NV_MEM_KIND_PITCH;
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metadata.priority = 1;
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metadata.modifier = DRM_FORMAT_MOD_LINEAR;
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drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
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&metadata, use_flags);
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drv_modify_combination(drv, DRM_FORMAT_XRGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT);
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drv_modify_combination(drv, DRM_FORMAT_ARGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT);
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use_flags &= ~BO_USE_SW_WRITE_OFTEN;
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use_flags &= ~BO_USE_SW_READ_OFTEN;
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use_flags &= ~BO_USE_LINEAR;
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metadata.tiling = NV_MEM_KIND_C32_2CRA;
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metadata.priority = 2;
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drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
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&metadata, use_flags);
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drv_modify_combination(drv, DRM_FORMAT_XRGB8888, &metadata, BO_USE_SCANOUT);
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drv_modify_combination(drv, DRM_FORMAT_ARGB8888, &metadata, BO_USE_SCANOUT);
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return 0;
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}
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static int tegra_bo_create(struct bo *bo, uint32_t width, uint32_t height, uint32_t format,
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uint64_t use_flags)
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{
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uint32_t size, stride, block_height_log2 = 0;
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enum nv_mem_kind kind = NV_MEM_KIND_PITCH;
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struct drm_tegra_gem_create gem_create;
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int ret;
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if (use_flags &
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(BO_USE_CURSOR | BO_USE_LINEAR | BO_USE_SW_READ_OFTEN | BO_USE_SW_WRITE_OFTEN))
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compute_layout_linear(width, height, format, &stride, &size);
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else
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compute_layout_blocklinear(width, height, format, &kind, &block_height_log2,
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&stride, &size);
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memset(&gem_create, 0, sizeof(gem_create));
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gem_create.size = size;
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gem_create.flags = 0;
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ret = drmIoctl(bo->drv->fd, DRM_IOCTL_TEGRA_GEM_CREATE, &gem_create);
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if (ret) {
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drv_log("DRM_IOCTL_TEGRA_GEM_CREATE failed (size=%zu)\n", size);
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return ret;
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}
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bo->handles[0].u32 = gem_create.handle;
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bo->offsets[0] = 0;
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bo->total_size = bo->sizes[0] = size;
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bo->strides[0] = stride;
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if (kind != NV_MEM_KIND_PITCH) {
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struct drm_tegra_gem_set_tiling gem_tile;
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memset(&gem_tile, 0, sizeof(gem_tile));
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gem_tile.handle = bo->handles[0].u32;
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gem_tile.mode = DRM_TEGRA_GEM_TILING_MODE_BLOCK;
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gem_tile.value = block_height_log2;
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ret = drmCommandWriteRead(bo->drv->fd, DRM_TEGRA_GEM_SET_TILING, &gem_tile,
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sizeof(gem_tile));
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if (ret < 0) {
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drv_gem_bo_destroy(bo);
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return ret;
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}
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/* Encode blocklinear parameters for EGLImage creation. */
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bo->tiling = (kind & 0xff) | ((block_height_log2 & 0xf) << 8);
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bo->format_modifiers[0] = fourcc_mod_code(NV, bo->tiling);
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}
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return 0;
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}
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static int tegra_bo_import(struct bo *bo, struct drv_import_fd_data *data)
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{
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int ret;
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struct drm_tegra_gem_get_tiling gem_get_tiling;
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ret = drv_prime_bo_import(bo, data);
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if (ret)
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return ret;
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/* TODO(gsingh): export modifiers and get rid of backdoor tiling. */
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memset(&gem_get_tiling, 0, sizeof(gem_get_tiling));
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gem_get_tiling.handle = bo->handles[0].u32;
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ret = drmIoctl(bo->drv->fd, DRM_IOCTL_TEGRA_GEM_GET_TILING, &gem_get_tiling);
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if (ret) {
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drv_gem_bo_destroy(bo);
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return ret;
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}
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/* NOTE(djmk): we only know about one tiled format, so if our drmIoctl call tells us we are
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tiled, assume it is this format (NV_MEM_KIND_C32_2CRA) otherwise linear (KIND_PITCH). */
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if (gem_get_tiling.mode == DRM_TEGRA_GEM_TILING_MODE_PITCH) {
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bo->tiling = NV_MEM_KIND_PITCH;
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} else if (gem_get_tiling.mode == DRM_TEGRA_GEM_TILING_MODE_BLOCK) {
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bo->tiling = NV_MEM_KIND_C32_2CRA;
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} else {
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drv_log("%s: unknown tile format %d\n", __func__, gem_get_tiling.mode);
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drv_gem_bo_destroy(bo);
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assert(0);
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}
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bo->format_modifiers[0] = fourcc_mod_code(NV, bo->tiling);
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return 0;
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}
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static void *tegra_bo_map(struct bo *bo, struct vma *vma, size_t plane, uint32_t map_flags)
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{
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int ret;
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struct drm_tegra_gem_mmap gem_map;
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struct tegra_private_map_data *priv;
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memset(&gem_map, 0, sizeof(gem_map));
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gem_map.handle = bo->handles[0].u32;
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ret = drmCommandWriteRead(bo->drv->fd, DRM_TEGRA_GEM_MMAP, &gem_map, sizeof(gem_map));
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if (ret < 0) {
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drv_log("DRM_TEGRA_GEM_MMAP failed\n");
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return MAP_FAILED;
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}
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void *addr = mmap(0, bo->total_size, drv_get_prot(map_flags), MAP_SHARED, bo->drv->fd,
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gem_map.offset);
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vma->length = bo->total_size;
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if ((bo->tiling & 0xFF) == NV_MEM_KIND_C32_2CRA && addr != MAP_FAILED) {
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priv = calloc(1, sizeof(*priv));
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priv->untiled = calloc(1, bo->total_size);
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priv->tiled = addr;
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vma->priv = priv;
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transfer_tiled_memory(bo, priv->tiled, priv->untiled, TEGRA_READ_TILED_BUFFER);
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addr = priv->untiled;
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}
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return addr;
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}
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static int tegra_bo_unmap(struct bo *bo, struct vma *vma)
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{
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if (vma->priv) {
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struct tegra_private_map_data *priv = vma->priv;
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vma->addr = priv->tiled;
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free(priv->untiled);
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free(priv);
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vma->priv = NULL;
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}
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return munmap(vma->addr, vma->length);
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}
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static int tegra_bo_flush(struct bo *bo, struct mapping *mapping)
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{
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struct tegra_private_map_data *priv = mapping->vma->priv;
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if (priv && (mapping->vma->map_flags & BO_MAP_WRITE))
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transfer_tiled_memory(bo, priv->tiled, priv->untiled, TEGRA_WRITE_TILED_BUFFER);
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return 0;
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}
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const struct backend backend_tegra = {
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.name = "tegra",
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.init = tegra_init,
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.bo_create = tegra_bo_create,
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.bo_destroy = drv_gem_bo_destroy,
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.bo_import = tegra_bo_import,
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.bo_map = tegra_bo_map,
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.bo_unmap = tegra_bo_unmap,
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.bo_flush = tegra_bo_flush,
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};
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#endif
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