/******************************************************************************/
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#ifdef JEMALLOC_H_TYPES
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#endif /* JEMALLOC_H_TYPES */
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/******************************************************************************/
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#ifdef JEMALLOC_H_STRUCTS
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#endif /* JEMALLOC_H_STRUCTS */
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/******************************************************************************/
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#ifdef JEMALLOC_H_EXTERNS
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#endif /* JEMALLOC_H_EXTERNS */
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/******************************************************************************/
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#ifdef JEMALLOC_H_INLINES
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#ifndef JEMALLOC_ENABLE_INLINE
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void mb_write(void);
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#endif
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#if (defined(JEMALLOC_ENABLE_INLINE) || defined(JEMALLOC_MB_C_))
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#ifdef __i386__
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/*
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* According to the Intel Architecture Software Developer's Manual, current
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* processors execute instructions in order from the perspective of other
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* processors in a multiprocessor system, but 1) Intel reserves the right to
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* change that, and 2) the compiler's optimizer could re-order instructions if
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* there weren't some form of barrier. Therefore, even if running on an
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* architecture that does not need memory barriers (everything through at least
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* i686), an "optimizer barrier" is necessary.
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*/
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JEMALLOC_INLINE void
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mb_write(void)
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{
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# if 0
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/* This is a true memory barrier. */
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asm volatile ("pusha;"
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"xor %%eax,%%eax;"
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"cpuid;"
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"popa;"
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: /* Outputs. */
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: /* Inputs. */
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: "memory" /* Clobbers. */
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);
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# else
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/*
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* This is hopefully enough to keep the compiler from reordering
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* instructions around this one.
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*/
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asm volatile ("nop;"
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: /* Outputs. */
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: /* Inputs. */
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: "memory" /* Clobbers. */
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);
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# endif
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}
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#elif (defined(__amd64__) || defined(__x86_64__))
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JEMALLOC_INLINE void
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mb_write(void)
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{
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asm volatile ("sfence"
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: /* Outputs. */
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: /* Inputs. */
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: "memory" /* Clobbers. */
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);
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}
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#elif defined(__powerpc__)
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JEMALLOC_INLINE void
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mb_write(void)
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{
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asm volatile ("eieio"
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: /* Outputs. */
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: /* Inputs. */
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: "memory" /* Clobbers. */
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);
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}
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#elif defined(__sparc64__)
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JEMALLOC_INLINE void
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mb_write(void)
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{
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asm volatile ("membar #StoreStore"
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: /* Outputs. */
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: /* Inputs. */
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: "memory" /* Clobbers. */
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);
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}
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#elif defined(__tile__)
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JEMALLOC_INLINE void
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mb_write(void)
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{
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__sync_synchronize();
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}
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#else
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/*
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* This is much slower than a simple memory barrier, but the semantics of mutex
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* unlock make this work.
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*/
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JEMALLOC_INLINE void
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mb_write(void)
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{
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malloc_mutex_t mtx;
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malloc_mutex_init(&mtx, "mb", WITNESS_RANK_OMIT);
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malloc_mutex_lock(TSDN_NULL, &mtx);
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malloc_mutex_unlock(TSDN_NULL, &mtx);
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}
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#endif
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#endif
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#endif /* JEMALLOC_H_INLINES */
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/******************************************************************************/
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